Important notice
Dear Customer,
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tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
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In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
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Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use http://www.nexperia.com
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Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
- © Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and
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Kind regards,
Team Nexperia
PH9030L
N-channel TrenchMOS logic level FET
Rev. 01 — 29 July 2008
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses
Suitable for logic level gate drive
sources
1.3 Applications
DC-to-DC convertors
Portable equipment
Notebook computers
Switched-mode power supplies
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage 25 °C ≤ Tj ≤ 150 °C
-
-
30
V
ID
drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1; see Figure 3
-
-
63
A
Ptot
total power
dissipation
Tmb = 25 °C; see Figure 2
-
-
62.5
W
VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 10;
see Figure 11
-
3.2
-
nC
VGS = 10 V; ID = 25 A;
Tj = 25 °C; see Figure 8; see
Figure 9
-
7
9
mΩ
Dynamic characteristics
QGD
gate-drain charge
Static characteristics
RDSon
drain-source
on-state resistance
PH9030L
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pinning information
Pin
Symbol
Description
Simplified outline
1,2,3
S
source
4
G
gate
mb
D
mounting base; connected to
drain
Graphic symbol
D
mb
G
mbb076
S
1 2 3 4
SOT669
(LFPAK)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
PH9030L
LFPAK
Description
Version
Plastic single-ended surface-mounted package (LFPAK); SOT669
4 leads
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 150 °C
-
30
V
VDGR
drain-gate voltage
25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ
VGS
gate-source voltage
ID
drain current
-
30
V
-20
20
V
VGS = 10 V; Tj = 100 °C; see Figure 1
-
39
A
VGS = 10 V; Tmb = 25 °C; see Figure 1;
see Figure 3
-
63
A
IDM
peak drain current
tp ≤ 10 µs; pulsed; Tmb = 25 °C; see
Figure 3
-
214
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
62.5
W
Tstg
storage temperature
-55
150
°C
Tj
junction temperature
-55
150
°C
Source-drain diode
IS
source current
Tmb = 25 °C
-
52
A
ISM
peak source current
tp ≤ 10 µs; pulsed; Tmb = 25 °C
-
208
A
VGS = 10 V; Tj(init) = 25 °C; ID = 33 A;
Vsup ≤ 30 V; unclamped; tp = 0.08 ms;
RGS = 50 Ω
-
53
mJ
Avalanche Ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
PH9030L_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 July 2008
2 of 12
PH9030L
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab757
120
003aab937
120
Ider
(%)
Pder
(%)
80
80
40
40
0
0
0
50
100
150
0
200
50
100
150
Tj (°C)
200
Tmb (°C)
Fig 1. Normalized continuous drain current as a
function of solder point temperature
Fig 2. Normalized total power dissipation as a
function of solder point temperature
003aab730
103
Limit RDSon = VDS / ID
ID
(A)
tp =10 μs
102
100 μs
1 ms
10
10 ms
100 ms
1
10−1
10−1
1
10
102
103
VDS (V)
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PH9030L_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 July 2008
3 of 12
PH9030L
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance
from junction to
mounting base
see Figure 4
-
-
2
K/W
003aab731
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
10−1
0.05
δ=
P
0.02
tp
T
single pulse
t
tp
10−2
10−5
T
10−4
10−3
10−2
10−1
1
10
tp (s)
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration
PH9030L_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 July 2008
4 of 12
PH9030L
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
ID = 250 µA; VGS = 0 V; Tj = 25 °C
30
-
-
V
ID = 250 µA; VGS = 0 V; Tj = -55 °C
27
-
-
V
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
VGS(th)
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C; see
voltage
Figure 6; see Figure 7
1.3
1.7
2
V
VGSth
gate-source threshold ID = 1 mA; VDS = VGS; Tj = -55 °C; see
voltage
Figure 7; see Figure 6
-
-
2.6
V
0.8
-
-
V
ID = 1 mA; VDS = VGS; Tj = 150 °C; see
Figure 7; see Figure 6
IDSS
drain leakage current
VDS = 30 V; VGS = 0 V; Tj = 25 °C
-
-
1
µA
IGSS
gate leakage current
VGS = 16 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = -16 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = 10 V; ID = 25 A; Tj = 150 °C; see
Figure 8; see Figure 9
-
11.9
15.8
mΩ
VGS = 4.5 V; ID = 25 A; Tj = 25 °C; see
Figure 8; see Figure 9
-
10
12.5
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C; see
Figure 8; see Figure 9
-
7
9
mΩ
RDSon
drain-source on-state
resistance
IDSS
drain leakage current
VDS = 30 V; VGS = 0 V; Tj = 150 °C
-
-
100
µA
RG
internal gate
resistance (AC)
f = 1 MHz
-
0.56
-
Ω
ID = 10 A; VDS = 12 V; VGS = 4.5 V; see
Figure 10; see Figure 11
-
13.3
-
nC
-
4.8
-
nC
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGD
gate-drain charge
-
3.2
-
nC
QGS(th)
pre-threshold
gate-source charge
-
1.8
-
nC
QGS(th-pl)
post-threshold
gate-source charge
-
3
-
nC
VGS(pl)
gate-source plateau
voltage
ID = 10 A; VDS = 12 V; see Figure 10; see
Figure 11
-
2.72
-
V
Ciss
input capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 12
-
1565
-
pF
VDS = 0 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C
-
1839
-
pF
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 12
-
355
-
pF
-
186
-
pF
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 5.6 Ω
-
20
-
ns
-
41
-
ns
-
15
-
ns
Coss
output capacitance
Crss
reverse transfer
capacitance
td(on)
turn-on delay time
tr
rise time
td(off)
turn-off delay time
PH9030L_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 July 2008
5 of 12
PH9030L
NXP Semiconductors
N-channel TrenchMOS logic level FET
Table 6.
Characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tf
fall time
VDS = 12 V; RL = 0.5 Ω; RL = 0.5 Ω;
VGS = 4.5 V; RG(ext) = 5.6 Ω
-
25
-
ns
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C; see
Figure 14
-
0.89
1.16
V
trr
reverse recovery time
-
43
-
ns
Qr
recovered charge
IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V;
VDS = 30 V
-
15
-
nC
003aab732
100
VGS (V) = 10
003aab271
10−3
5
ID
(A)
ID
(A)
4.5
75
10−4
50
max
typ
min
3.4
3.2
10−5
25
3.0
2.6
2.4
10−6
0
0
0.3
0.6
0.9
1.2
1.5
VDS (V)
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical
values
0
1
1.5
2
2.5
VGS (V)
Fig 6. Sub-threshold drain current as a function
of gate-source voltage
PH9030L_1
Product data sheet
0.5
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 July 2008
6 of 12
PH9030L
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab272
3
003aab733
25
VGS (V) = 3.2
RDSon
(mΩ)
VGS(th)
(V)
3.4
20
max
2
4.5
15
typ
1.5
min
5
10
1
10
5
0.5
0
-60
0
0
60
120
180
0
20
40
60
80
ID (A)
Tj (°C)
Fig 7. Gate-source threshold voltage as a
function of junction temperature
Fig 8. Drain-source on-state resistance as a
function of drain current; typical values
003aab467
2
VDS
a
ID
1.6
VGS(pl)
1.2
VGS(th)
VGS
0.8
QGS1
QGS2
QGS
0.4
QGD
QG(tot)
003aaa508
0
−60
0
60
120
180
Fig 10. Gate charge waveform definitions
Tj (°C)
Fig 9. Normalized drain-source on-state
resistance factor as a function of junction
temperature
PH9030L_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 July 2008
7 of 12
PH9030L
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab735
10
VGS
(V)
003aab737
104
VDS = 12 V
ID = 10 A
Tj = 25 °C
C
(pF)
7.5
Ciss
103
5
2.5
Coss
Crss
102
0
0
10
20
10−1
30
1
VDS (V)
Fig 11. Gate-source voltage as a function of gate
charge; typical values
003aab734
50
VDS > ID × RDSon
ID
(A)
102
10
QG (nC)
Fig 12. Input, output and reverse transfer
capacitances as a function of drain-source
voltage; typical values
003aab736
80
IS
(A)
40
60
30
40
20
Tj = 150 °C
25 °C
Tj = 150 °C
25 °C
20
10
0
0
0
1
2
3
4
0
Fig 13. Transfer characteristics: drain current as a
function of gate-source voltage; typical
values
0.6
0.9
1.2
Fig 14. Source current as a function of
source-drain voltage; typical values
PH9030L_1
Product data sheet
0.3
VSD (V)
VGS (V)
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 July 2008
8 of 12
PH9030L
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads
A2
A
E
SOT669
C
c2
b2
E1
b3
L1
mounting
base
b4
D1
D
H
L2
1
2
3
e
4
w M A
b
1/2
X
c
e
A
(A 3)
A1
C
θ
L
detail X
y C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
A1
A2
A3
b
b2
1.20 0.15 1.10
0.50 4.41
0.25
1.01 0.00 0.95
0.35 3.62
b3
b4
2.2
2.0
0.9
0.7
c
D (1)
c2
D1(1)
E(1) E1(1)
max
0.25 0.30 4.10
4.20
0.19 0.24 3.80
5.0
4.8
3.3
3.1
e
H
L
L1
L2
w
y
θ
1.27
6.2
5.8
0.85
0.40
1.3
0.8
1.3
0.8
0.25
0.1
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT669
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-10-13
06-03-16
MO-235
Fig 15. Package outline SOT669 (LFPAK)
PH9030L_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 July 2008
9 of 12
PH9030L
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PH9030L_1
20080729
Product data sheet
-
-
PH9030L_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 July 2008
10 of 12
PH9030L
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status [1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term 'short data sheet' is explained in section "Definitions".
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PH9030L_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 July 2008
11 of 12
PH9030L
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1.
1.1
1.2
1.3
1.4
2.
3.
4.
5.
6.
7.
8.
9.
9.1
9.2
9.3
9.4
10.
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10
Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Contact information. . . . . . . . . . . . . . . . . . . . . . 11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 July 2008
Document identifier: PH9030L_1
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