ML9211

E2C0045-19-83 ¡ Semiconductor ¡ Semiconductor ML9211 GENERAL DESCRIPTION This version: Aug. 1999 ML9211 el Pr im in y ar 56-Bit Duplex/Triplex (1/2 duty / 1/3 duty) VF Controller/Driver with Digital Dimming The ML9211 is a full CMOS controller/driver for Duplex or Triplex (1/2 duty or 1/3 duty) vacuum fluorescent display tube. It consists of a 56-segment driver multiplexed to drive up to 168 segments, and 10-bit digital dimming circuit. ML9211 features a selection of a master mode and a slave mode, and therefore it can be used to expand segments for the VFD driver with keyscan and A/D converter function. ML9211 provides an interface with a microcontroller only by three signal lines: DATA IN, CLOCK and CS. FEATURES • Logic supply voltage (VDD) : 4.5 to 5.5V : 8 to 18V • Driver supply voltage (VDISP) • Duplex/Triplex (1/2 duty / 1/3 duty) selectable DUP/TRI=1/2 duty selectable at "H" level DUP/TRI=1/3 duty selectable at "L" level • Number of display segments Max. 112-segment display (during 1/2 duty mode) Max. 168-segment display (during 1/3 duty mode) • Master/Slave selectable M/S=Master mode selectable at "H" level M/S=Slave mode selectable at "L" level • Interface with a microcontroller Three lines: CS, CLOCK, and DATA IN • 56-segment driver outputs : IOH=–5mA at VOH=VDISP–0.8V (SEG1 to 37) (can be directly connected to VFD tube : IOH=–10mA at VOH=VDISP–0.8V (SEG38 to 56) and require no external resistors) : IOL=500mA at VOL=2V (SEG1 to 56) • 3-grid pre-driver outputs : IOH=–5.0mA at VOH=VDISP–0.8V (require external drivers) IOL=10mA at VOL=2V • Logic outputs : IOH=–200mA at VOH=VDD–0.8V IOL=200mA at VOL=0.8V • Built-in digital dimming circuit (10-bit resolution) • Built-in oscillation circuit (external R and C) • Built-in Power-On-Reset circuit • Package options: 80-pin plastic QFP (QFP80-P-1420-0.80-BK) Product name: ML9211GA 80-pin plastic QFP (QFP80-P-1414-0.65-K) Product name: ML9211GP 1/19 ¡ Semiconductor ML9211 BLOCK DIAGRAM GRID1 GRID2 GRID3 SEG1 SEG56 VDISP D-GND VDD L-GND 0H 56 Segment Driver 3 Grid pre Driver Power On Reset 4H POR Out1-56 168 to 56 Segment Control in1-56 in1-56 in1-56 1H Mode Select POR 0H POR in1-3 Out1-56 Segment Latch 1 in1-56 2H 0H POR Out1-56 Segment Latch 2 in1-56 3H 0H POR Out1-56 Segment Latch 3 in1-56 CS CLOCK DATA IN Control Out1-3 3bit Shift Register POR Out1-56 56bit Shift Register 4H POR in1-10 Dimming Latch Out1-10 POR OSC0 OSC POR 10bit Digital Dimming DIM IN SYNC IN1 SYNC IN2 M/S DUP/TRI Timing Generator DIM OUT SYNC OUT1 SYNC OUT2 2/19 ¡ Semiconductor ML9211 INPUT AND OUTPUT CONFIGURATION Schematic Diagram of Driver Output Circuit VDISP VDISP OUTPUT D-GND D-GND 3/19 ¡ Semiconductor ML9211 PIN CONFIGURATION (TOP VIEW) 78 SEG36 77 SEG35 76 SEG34 75 SEG33 74 SEG32 73 SEG31 72 SEG30 71 SEG29 70 SEG28 69 SEG27 68 SEG26 67 SEG25 66 SEG24 79 SEG37 80 VDISP 65 VDISP 64 SEG23 63 SEG22 62 SEG21 61 SEG20 60 SEG19 59 SEG18 58 SEG17 57 SEG16 56 SEG15 55 SEG14 54 SEG13 53 SEG12 52 SEG11 51 SEG10 50 SEG9 49 SEG8 48 SEG7 47 SEG6 46 SEG5 45 SEG4 44 SEG3 43 SEG2 42 SEG1 41 NC SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 GRID1 GRID2 GRID3 NC D-GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 DIM IN SYNC IN 1 SYNC IN 2 CS CLOCK DATA IN NC L-GND OSC0 DUP/TRI M/S SYNC OUT 2 SYNC OUT 1 DIM OUT D-GND NC: No connection 80-pin Plastic QFP (QFP80-P-1420-0.80-BK) 40 4/19 ¡ Semiconductor  SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 GRID1 GRID2 GRID3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ML9211 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SEG39 SEG38 VDISP SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 VDISP SEG23 SEG22 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 NC D-GND VDD DIM IN SYNC IN 1 SYNC IN 2 CS CLOCK DATA IN NC L-GND OSC0 DUP/TRI M/S SYNC OUT 2 SYNC OUT 1 DIM OUT D-GND NC SEG1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC: No connection 80-pin Plastic QFP (QFP80-P-1414-0.65-K) 5/19 ¡ Semiconductor ML9211 PIN DESCRIPTIONS Pin QFP-1* QFP-2* 65, 80 25 24, 40 33 63 78 23 22, 38 31 Symbol VDISP VDD D-GND L-GND SEG1 to 37 Type — — — — O Description Power supply pins for VFD driver circuit. These should be connected externally. Power supply pin for logic drive. D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the logic circuit. These should be connected externally. Segment (anode) signal output pins for a VFD tube. These pins can be directly connected to the VFD tube. External circuit is not required. IOH£–5 mA Segment (anode) signal output pins for a VFD tube.These pins can be directly 42 to 64, 40 to 62, 66 to 79 64 to 77 79, 80, 1 to 17 18 19 20 27 28 29 SEG38 to 56 1 to 19 GRID1 GRID2 GRID3 CS CLOCK DATA IN 20 21 22 29 30 31 O connected to the VFD tube. External circuit is not required. IOH£–10 mA Inverted Grid signal output pins. For pre-driver, the external circuit is required. O IOL£10 mA Chip select input pin. Data is not transferred when CS is set to a Low level. Shift clock input pin. Serial data shifts at the rising edge of the CLOCK. Serial data input pin (positive logic). Data is input to the shift register at the rising edge of the CLOCK signal. Duplex/Triplex operation select input pin. Duplex (1/2 duty) operation is selected when this pin is set to VDD. Triplex (1/3 duty) operation is selected when this pin is set to L-GND. Master/Slave mode select input pin. Master mode is selected when this pin is set to VDD. Slave mode is selected when this pin is set to L-GND. Dimming pulse input. When the slave mode is selected, connect this pin to the master side DIM OUT pin at the slave mode. The pulse width of the all segment output are controlled by a input pulse width of DIM IN. When the master mode is selected, the input level of this pin is ignored. Connect this pin to VDD or L-GND at the master mode. The pulse width of the all grids and segment outputs are controlled by a built-in 10-bit dimming circuit. Synchronous signal input. When the slave mode is selected, connect these pins to the master side SYNC OUT 1 and 2 pins. When the master mode is selected, the input level of these pins are ignored. Connect these pins to VDD or L-GND at the master mode. Dimming pulse output. Connect this pin to the slave side DIM IN pin. I I I DUP/TRI 35 33 I M/S 36 34 I DIM IN 26 24 I SYNC IN 1 SYNC IN 2 DIM OUT 27 28 39 25 I 26 37 O 6/19 ¡ Semiconductor ML9211 Symbol SYNC OUT 1 SYNC OUT 2 Pin QFP-1* QFP-2* 38 37 36 35 Type O Synchronous signal output. Description Connect these pins to the slave side SYNC IN 1 and 2 pins. RC oscillator connecting pins. Oscillation frequency depends on display tubes to be used. For details, refer to ELECTRICAL CHARACTERISTICS. VDD OSC0 R C OSC0 34 32 I/O * QFP-1: QFP80-P-1420-0.80-BK QFP-2: QFP80-P-1414-0.65-K ABSOLUTE MAXIMUM RATING Parameter Driver Supply Voltage Logic Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDISP VDD VIN PD TSTG IO1 Output Current IO2 IO3 IO4 Ta≥25°C Condition — — — QFP80-P-1420-0.80-BK QFP80-P-1414-0.65-K — SEG1 to 37 SEG38 to 56 GRID1 to 3 DIM OUT, SYNC OUT1, SYNC OUT2 Ratings –0.3 to +20 –0.3 to +6.5 –0.3 to VDD+0.3 760 630 –55 to +150 –10.0 to +2.0 –20.0 to +2.0 –10.0 to +20.0 –2.0 to +2.0 Unit V V V mW °C mA mA mA mA RECOMMENDED OPERATING CONDITIONS Parameter Driver Supply Voltage Logic Supply Voltage High Level Input Voltage Low Level Input Voltage Clock Frequency Oscillation Frequency Frame Frequency Operating Temperature Symbol VDISP VDD VIH VIL fC fOSC fFR TOP Condition — — All inputs except OSC0 All inputs except OSC0 — R=10KW±5%, C=27pF±5% R=10KW±5%, C=27pF±5% — 1/3 Duty 1/2 Duty Min. 8.0 4.5 0.8VDD — — 2.6 211 317 –40 Typ. 13.0 5.0 — — — 3.3 269 403 — Max. 18.0 5.5 — 0.2VDD 2.0 4.0 325 488 +85 Unit V V V V MHz MHz Hz Hz °C 7/19 ¡ Semiconductor ML9211 ELECTRICAL CHARACTERISTICS DC Characteristics Ta=–40 to +85°C,VDISP =8.0 to 18.0V, VDD=4.5 to 5.5V Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Symbol Applied pin VIH VIL IIH IIL VOH1 High Level Output Voltage VOH2 VOH3 VOH4 VOL1 Low Level Output Voltage VOL2 VOL3 VOL4 Supply Current IDISP IDD *1) *1) *1) *1) SEG1-37 SEG38-56 GRID1-3 *2) SEG1-37 SEG38-56 GRID1-3 *2) VDISP VDD VDD=4.5V VDD=4.5V Condition — — VIH=VDD VIL=GND IOH1=–5mA VDISP=9.5V IOH2=–10mA IOH3=–5mA IOH4=–200mA IOL1=500mA VDISP=9.5V IOL2=500mA IOL3=10mA IOL4=200mA no load R=10KW±5%, C=27pF±5%, Min. 0.8VDD — –1.0 –1.0 VDISP–0.8 VDISP–0.8 VDISP–0.8 VDD–0.8 — — — — — — Max. — 0.2VDD +1.0 +1.0 — — — — 2.0 2.0 2.0 0.8 100 5.0 Unit V V mA mA V V V V V V V V mA mA *1) CS, CLOCK, DATA IN, DIM IN, SYNC IN 1, SYNC IN 2, M/S, DUP/TRI *2) DIM OUT, SYNC OUT 1, SYNC OUT 2 8/19 ¡ Semiconductor AC Characteristics ML9211 Ta=–40 to +85°C,VDISP =8.0 to 18.0V, VDD=4.5 to 5.5V Parameter Clock Frequency Clock Pulse Width Data Setup Time Data Hold Time CS Off Time CS Setup Time (CS-Clock) CS Hold Time (Clock-CS) CS Wait Time Output Slew Rate Time VDD Rise Time VDD Off Time Symbol fC tCW tDS tDH tCSL tCSS tCSH tRSOFF tR tF tPRZ tPOF CL=100pF Condition — — — — — — — — tR=20% to 80% tF=80% to 20% Min. — 200 200 200 20 200 200 400 — — — 5.0 Max. 2.0 — — — — — — — 2.0 2.0 100 — Unit MHz ns ns ns ms ns ns ms ms ms ms ms Mounted in a unit Mounted in a unit, VDD=0.0V TIMING DIAGRAM l Data Input Timing tCSS 1/fC CLOCK tDS DATA IN VALID VALID tDH VALID VALID tCW tCW tCSH tCSL –0.8VDD –0.2VDD –0.8VDD –0.2VDD –0.8VDD –0.2VDD CS l Reset Timing tPRZ tRSOFF CS tPOF –0.8VDD –0.0V –0.8VDD –0.0V VDD l Driver Output Timing tR tF tR –0.8VDISP –0.2VDISP SEG1-56, GRID1-3 9/19 ¡ Semiconductor l Output Timing (Duplex Operation) *1bit time=4/fOSC (The dimming data is 1016/1024 in the master mode) 2048bit times (1 display cycle) GRID1 1016bit times 8bit times GRID2 1016bit times 1016bit times 8bit times ML9211 VDISP 8bit times D-GND VDISP D-GND VDISP GRID3 3bit times SEG1-56 1019bit times 5bit times 1019bit times 5bit times DIM OUT 1019bit times 1019bit times 5bit times SYNC OUT1 1019bit times 1029bit times 5bit times SYNC OUT2 1029bit times 1019bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 1029bit times 5bit times 5bit times 5bit times 5bit times D-GND VDISP D-GND VDD L-GND VDD L-GND VDD L-GND l Output Timing (Triplex Operation) *1bit time=4/fOSC (The dimming data is 1016/1024 in the master mode) 3072bit times (1 display cycle) GRID1 1016bit times 8bit times GRID2 1016bit times 8bit times GRID3 3bit times SEG1-56 1019bit times 5bit times 1019bit times 5bit times DIM OUT 1019bit times 1019bit times 5bit times SYNC OUT1 1019bit times 1029bit times 5bit times SYNC OUT2 1029bit times 1019bit times 1016bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 5bit times 5bit times 5bit times D-GND VDISP D-GND VDISP D-GND VDD L-GND VDD L-GND VDD L-GND 8bit times VDISP D-GND VDISP 10/19 ¡ Semiconductor l Output Timing (Duplex Operation) *1bit time=4/fOSC (The dimming data is 64/1024 in the master mode) 2048bit times (1 display cycle) GRID1 64bit times 960bit times GRID2 64bit times 960bit times 64bit times 960bit times ML9211 VDISP D-GND VDISP D-GND VDISP GRID3 3bit times 957bit times SEG1-56 67bit times 957bit times DIM OUT 67bit times 957bit times SYNC OUT1 67bit times 957bit times SYNC OUT2 1981bit times 67bit times 1981bit times 957bit times 1981bit times 67bit times 957bit times 67bit times 957bit times 67bit times 957bit times 67bit times 957bit times 957bit times 67bit times 957bit times 957bit times D-GND VDISP D-GND VDD L-GND VDD L-GND VDD L-GND l Output Timing (Triplex Operation) *1bit time=4/fOSC (The dimming data is 64/1024 in the master mode) 3072bit times (1 display cycle) GRID1 64bit times 960bit times GRID2 64bit times 960bit times GRID3 3bit times 957bit times SEG1-56 67bit times 957bit times DIM OUT 67bit times 957bit times SYNC OUT1 67bit times 957bit times SYNC OUT2 1981bit times 67bit times 1981bit times 957bit times 67bit times 67bit times 957bit times 67bit times 957bit times 67bit times 957bit times 67bit times 957bit times 957bit times 67bit times 957bit times 64bit times 957bit times D-GND VDISP D-GND VDISP D-GND VDD L-GND VDD L-GND VDD L-GND 960bit times VDISP D-GND VDISP 11/19 ¡ Semiconductor ML9211 FUNCTIONAL DESCRIPTION Power-on Reset When power is turned on, the ML9211 is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: • The contents of the shift registers and latches are set to "0". • The digital dimming duty cycle is set to "0". • All segment outputs are set to Low level. • All grid outputs are set to High level. Data Transfer Method Data can be transferred between the rising edge and the next falling edge of chip select input. The mode data, segment data and dimming data are written by a serial transfer method. The serial data is input to the shift register at the rising edge of a shift clock pulse. The mode data (M0 to M2) must be transferred after the segment data and dimming data succeedingly. When the chip select input falls, an internal LOAD signal is automatically generated and data is loaded to the latches. Function Mode Function mode is selected by the mode data (M0 to M2). The relation between function mode and mode data is as follows: FUNCTION MODE 0 1 2 3 4 OPERATING MODE Segment Data for GRID1-3 Input Segment Data for GRID1 Input Segment Data for GRID2 Input Segment Data for GRID3 Input Digital Dimming Data Input FUNCTION DATA M0 0 1 0 1 0 M1 0 0 1 1 0 M2 0 0 0 0 1 Segment Data Input [Function Mode: 0 to 3] • ML9211 receives the segment data when function mode 0 to 3 are selected. • The same segment data is transferred to the 3 segment data latches corresponding to GRID 1 to 3 at the same time when the function mode 0 is selected. • The segment data is transferred to only one segment data latch corresponding to the specified GRID when the function mode is 1, 2 or 3 is selected. • Segment output (SEG1 to 56) becomes High level (lighting) when the segment data (S1 to S56) is set to "1". [Data Format] Input Data : 59 bits Segment Data : 56 bits Mode Data : 3 bits Bit Input Data 1 S1 2 S2 3 S3 4 S4 53 54 55 56 57 M0 58 M1 59 M2 S53 S54 S55 S56 Segment Data (56bits) Mode Data (3bits) 12/19 ¡ Semiconductor [Bit correspondence between segment output and segment data] SEG n Segment data SEG n Segment data SEG n Segment data 1 2 3 4 5 6 7 8 ML9211 9 10 11 12 13 14 15 16 17 18 19 20 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 Digital Dimming Data Input [Function Mode: 4] • ML9211 receives the digital dimming data when function mode 4 is selected. • The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. • The 10-bit digital dimming data is input from LSB. [Data Format] Input Data : 13 bits Digital Dimming Data: 10 bits Mode Data : 3 bits Bit Input Data 1 D1 LSB 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 8 D8 9 D9 10 11 12 13 Digital Dimming Data (10bits) D10 M0 M1 M2 MSB Mode Data (3bits) (MSB) (LSB) D1 0 1 1 0 1 1 D2 0 0 1 0 0 1 D3 0 0 1 0 0 1 D4 0 0 0 1 1 1 Dimming Data D5 0 0 1 1 1 1 D6 0 0 1 1 1 1 D7 0 0 1 1 1 1 D8 0 0 1 1 1 1 D9 0 0 1 1 1 1 D10 0 0 1 1 1 1 Duty Cycle 0/1024 1/1024 1015/1024 1016/1024 1016/1024 1016/1024 Master Mode Master Mode is selected when M/S pin is set at High level. The master mode operation is as follows: • The input levels of DIM IN, SYNC IN1 and SYNC IN2 are ignored, and these pins should be connected to L-GND or VDD. • Brightness is adjusted by the internal digital dimming circuit. • The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by the internal timing generator. 13/19 ¡ Semiconductor ML9211 Slave Mode Slave Mode is selected when M/S pin is set at Low level. The slave mode operation is as follows: • The internal dimming circuit is ignored. • The pulse width of SEG1 to 56 are controlled by the pulse width of DIM IN signal. • The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by SYNC IN1 and SYNC IN2 signals. • The output levels of GRID1 to 3 are set at High level. The output levels of DIM OUT, SYNC OUT1 and SYNC OUT2 are set at Low level. [Correspondence between SYNC IN1, 2 and Segment Latch1 to 3] [Correspondence between DIM IN and SEG1 to 56] SYNC IN 1 0 1 0 1 SYNC IN 2 0 0 1 1 Segment Latch No Latch1 Latch2 Latch3 GRID No GRID1 GRID2 GRID3 DIM IN 0 1 Note: Low: Lights OFF High: Lights ON SEG1 to 56 Low High 14/19 ¡ Semiconductor 1. Circuit for the duplex VFD tube with 128 segments (2 Grid ¥ 112 Anode) APPLICATION CIRCUITS VDD VDD VDISP VDD VDISP SEG1 SEG56 GRID1 GRID2 GRID3 SYNC OUT 2 SYNC OUT 1 DIM OUT GND VDD VDD VDISP SEG1 SEG56 GRID1 GRID2 GRID3 SYNC OUT 2 SYNC OUT 1 DIM OUT S1 S2 S3 G1 G2 S110 S111 S112 ML9211 (MASTER) DUP/TRI M/S SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK ML9211 (SLAVE) DUP/TRI M/S SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK Microcontroller GND VDD R C GND Duplex VFD Tube Ef VDD R D-GND C GND OSC 0 L-GND OSC 0 L-GND D-GND GND ML9211 15/19 ¡ Semiconductor 2. Circuit for the triplex VFD tube with 192 segments (3 Grid ¥ 112 Anode) VDD VDD VDISP VDD M/S DUP/TRI SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK VDISP SEG1 SEG56 GRID1 GRID2 GRID3 SYNC OUT 2 SYNC OUT 1 DIM OUT GND M/S VDD VDISP SEG1 SEG56 GRID1 GRID2 GRID3 SYNC OUT 2 SYNC OUT 1 DIM OUT S1 S2 S3 G1 G2 G3 S110 S111 S112 ML9211 (MASTER) ML9211 (SLAVE) DUP/TRI SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK Microcontroller GND Triplex VFD Tube Ef VDD R C GND VDD R OSC 0 L-GND D-GND C GND OSC 0 L-GND D-GND ML9211 GND 16/19 ¡ Semiconductor ML9211 NOTES ON TURNING POWER ON/OFF • Connect L-GND and D-GND externally to be an equal potential voltage. • To avoid wrong operations, turn on the driver power supply after turning on the logic power supply. Conversely, turn off the logic power supply after tuning off the driver power supply. [Voltage] VDISP VDD [Time] 17/19 ¡ Semiconductor ML9211 PACKAGE DIMENSIONS (Unit : mm) QFP80-P-1420-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.27 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/19 ¡ Semiconductor ML9211 (Unit : mm) QFP80-P-1414-0.65-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.85 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 19/19 E2Y0002-29-62 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation. 2. 3. 4. 5. 6. 7. 8. 9. Copyright 1999 Oki Electric Industry Co., Ltd. Printed in Japan