E2G0151-18-X2
¡ Semiconductor MSM5118165D/DSL
¡ Semiconductor
ThisMSM5118165D/DSL version: Oct. 1998
1,048,576-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM5118165D/DSL is a 1,048,576-word ¥ 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM5118165D/DSL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ double-layer metal CMOS process. The MSM5118165D/DSL is available in a 42-pin plastic SOJ or 50/44-pin plastic TSOP. The MSM5118165DSL (the self-refresh version) is specially designed for lower-power applications.
FEATURES
• 1,048,576-word ¥ 16-bit configuration • Single 5 V power supply, ± 10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (SL version) • Fast page mode with EDO, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • CAS before RAS self-refresh capability (SL version) • Package options: 42-pin 400 mil plastic SOJ (SOJ42-P-400-1.27) (Product : MSM5118165D/DSL-xxJS) 50/44-pin 400 mil plastic TSOP (TSOPII50/44-P-400-0.80-K)(Product : MSM5118165D/DSL-xxTS-K) (TSOPII50/44-P-400-0.80-L) (Product : MSM5118165D/DSL-xxTS-L) xx indicates speed rank.
PRODUCT FAMILY
Family Access Time (Max.) tRAC tAA tCAC tOEA Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) 84 ns 104 ns 124 ns 743 mW 688 mW 633 mW 5.5 mW/ 1.1 mW (SL version)
MSM5118165D/DSL-50 50 ns 25 ns 13 ns 13 ns MSM5118165D/DSL-60 60 ns 30 ns 15 ns 15 ns MSM5118165D/DSL-70 70 ns 35 ns 20 ns 20 ns
1/17
¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 DQ8 10 NC 11 NC 12 WE 13 RAS 14 NC 15 NC 16 A0 17 A1 18 A2 19 A3 20 VCC 21 42 VSS VCC 1
MSM5118165D/DSL
50 VSS VSS 50 1 VCC 41 DQ16 40 DQ15 39 DQ14 38 DQ13 37 VSS 36 DQ12 35 DQ11 34 DQ10 33 DQ9 32 NC DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 49 DQ16 DQ16 49 48 DQ15 DQ15 48 47 DQ14 DQ14 47 46 DQ13 DQ13 46 45 VSS VSS 45 44 DQ12 DQ12 44 43 DQ11 DQ11 43 42 DQ10 DQ10 42 41 DQ9 40 NC DQ9 41 NC 40 2 DQ1 3 DQ2 4 DQ3 5 DQ4 6 VCC 7 DQ5 8 DQ6 9 DQ7 DQ8 10 NC 11 10 DQ8 11 NC 31 LCAS 30 UCAS 29 OE 28 A9 27 A8 26 A7 25 A6 24 A5 23 A4 22 VSS NC 15 NC 16 WE 17 RAS 18 NC 19 NC 20 A0 21 A1 22 A2 23 A3 24 VCC 25 36 NC 35 LCAS 33 OE 32 A9 31 A8 30 A7 29 A6 28 A5 27 A4 26 VSS NC 36 LCAS 35 OE 33 A9 32 A8 31 A7 30 A6 29 A5 28 A4 27 VSS 26 15 NC 16 NC 17 WE 18 RAS 19 NC 20 NC 21 A0 22 A1 23 A2 24 A3 25 VCC 34 UCAS UCAS 34
42-Pin Plastic SOJ
50/44-Pin Plastic TSOP (K Type)
50/44-Pin Plastic TSOP (L Type)
Pin Name A0 - A9 RAS LCAS UCAS DQ1 - DQ16 OE WE VCC VSS NC
Function Address Input Row Address Strobe Lower Byte Column Address Strobe Upper Byte Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (5 V) Ground (0 V) No Connection
Note :
The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/17
¡ Semiconductor
MSM5118165D/DSL
BLOCK DIAGRAM
WE RAS LCAS UCAS
Column Address Buffers Internal Address Counter Row Address 10 Buffers Timing Generator I/O Controller I/O Controller
10 10 8
OE
Output Buffers
8
DQ1 - DQ8
8
Column Decoders
Input Buffers
8
A0 - A9
Refresh Control Clock
Sense Amplifiers
16
I/O Selector
16
8 10
Input Buffers
8
Row Decoders
Word Drivers
Memory Cells
8
DQ9 - DQ16
Output Buffers
8
VCC
On Chip VBB Generator On Chip IVCC Generator
VSS
FUNCTION TABLE
Input Pin RAS H L L L L L L L L LCAS * H L H L L H L L UCAS * H H L L H L L L WE * * H H H L L L H OE * * L L L H H H H High-Z High-Z DOUT High-Z DOUT DIN Don't Care DIN High-Z DQ Pin DQ1 - DQ8 DQ9 - DQ16 High-Z High-Z High-Z DOUT DOUT Don't Care DIN DIN High-Z Function Mode Standby Refresh Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write —
*: "H" or "L"
3/17
¡ Semiconductor
MSM5118165D/DSL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT VCC IOS PD* Topr Tstg Rating –0.5 to VCC + 0.5 –0.5 to 7 50 1 0 to 70 –55 to 150 Unit V V mA W °C °C
*: Ta = 25°C Recommended Operating Conditions
(Ta = 0°C to 70°C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 –0.5*2 Typ. 5.0 0 — — Max. 5.5 0 VCC + 0.5*1 0.8 Unit V V V V
Notes : *1. The input voltage is VCC + 2.0 V when the pulse width is less than 20 ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS – 2.0 V when the pulse width is less than 20 ns (the pulse width is with respect to the point at which VSS is applied). Capacitance
(VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Parameter Input Capacitance (A0 - A9) Input Capacitance (RAS, LCAS, UCAS, WE, OE) Output Capacitance (DQ1 - DQ16) Symbol CIN1 CIN2 CI/O Typ. — — — Max. 5 7 7 Unit pF pF pF
4/17
¡ Semiconductor DC Characteristics
Parameter Output High Voltage Output Low Voltage Input Leakage Current
Symbol
MSM5118165D/DSL
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Condition MSM5118165 MSM5118165 MSM5118165 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. VOH IOH = –5.0 mA VOL IOL = 4.2 mA 0 V £ VI £ 6.5 V; ILI All other pins not under test = 0 V DQ disable 0 V £ VO £ VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS ≥ VCC –0.2 V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tHPC = Min. tRC = 125 ms, ICC10 CAS before RAS, tRAS £ 1 ms RAS £ 0.2 V, CAS £ 0.2 V — 300 — 300 — 300 mA 1, 4, 5 — 135 — 125 — 115 mA 1, 3 — 135 — 125 — 115 mA 1, 2 — 5 — 5 — 5 mA 1 — 135 — 125 — 115 mA 1, 2 –10 10 –10 10 –10 10 mA 2.4 0 Max. VCC 0.4 Min. 2.4 0 Max. VCC 0.4 Min. 2.4 0 Max. VCC 0.4 V V
Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (Battery Backup) Average Power Supply Current (CAS before RAS Self-Refresh)
ILO
–10
10
–10
10
–10
10
mA
ICC1
— — — —
135 2 1 200
— — — —
125 2 1 200
— — — —
115 2 1 200
mA
1, 2
mA mA
1 1, 5
ICCS
—
300
—
300
—
300
mA
1, 5
Notes : 1. 2. 3. 4. 5.
ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ VCC + 0.5 V, –0.5 V £ VIL £ 0.2 V. SL version.
5/17
¡ Semiconductor AC Characteristics (1/2)
MSM5118165D/DSL
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS Data Output Hold After CAS Low CAS to Data Output Buffer Turn-off Delay Time RAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time WE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period Refresh Period (SL version) RAS Precharge Time RAS Pulse Width RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode with EDO) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge OE Hold Time from CAS (DQ Disable) RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to RAS Lead Time
Symbol
MSM5118165 MSM5118165 MSM5118165 D/DSL-60 D/DSL-50 D/DSL-70 Unit Note Min. Max. — — — — 50 13 25 30 13 — — 13 13 13 13 50 16 128 — 10,000
100,000
Min. 104 135 25 68 — — — — — 0 5 0 0 0 0 1 — — 40 60 60 10 10 10 10 40 5 35 5 14 12 0 10 0 10 30
Max. — — — — 60 15 30 35 15 — — 15 15 15 15 50 16 128 — 10,000
100,000
Min. 124 160 30 78 — — — — — 0 5 0 0 0 0 1 — — 50 70 70 13 13 10 13 45 5 40 5 14 12 0 10 0 13 35
Max. — — — — 70 20 35 40 20 — — 20 20 20 20 50 16 128 — 10,000
100,000
tRC tRWC tHPC tHPRWC tRAC tCAC tAA tCPA tOEA tCLZ tDOH tCEZ tREZ tOEZ tWEZ tT tREF tREF tRP tRAS tRSH tROH tCP tCAS tCSH tCRP tRHCP tCHO tRCD tRAD tASR tRAH tASC tCAH tRAL
84 110 20 58 — — — — — 0 5 0 0 0 0 1 — — 30 50 50 7 7 7 7 35 5 30 5 11 9 0 7 0 7 25
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 12 13 13 5 6 15 7, 8 7, 8 7 7 3 16 4, 5, 6 4, 5 4, 6 4, 13 4 4
RAS Pulse Width (Fast Page Mode with EDO) tRASP
— — — 10,000 — — — — 37 25 — — — — —
— — — 10,000 — — — — 45 30 — — — — —
— — — 10,000 — — — — 50 35 — — — — —
6/17
¡ Semiconductor AC Characteristics (2/2)
MSM5118165D/DSL
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Pulse Width WE Pulse Width (DQ Disable) OE Command Hold Time OE Precharge Time OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) RAS Pulse Width (CAS before RAS Self-Refresh) RAS Precharge Time (CAS before RAS Self-Refresh) CAS Hold Time (CAS before RAS Self-Refresh)
Symbol
MSM5118165 MSM5118165 MSM5118165 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. Max. — — — — — — — — — — — — — — — — — — — — — — — — — Min. 0 0 0 0 10 10 10 10 10 10 10 10 0 10 15 34 49 79 54 5 5 10 100 110 –50 Max. — — — — — — — — — — — — — — — — — — — — — — — — — Min. 0 0 0 0 13 10 10 13 10 10 13 13 0 13 20 44 59 94 64 5 5 10 100 130 –50 Max. — — — — — — — — — — — — — — — — — — — — — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns 14 11, 12 11, 12 10 10 10 10 12 12 13 16 16 16 12 9, 12 9 10, 12 12 0 0 0 0 7 7 7 7 7 7 7 7 0 7 13 30 42 67 47 5 5 10 100 90 –50
tRCS tRCH tRRH tWCS tWCH tWP tWPE tOEH tOEP tOCH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tRASS tRPS tCHS
7/17
¡ Semiconductor
MSM5118165D/DSL
Notes:
1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 2 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier. 13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later. 14. tCWL should be satisfied by both UCAS and LCAS. 15. tCP is determined by the time both UCAS and LCAS are high. 16. Only SL version.
8/17
E2G0104-17-41Q ¡ Semiconductor MSM5118165D/DSL
,,, , ,, , ,,,,
TIMING WAVEFORM
Read Cycle
tRC tRAS tRP RAS VIH – VIL – tCRP tCSH tCRP tRCD CAS VIH – VIL – tRAD tRSH tCAS tRAL tASR tRAH tASC tCAH Address VIH – VIL – VIH – VIL – VIH – VIL – VOH – Row Column tRCS tRRH tRCH WE tAA tROH tOEA tREZ OE tRAC tCAC tOEZ tCEZ DQ VOL – Open Valid Data-out tCLZ "H" or "L"
Write Cycle (Early Write)
tRC
tRAS
tRP
RAS
VIH – VIL –
tCRP
tCRP
tCSH
tRCD
tRSH
VIH – CAS VIL – VIH – VIL –
tRAD tRAH
tCAS
tASR
tASC
tCAH
tRAL
Address
Row
Column
tWCS
VIH – WE VIL –
tWCH tWP
tCWL
tRWL
VIH – OE VIL – VIH –
tDS
tDH
DQ
VIL –
Valid Data-in
Open
"H" or "L"
9/17
,,,
¡ Semiconductor MSM5118165D/DSL Read Modify Write Cycle
tRWC tRAS tRP VIH – RAS VIL – tCSH tCRP tCRP tRCD tRSH VIH – CAS VIL – tCAS tASR tRAH tASC tCAH VIH – Address VIL – VIH – VIL – VIH – VIL – VI/OH– Row Column tRAD tRWD tCWD WE OE tAA tAWD tCWL tRWL tWP tRCS tOEA tOED tOEH tCAC tRAC tOEZ tDS tDH DQ VI/OL– tCLZ Valid Data-out Valid Data-in "H" or "L"
10/17
¡ Semiconductor
Fast Page Mode Read Cycle (Part-1)
Address
Fast Page Mode Read Cycle (Part-2)
Address
, ,,, , ,
MSM5118165D/DSL
tRASP tRP RAS VIH – VIL – tRHCP tCRP tRCD tHPC tCP tCP CAS VIH – VIL – tCAS tCAS tCAS tRAD tASR tRAH tASC tCSH tCAH tASC tCAH tASC tCAH VIH – VIL – VIH – VIL – VIH – VIL – Row Column Column Column tRCS tRRH WE tCHO tOCH tRAC tAA tOEP OE tAA tAA tOEP tOEA tCAC tCPA tDOH tCAC tOEA tOEA tOEZ tCAC tOEZ tREZ DQ VOH – VOL – tCLZ
Valid Data-out
Valid Data-out Valid* Data-out Valid* Data-out
* : Same Data,
"H" or "L"
tRASP
tRP
RAS
VIH – VIL –
tRHCP
tCRP
tCRP
tHPC
tRCD
tCP
tCP
CAS
VIH – VIL –
tCAS
tCAS
tCAS
tRAD
tASR
tRAH
tCSH tASC tCAH Column
tASC
tCAH
tASC
tCAH
VIH – VIL – VIH – VIL – VIH – VIL –
Row
Column
Column
tRCS
tRCS
WE
tRAC tAA
tRCH
tWPE
tAA
tAA
OE
tCPA
tOEA tCAC
tWEZ
tCAC
tCAC tDOH
tCEZ
DQ
VOH – VOL –
tCLZ
Valid Data-out
Valid Data-out
Valid Data-out
"H" or "L"
11/17
,, , , ,
¡ Semiconductor MSM5118165D/DSL Fast Page Mode Write Cycle (Early Write)
tRASP tRP RAS VIH – VIL – tCRP tRCD tHPC tHPC tCP tCP CAS VIH – VIL – tCAS tCAS tCAS tRAD tASR tRAH tCSH tASC tCAH Column tASC tCAH tASC tRSH tCAH Address VIH – VIL – VIH – VIL – VIH – VIL – VIH – VIL – Row Column Column tWCS tWCH tWCS tWCH tWCS tWCH WE OE tDS tDH tDS tDH tDS tDH DQ Valid Data-in Valid Data-in Valid Data-in "H" or "L"
Fast Page Mode Read Modify Write Cycle
tRASP
RAS
VIH – VIL –
tRWD
tCRP
tRCD
tCP
CAS
VIH – VIL –
tRAD
tCWD
tASR
tRAH tASC
tHPRWC
tCPWD tASC
tCAH
tCWL
tCPA tCAH
tRWL
Address
VIH – VIL –
Row
Column
Column
tRCS
tAWD
tRCS
tCWD
WE
VIH – VIL –
tRAC
tAWD
tAA
tDS tWP
tAA
tDS
tWP
OE
VIH – VIL –
tOEA
tOED
tOEH tDH
tOEA
tOED
tOEH tDH
tCAC
tOEZ
tCAC
tOEZ
DQ
VI/OH – VI/OL –
Valid Data-out
Valid Data-in
Valid Data-out
Valid Data-in
tCLZ
tCLZ
"H" or "L"
12/17
,
¡ Semiconductor MSM5118165D/DSL RAS-Only Refresh Cycle
tRC RAS VIH – VIL – tRAS tRP tCRP tRPC CAS VIH – VIL – tASR tRAH Address VIH – VIL – Row tCEZ DQ VOH – VOL – Open Note: WE, OE = "H" or "L" "H" or "L"
CAS before RAS Refresh Cycle
tRC
tRP
tRAS
tRP
RAS
VIH – VIL –
tRPC
tRPC
tCP
tCSR
tCHR
CAS
VIH – VIL –
tCEZ
DQ
VOH – VOL –
Open Note: WE, OE, Address = "H" or "L"
13/17
¡ Semiconductor
Hidden Refresh Read Cycle
Hidden Refresh Write Cycle
Address
,,, ,, ,, ,
MSM5118165D/DSL
tRC tRAS tRP tRC tRAS tRP RAS VIH – VIL – tCRP tRCD tRSH tCHR CAS VIH – VIL – VIH – VIL – VIH – VIL – tASR tRAH tRAD tASC tCAH Address Row Column tRCS tRAL tRRH WE tAA tROH OE VIH – VIL – tOEA tRAC tCAC tCLZ tOEZ DQ VOH – VOL – Open Valid Data-out "H" or "L" tRC tRAS tRP tRC tRAS tRP RAS VIH – VIL – VIH – VIL – tCRP tRCD tRSH tCHR CAS tASR tRAH tRAD tASC tCAH tRAL VIH – VIL – VIH – VIL – VIH – VIL – VIH – VIL –
Row
Column
tWCS
tRWL tWCH
WE
tWP
OE
tDS
tDH
DQ
Valid Data-in "H" or "L"
14/17
¡ Semiconductor
CAS before RAS Self-Refresh Cycle
tRP RAS VIH – VIL – tRPC tCP CAS VIH VIL – – tCEZ DQ VOH – VOL – Open tCSR tRASS
Note: WE, OE, Address = "H" or "L" Only SL version
,
MSM5118165D/DSL
tRPS tRPC tCHS "H" or "L"
15/17
¡ Semiconductor
MSM5118165D/DSL
PACKAGE DIMENSIONS
(Unit : mm)
SOJ42-P-400-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.86 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
16/17
¡ Semiconductor
MSM5118165D/DSL
(Unit : mm)
TSOPII50/44-P-400-0.80-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.60 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
17/17
E2Y0002-28-41
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1998 Oki Electric Industry Co., Ltd.
Printed in Japan
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