MSM51V16400DSL-60TS-K

E2G0122-17-61 ¡ Semiconductor MSM51V16400D/DSL ¡ Semiconductor This version: Mar. 1998 MSM51V16400D/DSL Pr el im in ar y 4,194,304-Word ¥ 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM51V16400D/DSL is a 4,194,304-word ¥ 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM51V16400D/DSL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ double-layer metal CMOS process. The MSM51V16400D/DSL is available in a 26/24-pin plastic SOJ or 26/24-pin plastic TSOP. The MSM51V16400DSL (the self-refresh version) is specially designed for lower-power applications. FEATURES • 4,194,304-word ¥ 4-bit configuration • Single 3.3 V power supply, ± 0.3 V tolerance • Input : LVTTL compatible, low input capacitance • Output : LVTTL compatible, 3-state • Refresh : 4096 cycles/64 ms, 4096 cycles/128 ms (SL version) • Fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • CAS before RAS self-refresh capability (SL version) • Multi-bit test mode capability • Package options: 26/24-pin 300 mil plastic SOJ (SOJ26/24-P-300-1.27) (Product : MSM51V16400D/DSL-xxSJ) 26/24-pin 300 mil plastic TSOP (TSOPII26/24-P-300-1.27-K) (Product : MSM51V16400D/DSL-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) 90 ns 110 ns 130 ns 270 mW 252 mW 234 mW 1.8 mW/ 0.72 mW (SL version) MSM51V16400D/DSL-50 50 ns 25 ns 13 ns 13 ns MSM51V16400D/DSL-60 60 ns 30 ns 15 ns 15 ns MSM51V16400D/DSL-70 70 ns 35 ns 20 ns 20 ns 1/17 ¡ Semiconductor PIN CONFIGURATION (TOP VIEW) VCC 1 , 26 VSS VCC 1 26 VSS DQ1 2 WE 4 25 DQ4 23 CAS 22 OE DQ1 2 DQ2 3 WE 4 25 DQ4 DQ2 3 24 DQ3 24 DQ3 23 CAS 22 OE 21 A9 19 A8 RAS 5 RAS 5 A11R 6 A10R 8 A0 9 21 A9 19 A8 A11R 6 A10R 8 A0 9 18 A7 17 A6 16 A5 15 A4 14 VSS 18 A7 17 A6 16 A5 15 A4 14 VSS A1 10 A2 11 A3 12 VCC 13 28-Pin Plastic SOJ A1 10 A2 11 A3 12 VCC 13 28-Pin Plastic TSOP (K Type) Pin Name A0 - A9, A9R - A11R RAS CAS DQ1 - DQ4 OE WE VCC VSS Function Address Input Row Address Strobe Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (3.3 V) Ground (0 V) MSM51V16400D/DSL Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/17 ¡ Semiconductor MSM51V16400D/DSL BLOCK DIAGRAM RAS CAS Timing Generator Timing Generator 10 Column Address Buffers Internal Address Counter 10 Column Decoders Write Clock Generator WE OE 4 Output Buffers 4 4 A0 - A9 Refresh Control Clock Sense Amplifiers 4 I/O Selector 4 4 DQ1 - DQ4 Input Buffers 4 10 A10R, A11R VCC 2 Row Address Buffers 12 Row Decoders Word Drivers Memory Cells On Chip VBB Generator VSS 3/17 ¡ Semiconductor MSM51V16400D/DSL ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg Rating –0.5 to 4.6 50 1 0 to 70 –55 to 150 Unit V mA W °C °C *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 3.0 0 2.0 –0.3 Typ. 3.3 0 — — Max. 3.6 0 VCC + 0.3 0.8 (Ta = 0°C to 70°C) Unit V V V V Capacitance Parameter Input Capacitance (A0 - A9, A10R, A11R) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DQ1 - DQ4) Symbol CIN1 CIN2 CI/O Typ. — — — (VCC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz) Max. 5 7 7 Unit pF pF pF 4/17 ¡ Semiconductor DC Characteristics Parameter Output High Voltage Output Low Voltage Input Leakage Current Symbol MSM51V16400D/DSL (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Condition MSM51V16400 MSM51V16400 MSM51V16400 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. VOH IOH = –2.0 mA VOL IOL = 2.0 mA 0 V £ VI £ VCC + 0.3 V; ILI All other pins not under test = 0 V DQ disable 0 V £ VO £ VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS ≥ VCC –0.2 V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. tRC = 31.3 ms, ICC10 CAS before RAS, tRAS £ 1 ms RAS £ 0.2 V, CAS £ 0.2 V — 400 — 400 — 400 mA 1, 4, 5 — 70 — 65 — 60 mA 1, 3 — 75 — 70 — 65 mA 1, 2 — 5 — 5 — 5 mA 1 — 75 — 70 — 65 mA 1, 2 –10 10 –10 10 –10 10 mA 2.4 0 Max. VCC 0.4 Min. 2.4 0 Max. VCC 0.4 Min. 2.4 0 Max. VCC 0.4 V V Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (Battery Backup) Average Power Supply Current (CAS before RAS Self-Refresh) ILO –10 10 –10 10 –10 10 mA ICC1 — — — — 75 2 0.5 200 — — — — 70 2 0.5 200 — — — — 65 2 0.5 200 mA 1, 2 mA mA 1 1, 5 ICCS — 300 — 300 — 300 mA 1, 5 Notes : 1. 2. 3. 4. 5. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ VCC + 0.3 V, –0.3 V £ VIL £ 0.2 V. SL version. 5/17 ¡ Semiconductor AC Characteristics (1/2) MSM51V16400D/DSL (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS CAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period Refresh Period (SL version) RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS MSM51V16400 MSM51V16400 MSM51V16400 D/DSL-60 D/DSL-70 Unit Note Symbol D/DSL-50 Min. tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tOEA tCLZ tOFF tOEZ tT tREF tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH 90 131 35 76 — — — — — 0 0 0 3 — — 30 50 50 13 13 7 13 50 5 30 17 12 0 7 0 7 25 0 0 0 Max. — — — — 50 13 25 30 13 — 13 13 50 64 128 — 10,000 100,000 Min. 110 155 40 85 — — — — — 0 0 0 3 — — 40 60 60 15 15 10 15 60 5 35 20 15 0 10 0 10 30 0 0 0 Max. — — — — 60 15 30 35 15 — 15 15 50 64 128 — 10,000 100,000 Min. 130 185 45 100 — — — — — 0 0 0 3 — — 50 70 70 20 20 10 20 70 5 40 20 15 0 10 0 15 35 0 0 0 Max. — — — — 70 20 35 40 20 — 20 20 50 64 128 — 10,000 100,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 8 5 6 4, 5, 6 4, 5 4, 6 4 4 4 7 7 3 13 — — — 10,000 — — — 37 25 — — — — — — — — — — — 10,000 — — — 45 30 — — — — — — — — — — — 10,000 — — — 50 35 — — — — — — — — 6/17 ¡ Semiconductor AC Characteristics (2/2) MSM51V16400D/DSL (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 Parameter Write Command Set-up Time Write Command Hold Time Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) RAS Pulse Width (CAS before RAS Self-Refresh) RAS Precharge Time (CAS before RAS Self-Refresh) CAS Hold Time (CAS before RAS Self-Refresh) Symbol MSM51V16400MSM51V16400 MSM51V16400 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. Max. — — — — — — — — — — — — — — — — — — — — — — — Min. 0 10 10 15 15 15 0 10 15 40 55 85 60 5 10 10 10 10 10 10 100 110 –50 Max. — — — — — — — — — — — — — — — — — — — — — — — Min. 0 15 10 20 20 20 0 15 20 50 65 100 70 5 10 10 10 10 10 10 100 130 –50 Max. — — — — — — — — — — — — — — — — — — — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns 13 13 13 10 10 9 9 9 9 9 0 7 7 13 13 13 0 7 13 36 48 73 53 5 10 10 10 10 10 10 100 90 –50 tWCS tWCH tWP tOEH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tWRP tWRH tWTS tWTH tRASS tRPS tCHS 7/17 ¡ Semiconductor Notes: MSM51V16400D/DSL 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF. The output timing reference levels are VOH = 2.0 V and VOL = 0.8 V. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. In a test mode CA0 and CA1 are not used and each DQ pin now accesses 4-bit locations. Since all 4 DQ pins are used, a total of 16 data bits can be written in parallel into the memory array. In a read cycle, if 4 data bits are equal, the DQ pin will indicate a high level. If the 4 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 13. Only SL version. 8/17 E2G0101-17-41N ¡ Semiconductor MSM51V16400D/DSL ,,,



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,,,,  TIMING WAVEFORM Read Cycle tRC tRAS tRP RAS VIH – VIL – tCRP tCRP tCSH tRCD CAS VIH – VIL – tRAD tRSH tCAS tRAL tASR tRAH tASC tCAH Address VIH – VIL – VIH – VIL – VIH – VIL – VOH – Row Column tRCS tRRH tRCH WE OE tAA tROH tOEA tRAC tCAC tOEZ tOFF DQ VOL – Open Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRAS tRP RAS VIH – VIL – tCRP tCRP tCSH tRCD tRSH VIH – CAS VIL – VIH – VIL – VIH – tRAD tRAH tCAS tASR tASC tCAH tRAL Address Row Column tWCS tWCH tWP tCWL WE VIL – VIH – tRWL OE VIL – VIH – tDS tDH DQ VIL – Valid Data-in Open "H" or "L" 9/17 ,,,


     ¡ Semiconductor MSM51V16400D/DSL Read Modify Write Cycle tRWC tRAS tRP RAS VIH – VIL – tCSH tCRP tCRP tRCD tRSH VIH – CAS VIL – tCAS tASR tRAH tASC tCAH VIH – Address VIL – WE OE VIH – VIL – VIH – VIL – VI/OH– Row Column tRAD tRWD tCWD tAA tAWD tCWL tRWL tWP tRCS tOEA tOED tOEH tCAC tRAC tOEZ tDS tDH DQ VI/OL– tCLZ Valid Data-out Valid Data-in "H" or "L" 10/17 
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¡ Semiconductor MSM51V16400D/DSL Fast Page Mode Read Cycle tRASP tRP VIH – RAS V – IL VIH – CAS VIL – VIH – VIL – VIH – VIL – tRHCP tCRP tRCD tPC tRSH tCRP tCP tCP tRAD tCAS tCAS tCAS tASR tRAH tASC tCSH tCAH tASC tCAH tASC tRAL tCAH Address Row Column Column Column tRCS tRCH tRCS tAA tRCH tRCS tAA tRCH WE tAA tRRH VIH – OE VIL – tOEA tCPA tCPA tOEA tOEA tCAC tRAC tOFF tOEZ tCAC tOFF tCAC tOFF tCLZ tOEZ tCLZ tOEZ VOH – DQ VOL – tCLZ Valid Data-out Valid Data-out Valid Data-out "H" or "L" Fast Page Mode Write Cycle (Early Write) tRASP tPC tRP VIH – RAS V – IL VIH – CAS VIL – VIH – VIL – tRHCP tCRP tRCD tRSH tCRP tCAS tCP tCP tCAS tCAS tASR tRAH tASC tRAD tCSH tCAH tASC tCAH tASC tCAH tRAL Address Row tWCS WE VIH – VIL – Column tCWL tWCH tWP Column tCWL tWCS tWCH tWP Column tRWL tCWL tWCS tWCH tWP tDS tDH tDS tDH tDS tDH VIH – DQ VIL – Valid Data-in Valid Data-in Valid Data-in Note: OE = "H" or "L" "H" or "L" 11/17 ¡ Semiconductor Fast Page Mode Read Modify Write Cycle VIH – RAS VIL – VIH – CAS VIL – Address VIH – VIL – V WE IH – VIL – VIH – OE V – IL VI/OH– VI/OL – DQ RAS-Only Refresh Cycle RAS VIH – VIL – CAS VIH – VIL – Address VIH – VIL – DQ VOH – VOL – 
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, tRASP tRP tCSH tPRWC tRCD tCAS tCP tCAS tCP tRSH tCAS tCRP tRAD tRAH tCAH tASC tASC tASR tASC tCAH tCAH tRAL Row Column tRWD Column Column tRCS tCWD tCWL tRCS tCPWD tCWD tAWD tCWL tRCS tCPWD tCWD tAWD tRWL tCWL tAWD tRAC tDS tWP tDH tDS tWP tDH tROH tDS tWP tDH tAA tCPA tAA tCPA tAA tOEA tOEA tOEA tOED tOED tOED tCAC tOEZ tCAC tOEZ In MSM51V16400D/DSL tCAC tOEZ Out In Out Out In tCLZ tCLZ tCLZ "H" or "L" tRC tRAS tRP tCRP tRPC tASR tRAH Row tOFF Open Note: WE, OE = "H" or "L" "H" or "L" 12/17 ¡ Semiconductor CAS before RAS Refresh Cycle tRC tRP RAS VIH – VIL – tRPC tCP CAS VIH – VIL – tWRP tWRH tCSR tCHR tRAS MSM51V16400D/DSL tRP tRPC  


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 WE VIH – VIL – tOFF DQ VOH – VOL – Open Note: OE, Address = "H" or "L" "H" or "L" tWRP Hidden Refresh Read Cycle tRC tRC tRAS tRP tRAS tRP RAS VIH – VIL – VIH – VIL – tCRP tRCD tRSH tCHR CAS tASR tRAD tASC tRAH tCAH Address VIH – VIL – Row Column tRCS tRAL tRRH VIH – WE V IL – VIH – OE V IL – tAA tROH tOEA tRAC tCAC tCLZ tOFF tOEZ DQ VOH – VOL – Valid Data-out "H" or "L" 13/17 ¡ Semiconductor Hidden Refresh Write Cycle tRC tRAS RAS VIH – VIL – VIH – VIL – VIH – VIL – VIH – VIL – VIH – VIL – VIH – VIL – tRP MSM51V16400D/DSL tRC tRAS tRP CAS Address WE OE DQ CAS before RAS Self-Refresh Cycle tRP VIH – RAS VIL – VIH – CAS VIL – DQ VOH – VOL –
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,   tCRP tRCD tRSH tCHR tASR tRAH tRAD tASC tCAH tRAL Row Column tWCS tWCH tWP tWRP tWRH tDS tDH Valid Data-in "H" or "L" tRASS tRPS tRPC tCP tCSR tRPC tCHS tOFF Open Note: WE, OE, Address = "H" or "L" Only SL version "H" or "L" 14/17 ¡ Semiconductor Test Mode Initiate Cycle RAS CAS WE DQ ,

     MSM51V16400D/DSL tRC tRP tRAS VIH – VIL – tRPC tCP tCSR tCHR VIH – VIL – tWTS tWTH VIH – VIL – tOFF VOH – VOL – Open Note: OE, Address = "H" or "L" "H" or "L" 15/17 ¡ Semiconductor MSM51V16400D/DSL PACKAGE DIMENSIONS (Unit : mm) SOJ26/24-P-300-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.80 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/17 ¡ Semiconductor MSM51V16400D/DSL (Unit : mm) TSOPII26/24-P-300-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/17