MSM5839

E2B0021-27-Y2 ¡ Semiconductor ¡ Semiconductor MSM5839C 40-DOT SEGMENT DRIVER This version: MSM5839C Nov. 1997 Previous version: Mar. 1996 GENERAL DESCRIPTION The MSM5839C is a dot matrix LCD segment driver LSI which is fabricated using low power CMOS metal gate technology. This LSI consists of two 20-bit shift registers, two 20-bit latches, a 40-bit level shifter and a 40-bit 4-level driver. It converts serial data, which is received from LCD controller LSI, into parallel data and outputs LCD driving waveform to the LCD panel. Expansion of display can easily be made by increasing the number of characters and character patterns. This LSI can drive a variety of LCD panels because the bias voltage, which determines an LCD driving voltage, can be optionally supplied from the external source. FEATURES • Supply voltage : 4.5 to 5.5V • LCD driving voltage : 4 to 11V • Applicable LCD duty : 1/3 to 1/64 • Bias voltage can be supplied externally. • Applicable commomn driver: MSM5238 (32 outputs) • Package options: 56-pin plastic QFP (QFP56-P-910-0.65-K) (Product name: MSM5839C GS-K) 56-pin plastic QFP (QFP56-P-910-0.65-L2) (Product name: MSM5839C GS-L2) 1/9 ¡ Semiconductor MSM5839C BLOCK DIAGRAM O1 O2 O19 O20 O21 O22 O39 O40 VDD(V1) V2 V3 VEE(V4) 40-Bit 4-Level Driver VDD VEE 40-Bit Level Shifter DF LOAD 20-Bit Latch 20-Bit Latch VDD VSS VSS DI1 CP 20-Bit Shift Register 20-Bit Shift Register DO40 DO20 DI21 2/9 ¡ Semiconductor MSM5839C PIN CONFIGURATION (TOP VIEW) (Top view) NC NC NC DF LOAD DI 1 CP VDD VSS V2 V3 VEE(V4) DO20 DI 21 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 56 55 54 53 52 51 50 49 48 47 46 45 44 43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 DO40 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 O30 O29 O28 56-Pin Plastic QFP (Type K) 9 10 11 12 13 NC NC NC DF LOAD DI1 CP VDD VSS V2 V3 VEE(V4) DO20 DI21 14 1 2 3 4 5 6 7 8 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 *(VDD) O21 O22 O23 O24 O25 O26 O27 NC: No connection 56 55 54 53 52 51 50 49 48 47 46 45 44 43 15 16 17 18 19 20 21 22 23 24 25 26 27 28 O15 O16 O17 O18 O19 O20 *(VDD) O21 O22 O23 O24 O25 O26 O27 42 41 40 39 38 37 36 35 34 33 32 31 30 56-Pin Plastic QFP (Type L) * This pin is internally connected to VDD, so connect it to the power supply or leave it open. Note : The figure for Type L shows the configuration viewed from the reverse side of the package. Pay attention to the difference in pin arrangement. 3/9 DO40 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 O30 O29 O28 NC: No connection 29 ¡ Semiconductor MSM5839C ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage (1) Supply Voltage (2) Input Voltage Storage Temperature Symbol VDD VDD – VEE*1 V1 TSTG Condition Ta = 25°C Ta = 25°C Ta = 25°C — Rating –0.3 to +6 0 to 12 –0.3 to VDD +0.3 –55 to +150 Unit V V V °C *1: VDD>V2>V3>VEE RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage (1) Supply Voltage (2) Operating Temperature Symbol VDD VDD – VEE*1 Top Condition — — — Range 4.5 to 5.5 4 to 11 –20 to +85 Unit V V °C *1: VDD>V2>V3>VEE ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 5V ±10%, Ta = –20 to +85°C) Parameter "H" Input Voltage "L" Input Voltage "H" Input Current "L" Input Current "H" output Voltage "L" output Voltage ON Resistance Supply Current Symbol VIH *1 VIL *1 IIH *1 VI = VDD IIL *1 VI = 0V VOH *2 IO = –0.4 mA VOL *2 IO = 0.4 mA RON *4 IDD VDD – VEE = 8V |VN – VO| = 0.25V VDD – VEE = 11V, No load *3 Connect all inputs to VDD or VSS Condition — — Min. 0.8VDD VSS — — VDD – 0.4 — — — Typ. — — — — — — 5 — Max. VDD 0.2VDD 1 –1 — 0.4 10 100 Unit V V mA mA V V kW mA *1: *2: *3: *4: Applicable to LOAD, CP, DI1, DI21, DF Applicable to DO20, DO40 VN = VDD to VEE, V2 = 7 (VDD – VEE), V3 = 2 (VDD – VEE) 9 Applicable to O1 - O40 9 4/9 ¡ Semiconductor Switching Characteristics MSM5839C (VDD = 5V ±10%, Ta = –20° to +85°C, CL = 15pF) Parameter "H", "L" Propagation Delay Time Clock Frequency Clock Pulse Width LOAD Pulse Width Data Setup Time DI to CP CP to LOAD Time LOAD to CP Time DATA Hold Time DI to CP CP Rise/Fall Time LOAD Rise/Fall Time Symbol tPLH tPHL fCP tW(CP) tW(L) tSETUP tCL tLC tHOLD tr(CP) tf(CP) tr(L) tf(L) Condition — DUTY = 50% — — — — — — — — Min. — — 150 150 100 250 0 50 — — Typ. — — — — — — — — — — Max. 250 2 — — — — — — 50 1 Unit ns MHz ns ns ns ns ns ns ns ms tf(CP) tw(CP) 0.8VDD CP 0.8VDD tSETUP 0.2VDD tHOLD 0.8VDD 0.8VDD tr(CP) tw(CP) 0.8VDD 0.2VDD tSETUP 0.8 VDD 0.2 VDD 0.8 VDD 0.2 VDD 0.8VDD 0.2VDD tHOLD DI1, DI21 0.2VDD 0.2VDD tPLH tPHL DO20, DO40 0.8VDD 0.2VDD tCL tf(L) tLC 0.2VDD LOAD 0.2VDD tr(L) tw(L) 5/9 ¡ Semiconductor MSM5839C FUNCTIONAL DESCRIPTION Pin Functional Description • DI1 The data input pin for the 20-bit shift register (from 1st to 20th bit). The display data is input to the data input pin in synchronization with a clock pulse. • CP Clock pulse input pin for the two 20-bit shift registers. The data is shifted in the two 20-bit shift registers at the falling edge of the clock pulse. Data setup time (tSETUP) and data hold time (tHOLD) are required between DI1, DI21 and CP. • DO20 The 20th output bit of the shift register. The data which is input from DI1 is clocked out with a delay of the number of bits of the shift register (20). A 40-bit shift register can be configured by connecting the output of this pin to DI21 pin. • DI21 The data input pin for the 20-bit shift register (from 21st to 40th bit). Connecting the DO20 pin and this pin allows the device to be used as a 40-bit shift register. • DO40 The 40th output bit of the shift register. The data which is input from DI1 is clocked out with a delay of the number of the bits of the shift register. When increasing the number of characters, this pin is used to cascade connect the next MSM5839C. • DF Alternate signal input pin for LCD driving waveform. • VDD(V1), VSS Supply voltage pins. VDD should be 4.5 to 5.5V. VSS is a ground pin (VSS = 0V). • V2, V3, VEE(V4) Bias supply voltage pins to drive the LCD. Bias voltage is supplied from an external source. • LOAD The signal for latching the shift register contents is input from this pin. When LOAD pin is set at "H", the shift register contents are transferred to the 40-bit 4-level driver. When LOAD pin is set at "L", the last display output data (O1 to O40), which was transferred when LOAD pin was at "H", is held. 6/9 ¡ Semiconductor MSM5839C • O1 to O40 Display data output pins which correspond to each data bit in the latch. One of VDD, V2, V3 or VEE (V4) is selected as a display driving voltage source based on the combination of latched data level and DF signal. Refer to the Truth Table below. These pins should be connected to the SEGMENT side of the LCD panel. Truth Table Latched data H L DF H L H L LCD driver output VEE (V4) VDD (V1) V3 V2 7/9 ¡ Semiconductor MSM5839C PACKAGE DIMENSIONS (Unit : mm) QFP56-P-910-0.65-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.36 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 8/9 ¡ Semiconductor MSM5839C (Unit : mm) QFP56-P-910-0.65-L2 Spherical surface Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.36 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 9/9