74HCU04DR2G

74HCU04 Hex Unbuffered Inverter High−Performance Silicon−Gate CMOS The 74HCU04 is identical in pinout to the LS04 and the MC14069UB. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of six single−stage inverters. These inverters are well suited for use as oscillators, pulse shapers, and in many other applications requiring a high−input impedance amplifier. For digital applications, the HC04 is recommended. Features http://onsemi.com MARKING DIAGRAMS 14 14 • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V; 2.5 to 6.0 V in Oscillator • • • • • • SOIC−14 D SUFFIX CASE 751A Configurations Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7.0 A Requirements ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 12 FETs or 3 Equivalent Gates These are Pb−Free Devices 1 HCU04G AWLYWW 1 14 14 1 TSSOP−14 DT SUFFIX CASE 948G 1 HCU04 A L, WL Y W, WW G or G HCU 04 ALYWG G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2007 March, 2007 − Rev. 0 1 Publication Order Number: 74HCU04/D 74HCU04 PIN ASSIGNMENT A1 1 14 VCC Y1 2 13 A6 A2 3 12 Y6 Y2 4 11 A5 A3 5 10 Y5 Y3 6 9 A4 GND 7 8 Y4 LOGIC DIAGRAM A1 A2 A3 A4 A5 FUNCTION TABLE Inputs A Outputs Y L H H L A6 1 2 3 4 5 6 9 8 11 10 13 12 Y=A Y1 Y2 Y3 Y4 Y5 Y6 PIN 14 = VCC PIN 7 = GND ORDERING INFORMATION Package Shipping † SOIC−14 (Pb−Free) 2500 / Tape & Reel Device 74HCU04DR2G 74HCU04DTR2G TSSOP−14* †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 2 74HCU04 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol Parameter Value Unit – 0.5 to + 7.0 V DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air 500 450 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature, 1 mm from case for 10 Seconds SOIC or TSSOP Package SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. _C 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating — SOIC Package: –7mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) Min Max Unit 2.0 6.0 V 0 VCC V – 55 + 125 _C − No Limit ns DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) http://onsemi.com 3 74HCU04 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC (V) – 55 to 25_C v 85_C v 125_C Unit VIH Minimum High−Level Input Voltage Vout = 0.5 V* |Iout| v 20 mA 2.0 3.0 4.5 6.0 1.7 2.5 3.6 4.8 1.7 2.5 3.6 4.8 l.7 2.5 3.6 4.8 V VIL Maximum Low−Level Input Voltage Vout = VCC – 0.5 V* |Iout| v 20 mA 2.0 3.0 4.5 6.0 0.3 0.5 0.8 1.1 0.3 0.5 0.8 1.1 0.3 0.5 0.8 1.1 V VOH Minimum High−Level Output Voltage Vin = GND |Iout| v 20 mA 2.0 4.5 6.0 1.8 4.0 5.5 1.8 4.0 5.5 1.8 4.0 5.5 V 3.0 4.5 6.0 2.36 3.86 5.36 2.26 3.76 5.26 2.20 3.70 5.20 2.0 4.5 6.0 0.2 0.5 0.5 0.2 0.5 0.5 0.2 0.5 0.5 3.0 4.5 6.0 0.32 0.32 0.32 0.32 0.37 0.37 0.32 0.40 0.40 Vin = GND VOL Maximum Low−Level Output Voltage |Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA Vin = VCC |Iout| v 20 mA Vin = VCC |Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 6.0 2.0 20 40 mA 1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). 2. For VCC = 2.0 V, Vout = 0.2 V or VCC − 0.2 V. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC (V) – 55 to 25_C v 85_C v 125_C Unit tPLH, tPHL Maximum Propagation Delay, Input A to Output Y (Figures 1 and 2) 2.0 3.0 4.5 6.0 70 40 14 12 90 45 18 15 105 50 21 18 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns Maximum Input Capacitance — 10 10 10 pF Cin 3. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). 4. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD 15 Power Dissipation Capacitance (Per Inverter)* pF 5. Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). http://onsemi.com 4 74HCU04 VCC TYPICAL APPLICATIONS TEST POINT tr tf 90% 50% 10% INPUT A VCC GND tPHL A OUTPUT DEVICE UNDER TEST tPLH Y C L* 90% 50% 10% OUTPUT Y tTHL tTLH *Includes all probe and jig capacitance Figure 1. Switching Waveforms R2 1/6 HCU04A Figure 3. Logic Detail (1/6 of Device Shown) Figure 2. Test Circuit 1/6 HCU04A 1/6 HCU04A 1/6 HCU04A Vout R2 > > R1 C1 < C2 R1 C R2 C2 C1 R1 Vout Figure 4. Crystal Oscillator Figure 5. Stable RC Oscillator VCC R2 Vin R1 1/6 HCU04A 1 M 1/6 HCU04A 1/6 HCU04A INPUT R2 > 6R1 OUTPUT 1M Vout Figure 6. Schmitt Trigger Figure 7. High Input Impedance Single−Stage Amplifier with a 2 to 6 V Supply Range http://onsemi.com 5 74HCU04 TYPICAL APPLICATIONS +V VCC 1/6 HCU04A 1/6 HCU04A 1/6 HCU04A 1/6 HCU04A INPUT OUTPUT For reduced power supply current, use high−efficiency LEDs such as the Hewlett−Packard HLMP series or equivalent. Figure 8. Multi−Stage Amplifier Figure 9. LED Driver http://onsemi.com 6 74HCU04 PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE H NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 14 8 −B− P 7 PL 0.25 (0.010) M 7 1 G −T− D 14 PL 0.25 (0.010) T B S A DIM A B C D F G J K M P R J M K M F R X 45 _ C SEATING PLANE B M S SOLDERING FOOTPRINT* 7X 7.04 14X 1.52 1 14X 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 74HCU04 PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U 0.25 (0.010) 8 S DETAIL E K A −V− ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 J J1 DIM A B C D F G H J J1 K K1 L M SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 74HCU04 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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