CAT524LI

Not Recommended for New Design CAT524 Quad Digitally Programmable Potentiometer (DPP™) with 256 Taps and Microwire Interface FEATURES DESCRIPTION „ Four 8-bit DPPs configured as programmable voltage sources in DAC-like applications „ Common reference inputs „ Buffered wiper outputs „ Non-volatile NVRAM memory wiper storage „ Output voltage range includes both supply rails „ 4 independently addressable buffered output wipers „ 1 LSB accuracy, high resolution „ Serial Microwire-like interface „ Single supply operation: 2.7V - 5.5V „ Setting read-back without effecting outputs The CAT524 is a quad, 8-bit digitally-programmable potentiometer (DPP™) configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for selfcalibrating systems and for applications where equipment which requires periodic adjustment is either difficult to access or in a hazardous environment. The four independently programmable DPPs have an output range which includes both supply rails. The wipers are buffered by rail to rail op amps. Wiper settings, stored in non-volatile NVRAM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each wiper can be dithered to test new output values without effecting the stored settings, and stored settings can be read back without disturbing the DPP’s output. For Ordering Information details, see page 14. APPLICATIONS „ Automated product calibration. „ Remote control adjustment of equipment „ Offset, gain and zero adjustments in selfcalibrating and adaptive control systems. „ Tamper-proof calibrations. „ DAC (with memory) substitute The CAT524 is controlled with a simple 3-wire serial, Microwire-like interface. A Chip Select pin allows several devices to share a common serial interface. Communication back to the host controller is via a single serial data line thanks to the Tri-Stated CAT524 Data Output pin. A RDY/BSY ¯¯¯¯ output working in concert with an internal low voltage detector signals proper operation of the non-volatile NVRAM memory Erase/Write cycle. PIN CONFIGURATION The CAT524 is available in the 0ºC to 70ºC commercial and -40ºC to 85ºC industrial operating temperature ranges. Both 14-pin plastic DIP and SOIC packages are offered. PDIP 14-Lead (L) SOIC 14-Lead (W) VDD 1 14 VREFH CLK 2 13 VOUT1 RDY/¯¯¯¯ BSY 3 12 VOUT2 4 CAT524 11 VOUT3 DI 5 10 VOUT4 DO 6 8 VREFL PROG 7 8 GND CS © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. MD-2006 Rev. H Not Recommended for New Design CAT524 FUNCTIONAL DIAGRAM 7 PROGRAM CONTROL 5 2 SERIAL CONTROL 4 + 13 – + 12 – + 11 – 24kΩ CS 3 24kΩ CLK 14 24kΩ DI 1 24kΩ PROG VREFH WIPER CONTROL REGISTERS AND NVRAM RDY/BSY VDD + 10 – SERIAL DATA OUTPUT REGISTER 6 VOUT1 VOUT2 VOUT2 VOUT2 DO CAT524 8 9 GND Doc. No. MD-2006 Rev. H VREFL 2 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice Not Recommended for New Design CAT524 ABSOLUTE MAXIMUM RATINGS (1) Parameters Ratings Supply Voltage VDD to GND Inputs CLK to GND CS to GND DI to GND ¯¯¯¯ to GND RDY/BSY PROG to GND VREFH to GND VREFL to GND Units -0.5 to +7 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 V V V V V V V V Parameters Outputs D0 to GND VOUT 1– 4 to GND Operating Ambient Temperature Commercial (‘C’ or Blank suffix) Industrial (‘I’ suffix) Junction Temperature Storage Temperature Lead Soldering (10 sec max) Ratings Units -0.5 to VDD +0.5 V -0.5 to VDD +0.5 V 0 to +70 -40 to +85 +150 -65 to +150 +300 °C °C °C °C °C RELIABILITY CHARACTERISTICS Symbol Parameter Test Method Min VZAP(2) ILTH(2)(3) Max Units ESD Susceptibility MIL-STD-883, Test Method 3015 2000 V Latch-Up JEDEC Standard 17 100 mA POWER SUPPLY Symbol Parameter Conditions IDD1 Supply Current (Read) IDD2 Supply Current (Write) VDD Min Typ Max Units Normal Operating — 400 600 µA Programming, VDD = 5V — 1600 2500 µA VDD = 3V — 1000 1600 µA 2.7 — 5.5 V Min Typ Max Units Operating Voltage Range LOGIC INPUTS Symbol Parameter Conditions IIH Input Leakage Current VIN = VDD — — 10 µA IIL Input Leakage Current VIN = 0V — — -10 µA VIH High Level Input Voltage 2 — VDD V VIL Low Level Input Voltage 0 — 0.8 V LOGIC OUTPUTS Symbol Parameter Conditions Min Typ Max Units VOH High Level Output Voltage IOH = -40µA VDD -0.3 — — V VIL Low Level Output Voltage IOL = 1mA, VDD = +5V — — 0.4 V IOL = 0.4mA, VDD = +3V — — 0.4 V Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. MD-2006 Rev. H Not Recommended for New Design CAT524 POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol RPOT Parameter Conditions Potentiometer Resistance See note 3 Min Typ Max 24 RPOT to RPOT Match — Units kΩ ±0.5 Pot Resistance Tolerance ±1 % ±20 % Voltage on VREFH pin 2.7 VDD V Voltage on VREFL pin 0 VDD - 2.7 V Resolution 0.4 % INL Integral Linearity Error 0.5 1 LSB DNL Differential Linearity Error 0.25 0.5 LSB ROUT Buffer Output Resistance 10 Ω IOUT Buffer Output Current 3 mA TCRPOT TC of Pot Resistance 300 ppm/ºC CH/CL Potentiometer Capacitances 8/8 pF AC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units Minimum CS Low Time 150 — — ns tCSS CS Setup Time 100 — — ns tCSH CS Hold Time 0 — — ns tDIS DI Setup Time 50 — — ns 50 — — ns Digital tCSMIN CL = 100pF (1) tDIH DI Hold Time tDO1 Output Delay to 1 — — 150 ns tDO0 Output Delay to 0 — — 150 ns tHZ Output Delay to High-Z — 400 — ns tLZ Output Delay to Low-Z — 400 — ns tBUSY Erase/Write Cycle Time — 4 5 ms PROG Setup Time 150 — — ns tPROG Minimum Pulse Width 700 — — ns tCLKH Minimum CLK High Time 500 — — ns tCLKL Minimum CLK Low Time 300 — — ns Clock Frequency DC — 1 MHz CLOAD = 10pF, VDD = +5V — 3 10 µs CLOAD = 10pF, VDD = +3V — 6 10 µs tPS fC Analog tDS DPP Settling Time to 1 LSB Notes: (1) All timing measurements are defined at the point of signal crossing VDD / 2. (2) These parameters are periodically sampled and are not 100% tested. (3) The 24kΩ +20% resistors are configured as 4 resistors in parallel which would provide a measured value between VREFH and VREFL of 6kΩ +20%. The individual 24kΩ resistors are not measurable but guaranteed by design and verification of the 6kΩ +20% value. Doc. No. MD-2006 Rev. H 4 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 RDY/BSY PROG DO DI CS CLK to to t LZ t DIS t CSS 1 1 t DO1 t DIH 2 2 t CLK H 3 t PROG t PS t CLK L 3 t DO0 4 t BUSY t CSH 4 t HZ t CSMIN 5 5 FROM TIMING TO Rising CS edge to D0 becoming high low impedance (active output) t LZ Rising PROG edge to next rising CLK edge Falling CS edge to D0 becoming high impedance (Tri-State) t BUSY Falling CLK edge after PROG=H to rising RDY/BSY edge t PROG Rising PROG edge to falling PROG edge t PS t HZ Rising CLK edge to D0 = high Rising CLK edge to D0 = low t DO0 t DO1 Rising CLK edge to end of datavalid t DIH Max Min Min (Max) Max (Max) Max Min Min Data valid to first rising CLK edge after CS = high t DIS Min Min Rising CS edge to next rising CLK edge t CSMIN Falling CS edge torising CS edge t CSS Min t CSH Falling CLK edge for last data bit (DI) to falling CS edge Min Min MIN/MAX t CLK L Falling CLK edge to CLKrising edge t CLK H Rising CLK edge tofalling CLK edge PARAM NAME Not Recommended for New Design CAT524 A.C. TIMING DIAGRAM Doc. No. MD-2006 Rev. H Not Recommended for New Design CAT524 PIN DESCRIPTION Pin Name 1 VDD Power supply positive 2 CLK Clock input pin 3 ¯¯¯¯ RDY/BSY 4 CS Chip select 5 DI Serial data input pin 6 DO Serial data output pin 7 PROG 8 GND Power supply ground 9 VREFL Minimum DAC output voltage 10 VOUT4 DPP output channel 4 11 VOUT3 DPP output channel 3 12 VOUT2 DPP output channel 2 13 VOUT1 DPP output channel 1 14 VREFH Maximum DPP output voltage DPP addressing is as follows: Function Ready/Busy output A0 A1 0 0 VOUT2 1 0 VOUT3 0 1 VOUT4 1 1 Non-volatile Programming Enable Input Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. DEVICE OPERATION The CAT524 is a quad 8-bit configured digitally programmable potentiometer (DPP) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPPs return to the settings stored in non-volatile memory. Each DPP can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be temporarily adjusted without changing the stored output setting, which is useful for testing new output settings before storing them in memory. CHIP SELECT Chip Select (CS) enables and disables the CAT524’s read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in non-volatile memory and switches DO to its high impedance Tri-State mode. Because CS functions like a reset the CS pin has been equipped with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. DIGITAL INTERFACE The CAT524 employs a 3 wire serial, Microwire-like control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic “1” as a start bit. The DPP address and data are clocked into the DI pin on the clock’s rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. Doc. No. MD-2006 Rev. H DPP OUTPUT VOUT1 CLOCK The CAT524’s clock controls both data flow in and out of the IC and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock’s rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being 6 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice Not Recommended for New Design CAT524 minimum value required for non-volatile programming, ¯¯¯¯ will remain high following the program RDY/BSY command indicating a failure to record the desired data in non-volatile memory. saved may already be resident in the DPP wiper control register. No clock is necessary upon system power-up. The CAT524’s internal power-on reset circuitry loads data from non-volatile memory to the DPPs without using the external clock. DATA OUTPUT Data is output serially by the CAT524, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 524s to share a single serial data line and simplifies interfacing multiple 524s to a microprocessor. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. WRITING TO MEMORY Programming the CAT524’s non-volatile memory is accomplished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit followed by a two bit DPP address and eight data bits are clocked into the DPP control register via the DI pin. Data enters on the clock’s rising edge. The DPP output changes to its new setting on the clock cycle following D7, the last data bit. VREF VREF, the voltage applied between pins VREFH and VREFL, sets the configured DPP’s Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH and VREFL are connected across the power supply rails. When using less than the full supply voltage VREFH is restricted to voltages between VDD and VDD/2 and VREFL to voltages between GND and VDD/2. Programming is achieved by bringing PROG high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DPP wiper control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of ramping the programming voltage for data transfer to the nonvolatile cells. The CAT524 non-volatile memory cells will endure over 100,000 write cycles and will retain data for a minimum of 20 years without being refreshed. ¯¯¯¯¯ READY/BUSY When saving data to non-volatile memory, the ¯¯¯¯) signals the start and Ready/Busy output (RDY/BSY duration of the non-volatile erase/write cycle. Upon receiving a command to store data (PROG goes high) ¯¯¯¯ goes low and remains low until the RDY/BSY programming cycle is complete. During this time the CAT524 will ignore any data appearing at DI and no data will be output on DO. ¯¯¯¯ is internally ANDed with a low voltage RDY/BSY detector circuit monitoring VDD. If VDD is below the Figure 1. Writing to Memory to 1 2 3 4 5 6 A0 A1 D0 D1 7 8 9 10 11 12 N N+1 N+2 CS NEW DPP DATA DI 1 D2 D3 D4 D5 D6 D7 D6 D7 CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 PROG RDY/BSY DPP OUTPUT © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CURRENT DPP VALUE NEW DPP VALUE NEW DPP VALUE NON-VOL ATILE VOLATILE NON-VOL ATILE 7 Doc. No. MD-2006 Rev. H Not Recommended for New Design CAT524 READING DATA Each time data is transferred into a DPP wiper control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DPP’s output. This feature allows µPs to poll DPPs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the non-volatile memory setting is reloaded into the DPP wiper control register. TEMPORARILY CHANGE OUTPUT The CAT524 allows temporary changes in DPP’s output to be made without disturbing the settings retained in non-volatile memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. Figure 3 shows the control and data signals needed to effect a temporary output change. DPP wiper settings may be changed as many times as required and can be made to any of the four DPPs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all four DPPs will return to the output values stored in non-volatile memory. Since this value is the same as that which had been there previously no change in the DPP’s output is noticed. Had the value held in the control register been different from that stored in non-volatile memory then a change would occur at the read cycle’s conclusion. When it is desired to save a new setting acquired using this feature, the new value must be reloaded into the DPP control register prior to programming. This is because the CAT524’s internal control circuitry discards the new data from the programming register two clock cycles after receiving it (after reception is complete) if no PROG signal is received. Figure 3. Temporary Change in Output Figure 2. Reading from Memory to 1 2 3 4 5 6 7 8 9 10 11 12 to CS 1 2 3 4 5 6 A0 A1 D0 D1 D0 D1 7 8 9 10 11 12 N N+1 N+2 CS NEW DPP DATA DI 1 A0 A1 DI 1 D2 D3 D4 D5 D6 D7 D6 D7 CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 D6 CURRENT DPP DATA D7 DO D2 D3 D4 D5 PROG PROG RDY/BSY DPP OUTPUT RDY/BSY CURRENT DPP VALUE DPP OUTPUT NON-VOL ATILE Doc. No. MD-2006 Rev. H 8 CURRENT DPP VALUE NEW DPP VALUE CURRENT DPP VALUE NON-VOL ATILE VOLATILE NON-VOL ATILE © Catalyst Semiconductor, Inc. Characteristics subject to change without notice Not Recommended for New Design CAT524 APPLICATION CIRCUITS +5V VI RI DPP INPUT RF DPP OUTPUT VDPP +15V VDD CONTROL & DATA CAT524 GND MSB – VREFH VDPP + VOUT OP 07 -15V VREFL VOUT = LSB VDPP ( RI + RF ) - VI R F RI For R I = RF VOUT = 2VDPP - VI 1111 1111 1000 0000 0111 1111 0000 0001 0000 0000 ANALOG OUTPUT CODE = x (VFS - VZERO) + VZERO 255 VFS = 0.99VREF VREF = 5V VZERO = 0.01VREF RI = RF 255 × 0.98VREF + 0.01VREF = 0.990 VREF 255 128 × 0.98VREF + 0.01VREF = 0.502VREF 255 127 × 0.98VREF + 0.01VREF = 0.498 VREF 255 1 × 0.98VREF + 0.01VREF = 0.014 VREF 255 0 × 0.98VREF + 0.01VREF = 0.010 VREF 255 VOUT = +4.90V VOUT = +0.02V VOUT = -0 .02V VOUT = -4.86V VOUT = -4.90V Bipolar DPP Output 28 - 32V 15kΩ 10µF 10kΩ 1N5231B VDD CONTROL & DATA VREFH 5.1V CAT524 + MPT3055EL GND VREFL – LM 324 OUTPUT 1.00kΩ 4.02kΩ 10µF 35V 0 - 25V @ 1A Digitally Controlled Voltage Reference © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc. No. MD-2006 Rev. H Not Recommended for New Design CAT524 +5V VREF VIN 1.0µF LM339 + VDD VREFH CAT524 – 10kΩ +5V WINDOW 1 + – DPP1 + – VREF 10kΩ +5V WINDOW 2 + VPP WINDOW 1 VOUT1 – CS WINDOW 2 VOUT2 + DPP2 DI – WINDOW 3 10kΩ +5V WINDOW 3 + DO PROG WINDOW 4 VOUT4 – DPP3 WINDOW 5 + GND – CLK VOUT3 10kΩ WINDOW STRUCTURE +5V WINDOW 4 + – + DPP4 – GND 10kΩ +5V VREFL WINDOW 5 + – Staircase Window Comparator Doc. No. MD-2006 Rev. H 10 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice Not Recommended for New Design CAT524 +5V VREF VIN 1.0µF LM339 + – 10kΩ +5V VDD VREFH WINDOW 1 + CAT524 – DPP1 + – 10kΩ +5V WINDOW 2 VREF WINDOW 1 + VOUT1 – WINDOW 2 CS VOUT2 + DPP2 DI – WINDOW 3 10kΩ +5V DO WINDOW 4 WINDOW 5 GND + DPP3 VOUT3 VOUT4 – PROG CLK WINDOW 3 + – WINDOW STRUCTURE 10kΩ +5V WINDOW 4 + – + DPP4 – GND 10kΩ +5V VREFL WINDOW 5 + – Overlapping Window Comparator © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc. No. MD-2006 Rev. H Not Recommended for New Design CAT524 PACKAGE OUTLINE DRAWING PDIP 14-Lead (L) (1)(2) SYMBOL NOM A 3.56 0.38 5.33 A2 2.92 3.30 4.95 b 0.36 0.45 0.55 b1 1.15 1.52 1.77 c 0.21 0.26 0.35 D 18.67 19.05 19.68 E 7.62 7.87 8.25 E1 6.10 6.35 7.11 e TOP VIEW MAX A1 E1 D MIN 2.54 BSC eB 7.88 L 2.99 10.92 3.30 3.81 E A2 A c A1 e L b b1 eB SIDE VIEW END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-001. Doc. No. MD-2006 Rev. H 12 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice Not Recommended for New Design CAT524 SOIC 14-Lead (W) (1)(2) E1 SYMBOL MIN A 1.35 NOM MAX A1 0.10 0.25 b 0.33 0.51 1.75 c 0.19 D 8.55 8.65 8.75 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 E e 0.25 1.27 BSC h 0.25 0.50 L 0.40 1.27 θ 0º 8º PIN#1 IDENTIFICATION TOP VIEW h D θ A e b c L A1 SIDE VIEW END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-012. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 13 Doc. No. MD-2006 Rev. H Not Recommended for New Design CAT524 EXAMPLE OF ORDERING INFORMATION Prefix Device # Suffix CAT 524 W Optional Company ID I Temperature Range I = Industrial (-40ºC to 85ºC) Product Number 524 T2 Tape & Reel T: Tape & Reel 2: 2000/Reel Package L: PDIP W: SOIC Notes: (1) (2) (3) All packages are RoHS compliant (Lead-free, Halogen-free). Standard lead finish is Matte-Tin. This device used in the above example is a CAT524WI-T2 (SOIC, Industrial Temperature, Tape & Reel). ORDERING PART NUMBER CAT524LI CAT524WI Doc. No. MD-2006 Rev. H 14 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice REVISION HISTORY Date 16-Mar-04 Revision D Description Updated Potentiometer Characteristics 12-Jul-04 E Updated Functional Diagram Updated Potentiometer Characteristics Added Note 3 under Potentiometer/AC Characteristics tables 26-Jul-07 F Added Package Outline Drawings Updated Example of Ordering Information Added MD- in front of Document No. 08-Oct-07 G Change title Update Writing to memory Update Application Circuits 15-Jul-08 H Add “Not Recommended for New Design” to the top of all pages Copyrights, Trademarks and Patents © Catalyst Semiconductor, Inc. Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quantum Charge Programmable™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 0Hwww.catsemi.com Document No: MD-2006 Revision: H Issue date: 07/15/08