CAT874-80ULGT3

CAT874 Smart Phone Battery Switch Controller Description CAT874 is a switch controller designed to start/shut−off smart phones with the push button input or by phone microcontroller unit. CAT874 monitors two inputs and outputs an active high output after PWR_ON input has been active (logic low) for a factory preset minimum time. Releasing input from its active state before the minimum timeout period resets the internal timer and must return to being active before the timer will restart with a fresh count down. The output remains high until the next PWR_ON high−to−low or VCHG low−to−high transition. CAT874’s push pull output is capable of sinking up to 3 mA of current. http://onsemi.com 1 ULLGA−6 UL SUFFIX CASE 613AF Features MARKING DIAGRAM Operate on 1.8 V to 5.5 V Power Supplies Ultra Low Quiescent Current: 100 nA (typical) Schmitt Trigger Inputs Small mLLGA−6 Package: 1.45 x 1.0 x 0.4 mm These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant X = Specific Device Code = ( = CAT874) = Date Code M “P” written at 180° clockwise rotation Typical Applications • • • • XM P • • • • • Mobile Phones PDAs MP3 Players Personal Navigation Devices PIN CONNECTIONS PWR ON 1 VDD VCHG OUT NIC GND (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Figure 1. Application Schematic © Semiconductor Components Industries, LLC, 2013 July, 2013 − Rev. 1 1 Publication Order Number: CAT874/D CAT874 Figure 2. Functional Block Diagram Table 1. PIN FUNCTION DESCRIPTION Pin No. Pin Name Description 1 PWR_ON Power ON, CMOS input. 2 VCHG Charger IN, CMOS input. 3 NIC No Internal Connection. A voltage or signal applied to this pin will have no effect on device operation. 4 GND System Ground. 5 OUT Drive Output. Active−high push−pull output. 6 VDD Positive Power Supply. Table 2. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage Range VDD −0.3 to 6 V Output Voltage Range VOUT −0.3 to 6 or (VDD + 0.3), whichever is lower V Input Voltage; PWR_ON, VCHG VIN −0.3 to 6 or (VDD + 0.3), whichever is lower V Maximum Junction Temperature TJ(max) 150 °C Output Current; OUT IOUT 10 mA Storage Temperature Range TSTG −65 to 150 °C ESD Capability, Human Body Model (Note 1) ESDHBM 2 kV ESD Capability, Machine Model (Note 2) ESDMM 150 V TSLD 260 °C Lead Temperature Soldering Reflow (SMD Styles Only), Pb−Free Versions (Note 2) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) Latch−up Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78 2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D Table 3. RECOMMENDED OPERATING CONDITIONS Rating Symbol Min Max Unit Input Voltage; VDD VDD 1.8 5.5 V Input Voltage; PWR_ON, VCHG VIN 0 VDD V Output Current; OUT IOUT 0 3 mA Ambient Temperature TA −40 85 °C http://onsemi.com 2 CAT874 Table 4. ELECTRICAL OPERATING CHARACTERISTICS (VDD = 1.8 V to 5.5 V. For typical values TA = 25°C, for min/max values TA = −40°C to +85°C unless otherwise noted.) Parameter Test Conditions Symbol Min VDD 1.8 Typ Max Unit 5.5 V 1000 nA 50 mA POWER VDD Supply Voltage Quiescent Supply Current PWR_ON = VDD, VCHG = 0 V Operating Supply Current PWR_ON = 0 V, VCHG = 0 V Measured during setup period. Measurement includes current through internal 200 kW pull−up resistor on PWR_ON IDD 100 LOGIC INPUTS AND OUTPUTS Input Voltage; HIGH PWR_ON, VCHG VIH Input Voltage; LOW PWR_ON, VCHG VIL Hysteresis 0.7 x VDD V 0.25 x VDD VHYS 250 V mV Input Current VCHG VCHG = 0 V; VDD = 5 V (internal pull−down) IIL1 50 300 Input Current VCHG VCHG = 5 V; VDD = 5 V (internal pull−down) IIH1 25 mA Input Current PWR_ON PWR_ON = 0 V; VDD = 5 V (internal 200 kW pull−up resistor) IIL2 25 mA Input Current PWR_ON PWR_ON = 5 V; VDD = 5 V (internal 200 kW pull−up resistor) IIH2 50 Output Voltage; HIGH ISOURCE = −0.1 mA, VDD = 1.8 V VOH Output Voltage; LOW ISINK = 3 mA, VDD = 1.8 V VOL 300 VDD − 0.2 nA nA V 0.1 0.4 V 8.00 9.44 s TIMING Input Delay PWR_ON tlow_delay TA = 25°C TA = −40°C to +85°C 6.56 6.00 10.00 TEST MODE (VDD = 5 V, TA = 25°C) (Note 3) tST Start TEST Window 35 ms Test Mode Delay PWR_ON = 0 V, VCHG → 7 cycles, delay measured after 8th rising edge of VCHG clock pulse tD 250 ms Test Mode Clock Frequency Clock applied to VCHG ftm 1 MHz PWR_ON Test Mode Clock Setup Time Measured from PWR_ON falling edge to first falling edge of VCHG tP VCHG Input Voltage; LOW VCHG, Test Mode Operation 1 ms VIL_TM VCHG Pulse Width tpw 3. “Test Mode” parameters are not tested in production. http://onsemi.com 3 0.2 x VDD 500 V ns CAT874 TIMING WAVEFORMS H VBAT L H VCHG L H PWRON L H OUT L