CS2841B
Automotive Current Mode
PWM Control Circuit
The CS2841B provides all the necessary features to implement
off-line fixed frequency current-mode control with a minimum
number of external components.
The CS2841B (a variation of the CS2843A) is designed specifically
for use in automotive operation. The low start threshold voltage of 8.0 V
(typ), and the ability to survive 40 V automotive load dump transients
are important for automotive subsystem designs. The CS2841 series
has a history of quality and reliability in automotive applications.
The CS2841B incorporates a precision temperature-controlled
oscillator with an internally trimmed discharge current to minimize
variations in frequency. Duty-cycles greater than 50% are also
possible. On board logic ensures that VREF is stabilized before the
output stage is enabled. Ion implant resistors provide tighter control of
undervoltage lockout.
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PDIP-8
N SUFFIX
CASE 626
8
1
SOIC-14
D SUFFIX
CASE 751A
14
1
Features
•Optimized for Off-Line Control
•Internally Trimmed Temperature Compensated Oscillator
•Maximum Duty-Cycle Clamp
•VREF Stabilized Before Output Stage Enabled
•Low Start-Up Current
•Pulse-By-Pulse Current Limiting
•Improved Undervoltage Lockout
•Double Pulse Suppression
•1.0 % Trimmed Bandgap Reference
•High Current Totem Pole Output
•Pb-Free Packages are Available*
PIN CONNECTIONS AND
MARKING DIAGRAM
VREF
COMP
CS2841BEB
AWL
YYWWG
VFB
Sense
OSC
VCC
VOUT
GND
PDIP-8
14
CS2841BD14G
AWLYWW
VFB
NC
Sense
NC
OSC
1
COMP
NC
VREF
NC
VCC
VCC PWR
VOUT
PWR GND
GND
SOIC-14
CS2841B
A
WL
YY, Y
WW
G
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2008
March, 2008 - Rev. 8
1
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
CS2841B/D
CS2841B
VCC
VCC Pwr
Undervoltage
Lockout Circuit
Set/
Reset
GND
5.0 V
Reference
VREF
8.0 V/7.4 V
Internal
Bias
2.5 V
Output
Enable
NOR
Oscillator
OSC
VOUT
S
VFB
+
Error
Amplifier
2R
VC
R
R
1.0 V
PWM
Latch
Pwr GND
Current
Sensing
Comparator
COMP
Sense
Figure 1. Block Diagram
MAXIMUM RATINGS
Rating
Value
Unit
40
V
Output Current
±1.0
A
Output Energy (Capacitive Load)
5.0
mJ
-0.3 to 5.5
V
10
mA
260 peak
230 peak
°C
°C
Supply Voltage (Low Impedance Source)
Analog Inputs (VFB, Sense)
Error Amp Output Sink Current
Lead Temperature Soldering
Wave Solder (through hole styles only) Note 1
Reflow (SMD styles only) Note 2
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 10 seconds max
2. 60 seconds max above 183°C
ORDERING INFORMATION
Device
CS2841BEBN8
Package
Shipping†
PDIP-8
50 Units / Rail
CS2841BEBN8G
PDIP-8
(Pb-Free)
50 Units / Rail
CS2841BED14
SOIC-14
55 Units / Rail
CS2841BED14G
SOIC-14
(Pb-Free)
55 Units / Rail
CS2841BEDR14
SOIC-14
2500 / Tape & Reel
CS2841BEDR14G
SOIC-14
(Pb-Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
CS2841B
ELECTRICAL CHARACTERISTICS (-40°C ≤ TA ≤ 85°C, RT = 680 kW, CT = 0.022 mF for Triangular Mode, VCC = 15 V (Note 3),
RT = 10 kW, CT = 3.3 nF for Sawtooth Mode (see Figure 7); unless otherwise specified.)
Test Conditions
Characteristic
Min
Typ
Max
Unit
4.9
5.0
5.1
V
Reference Section
Output Voltage
TJ = 25°C, IOUT = 1.0 mA
Line Regulation
8.4 ≤ VCC ≤ 16 V
-
6.0
20
mV
Load Regulation
1.0 ≤ IOUT ≤ 20 mA
-
6.0
25
mV
Temperature Stability
Note 4
-
0.2
0.4
mV/°C
Total Output Variation
Line, Load, Temp. Note 4
4.82
-
5.18
V
Output Noise Voltage
10 Hz ≤ f ≤ 10 kHz, TJ = 25°C. Note 4
-
50
-
mV
Long Term Stability
TA = 125°C, 1000 Hrs. Note 4
-
5.0
25
mV
Output Short Circuit
TA = 25°C
-30
-100
-180
mA
Initial Accuracy
Sawtooth Mode: TJ = 25°C. See Figure 7.
Sawtooth Mode: -40°C ≤ TA ≤ +85°C
Triangular Mode: TJ =25°C. See Figure 7.
47
44
44
52
52
52
57
60
60
kHz
kHz
kHz
Voltage Stability
8.4 ≤ VCC ≤ 16 V
-
0.2
1.0
%
Temperature Stability
Sawtooth Mode: TMIN ≤ TA ≤ TMAX. Note 4
Triangular Mode: TMIN ≤ TA ≤ TMAX. Note 4
-
5.0
8.0
-
%
%
Amplitude
VOSC (Peak to Peak)
-
1.7
-
V
Discharge Current
TJ = 25°C
TMIN ≤ TA ≤ TMAX
7.4
7.2
8.3
-
9.2
9.4
mA
mA
Input Voltage
VCOMP = 2.5 V
2.42
2.5
2.58
V
Input Bias Current
VFB = 0 V
-
-0.3
-2.0
mA
AVOL
2.0 ≤ VOUT ≤ 4.0 V
65
90
-
dB
Unity Gain Bandwidth
Note 4
0.7
1.0
-
MHz
PSRR
8.4 V ≤ VCC ≤ 16 V
60
70
-
dB
Output Sink Current
VFB = 2.7 V, VCOMP = 1.1 V
2.0
6.0
-
mA
Output Source Current
VFB = 2.3 V, VCOMP = 5.0 V
-0.5
-0.8
-
mA
VOUT High
VFB = 2.3 V, RL = 15 kW to Ground
5.0
6.0
-
V
VOUT Low
VFB = 2.7 V, RL = 15 kW to VREF
-
0.7
1.1
V
Oscillator Section
Error Amp Section
Current Sense Section
Gain
Notes 5 and 6
2.85
3.0
3.15
V/V
Maximum Input Signal
VCOMP = 5.0 V. Note 5
0.9
1.0
1.1
V
PSRR
12 V ≤ VCC ≤ 25 V. Note 5
-
70
-
dB
Input Bias Current
VSense = 0 V
-
-2.0
-10
mA
Delay to Output
TJ = 25°C. Note 4
-
150
300
ns
3.
4.
5.
6.
Adjust VCC above the start threshold before setting at 15 V
These parameters, although guaranteed, are not 100% tested in production
Parameter measured at trip point of latch with VFB = 0
Gain defined as:
A+
DVCOMP
; 0 v VSense v 0.8V.
DVSense
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3
CS2841B
ELECTRICAL CHARACTERISTICS (-40°C ≤ TA ≤ 85°C, RT = 680 kW, CT = 0.022 mF for Triangular Mode, VCC = 15 V (Note 3),
RT = 10 kW, CT = 3.3 nF for Sawtooth Mode (see Figure 7); unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Output Section
Output Low Level
ISINK = 20 mA
ISINK = 200 mA
-
0.1
1.5
0.4
2.2
V
V
Output High Level
ISOURCE = 20 mA
ISOURCE = 200 mA
13
12
13.5
13.5
-
V
V
Rise Time
TJ = 25°C, CL = 1.0 nF. Note 7
-
50
150
ns
Fall Time
TJ = 25°C, CL = 1.0 nF. Note 7
-
50
150
ns
Output Leakage
Undervoltage Active, VOUT = 0
-
-0.01
-10
mA
-
-
0.5
1.0
mA
VFB = VSense = 0 V, RT = 10 kW, CT = 3.3 nF
-
11
17
mA
-
7.6
8.0
8.4
V
7.0
7.4
7.8
V
Total Standby Current
Startup Current
Operating Supply Current ICC
Undervoltage Lockout Section
Start Threshold
Min. Operating Voltage
After Turn On
7. These parameters, although guaranteed, are not 100% tested in production.
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
PDIP-8
SOIC-14
PIN SYMBOL
1
1
COMP
2
3
VFB
3
5
Sense
4
7
OSC
Oscillator Timing Network with Capacitor to Ground, Resistor to VREF
5
8
GND
Ground
9
Pwr GND
10
VOUT
11
VCC Pwr
7
12
VCC
Positive Power Supply
8
14
VREF
Output of 5.0 V Internal Reference
2, 4, 6, 13
NC
6
FUNCTION
Error Amp Output, Used to Compensate Error Amplifier
Error Amp Inverting Input
Noninverting Input to Current Sense Comparator
Output Driver Ground
Output Drive Pin
Output Driver Positive Supply
No Connection
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4
CS2841B
TYPICAL PERFORMANCE CHARACTERISTICS
100
900
90
RT = 680 W
700
Duty Cycle (%)
600
RT = 1.5 kW
300
70
60
50
40
30
20
RT = 10 kW
7k
.02 .03 .04 .05
10 k
.01
CT (mF)
3k
4k
5k
.002 .003 .005
2k
.001
1k
.0005
700
10
100
300
400
500
200
200
500
400
80
100
Frequency (kHz)
800
RT (W)
Figure 2. Oscillator Frequency vs. CT
Figure 3. Oscillator Duty Cycle vs. RT
VREF
RT
2N2222
4.7 kW
A
VREF
COMP
0.1 mF
1.0 kW
Error Amp
Adjust
4.7 kW
VCC
100 kW
VFB
5.0 kW
Sense
Adjust
VCC
0.1 mF
CS2841B
Sense
VOUT
OSC
GND
1.0 kW
1.0 W
VOUT
GND
CT
Figure 4. Test Circuit
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5
CS2841B
CIRCUIT DESCRIPTION
Undervoltage Lockout
When the power supply sees a sudden large output current
increase, the control voltage will increase allowing the duty
cycle to momentarily increase. Since the duty cycle tends to
exceed the maximum allowed to prevent transformer
saturation in some power supplies, the internal oscillator
waveform provides the maximum duty cycle clamp as
programmed by the selection of OSC components.
During Undervoltage Lockout (Figure 5), the output
driver is biased to a high impedance state. The output should
be shunted to ground with a resistor to prevent output
leakage current from activating the power switch.
ON/OFF Command
to Reset of IC
VCC
VREF
RT
VON = 8.0 V
VOFF = 7.4 V
OSC
CT
GND
ICC
Timing Parameters
< 15 mA
Vupper
< 1.0 mA
VCC
7.4 V
8.0 V
Vlower
tc
Figure 5. Typical Undervoltage Characteristics
td
Sawtooth Mode
Large RT (≈ 10 kW)
PWM Waveform
To generate the PWM waveform, the control voltage from
the error amplifier is compared to a current sense signal
representing the peak output inductor current (Figure 6). An
increase in VCC causes the inductor current slope to
increase, thus reducing the duty cycle. This is an inherent
feed-forward characteristic of current mode control, since
the control voltage does not have to change during changes
of input supply voltage.
VOSC
Internal Clock
Triangular Mode
Small RT (≈ 700 kW)
VOSC
OSC
OSC
RESET
Internal Clock
EA Output
Figure 7. Oscillator Timing Network and
Parameters
Switch
Current
VCC
Setting the Oscillator
IO
Oscillator timing capacitor, CT, is charged by VREF
through RT and discharged by an internal current source.
During the discharge time, the internal clock signal blanks
out the output to the Low state, thus providing a user selected
maximum duty cycle clamp. Charge and discharge times are
determined by the general formulas:
VO
Figure 6. Timing Diagram for Key CS2841B
Parameters
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6
CS2841B
ǒ
V
* Vlower
tc + RTCT ln REF
VREF * Vupper
Ǔ
ǒ
VREF * IdRT * Vupper
td + RTCT ln
VREF * IdRT * Vlower
The frequency and maximum duty cycle can be
determined from the Typical Performance Characteristic
graphs.
Ǔ
Grounding
High peak currents associated with capacitive loads
necessitate careful grounding techniques. Timing and
bypass capacitors should be connected close to GND pin in
a single point ground.
The transistor and 5.0 kW potentiometer are used to
sample the oscillator waveform and apply an adjustable
ramp to Sense.
Substituting in typical values for the parameters in the
above formulas:
VREF + 5.0V
Vupper + 2.7V
Vlower + 1.0V
Id + 8.3mA
tc [ 0.5534RTCT
ǒ
2.3 * 0.0083RT
td + RTCT ln
4.0 * 0.0083RT
VPR
C1
68 mF
GND
Q1
Ǔ
C2
68 mF
C3
4.7 pF
100 V
R1
4.7 k
20T D2 MBR360
R2
47
MURS120T3
D1
2n4401
9T
DZ1
13 V
1N5243B
L1 2.2 mH
C4
0.1 mF
C5
1000 mF
C6
1000 mF
C7
0.1 mF
VCC = 5.0 V @ 750 mA
VC
C8
10 mF
C9
0.1 mF
VCC
PVCC
C12
CS2841B
R5
2.0 k
Q2
MTDISN06VTL4
R4
VOUT
VREF
C10
0.1 mF
R3
4.99 k
1.0 %
10
10 nF
SENSE
R6
1.0 k
OSC
COMP
C11
R7
GND
C13
4.7 nF
PGND VFB
R8
4.99 k
1.0 %
22.1 k 0.33 mF
C14
47 pF
Figure 8. Flyback Application
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7
R9
0.2
1.0 %
VCC
VCC-GND
CS2841B
D1 1N5818
L1
VPR
C1
100 mF
100 V
GND
17 V
100 mH
C2
330 mF
C3
0.1 mF
R2
10
C4
10 mF
R1
12 k
C5
0.1 mF
VCC
VOUT
VREF
C6
0.1 mF
10
R5
CS2841B
R4
3.0 k
SENSE
100
COMP
OSC
Q1
MTP12N10
R3
C7
0.01 mF
FB
GND
R8
2.0 k
C9
470 pF
C8
1.0 nF
D2
1N5818
R6
10 k
R7
1.0
Input Voltage Range: 8.0 V to 16 V
Output Voltage: 17 V @ 100 mA > 300 mA
Figure 9. Boost Application
PACKAGE THERMAL DATA
Parameter
PDIP-8
SOIC-14
Unit
RqJC
Typical
52
30
°C/W
RqJA
Typical
100
125
°C/W
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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