EMI4192MTTAG

EMI4192 Common Mode Filter with ESD Protection Functional Description The EMI4192 is an integrated common mode filter providing both ESD protection and EMI filtering for high speed digital serial interfaces such as HDMI or MIPI D−PHY. The EMI4192 provides protection for two differential data line pairs in a small RoHS−compliant WDFN10 package. http://onsemi.com MARKING DIAGRAMS Features • Highly Integrated Common Mode Filter (CMF) with ESD Protection • • • • • • provides protection and EMI reduction for systems using High Speed Serial Data Lines with cost and space savings over discrete solutions Large Differential Mode Bandwidth with Cutoff Frequency > 2 GHz High Common Mode Stop Band Attenuation Provides ESD Protection to IEC61000−4−2 Level 4, ±15 kV Contact Discharge Low Channel Input Capacitance Provides Superior Impedance Matching Performance Low Profile Package with Small Footprint in WDFN10 2 x 2.5 mm Pb−Free Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Applications • HDMI/DVI Display in Mobile Phones • MIPI D−PHY (CSI−2, DSI, etc) in Mobile Phones and Digital Still 43 M G = Specific Device Code = Date Code = Pb−Free Package (*Note: Microdot may be in either location) PIN CONNECTIONS In_1+ 1 10 Out_1+ In_1− 2 9 Out_1− GND 3 8 GND In_2+ 4 7 Out_2+ In_2− 5 6 Out_2− Cameras 1 43 MG G WDFN10 CASE 511BM 10 2 External (Connector) 4 9 5 6 7 Internal (ASIC) ORDERING INFORMATION Device Package Shipping† EMI4192MTTAG WDFN10 (Pb−Free) 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 3, 8 Figure 1. EMI4192 Electrical Schematic © Semiconductor Components Industries, LLC, 2013 April, 2013 − Rev. 2 1 Publication Order Number: EMI4192/D EMI4192 PIN FUNCTION DESCRIPTION Pin Name Pin No. Type In_1+ 1 I/O CMF Channel 1+ to Connector Description In_1− 2 I/O CMF Channel 1− to Connector Out_1+ 10 I/O CMF Channel 1+ to ASIC Out_1− 9 I/O CMF Channel 1− to ASIC In_2+ 4 I/O CMF Channel 2+ to Connector In_2− 5 I/O CMF Channel 2− to Connector Out_2+ 7 I/O CMF Channel 2+ to ASIC Out_2− 6 I/O CMF Channel 2− to ASIC VN 3, 8 GND Ground ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Parameter Symbol Value Unit Operating Temperature Range TOP −40 to +85 °C Storage Temperature Range TSTG −65 to +150 °C ESD Discharge IEC61000−4−2 Contact Discharge VPP ±15 kV TL 260 °C ILINE 100 mA Maximum Lead Temperature for Soldering Purposes (1/8” from Case for 10 seconds) DC Current per Line Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Test Conditions Min Typ Max Unit 1.0 mA 1.5 V 0.8 1.3 pF 3.5 5.0 W ILEAK Channel Leakage Current TA = 25°C, VIN = 5 V, GND = 0 V VF Channel Negative Voltage TA = 25°C, IF = 10 mA CIN Channel Input Capacitance to Ground (Pins 1, 2, 4, 5 to Pins 3, 8) TA = 25°C, At 1 MHz, GND = 0 V, VIN = 1.65 V RCH Channel Resistance (Pins 1−10, 2−9, 4−7 and 5−6) f3dB Differential Mode Cut−off Frequency 50 W Source and Load Termination Common Mode Stop Band Attenuation @ 900 MHz Common Mode Impedance @ 100 MHz ESD Protection − Peak Discharge Voltage at any channel input, in system: Contact discharge per IEC61000−4−2 standard TA = 25°C (Notes 1 and 2) Pins 1, 2, 4, 5 TLP Clamping Voltage (See Figure 9) Forward IPP = 8 A Forward IPP = 16 A Forward IPP = −8 A Forward IPP = −16 A 12 18 −6 −12 RDYN Dynamic Resistance Positive Transients Negative Transients TA = 25°C, IPP = 1 A, tP = 8/20 ms Any I/O pin to Ground; Notes 1 and 3 1.36 0.6 VRWM Reverse Working Voltage (Note 3) Breakdown Voltage IT = 1 mA; (Note 4) Fatten ZC VESD VCL VBR 0.1 4.0 GHz 16 dB 32 W kV ±15 5.6 V V V V 5.0 V 9.0 V 1. Standard IEC61000−4−2 with CDischarge = 150 pF, RDischarge = 330, GND grounded. 2. These measurements performed with no external capacitor. 3. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal to or greater than the DC or continuous peak operating voltage level. 4. VBR is measured at pulse test current IT. http://onsemi.com 2 EMI4192 TYPICAL CHARACTERISTICS 0 0 −1 −5 −2 −10 −15 −4 dB dB −3 −5 −20 −25 −6 −7 −30 −8 −35 −9 1E6 1E7 1E8 FREQUENCY (Hz) 1E9 −40 1E10 1E6 Figure 2. Differential Mode Attenuation vs. Frequency 1E7 1E8 1E9 FREQUENCY (Hz) Figure 3. Common Mode Attenuation vs. Frequency MIPI DSI (D−PHY) Host MIPI DSI (D−PHY) Client EMI4192 Evaluation Board Figure 4. MIPI D−PHY LP Mode Test Setup Figure 5. EMI4192 MIPI D−PHY LP Mode Measured Results http://onsemi.com 3 1E10 EMI4192 EMI4192 HDMI source HDMI To SMA N5380A Probe Head TVdd Figure 6. EMI4182 Eye Diagram Test Setup Figure 7. EMI4192 Measured Eye Diagram http://onsemi.com 4 1169A Probe Agilent DSO81204A scope EMI4192 Transmission Line Pulse (TLP) Measurements Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 8. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10 s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 9 where an 8 kV IEC61000−4−2 current waveform is compared with TLP current pulses at 8 and 16 A. A TLP curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. Typical TLP I−V curves for the EMI4192 are shown in Figure 10. L SW 50 W Coax Cable Attenuator 50 W Coax Cable ÷ IM VM 10 MW VC DUT Oscilloscope Figure 8. Simplified Schematic of a Typical TLP System Figure 9. Comparison Between 8 kV IEC61000−4−2 and 8 A and 16 A TLP Waveforms Figure 10. Positive and Negative TLP Waveforms http://onsemi.com 5 EMI4192 ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to On Semiconductor Application Notes AND8307/D and AND8308/D. IEC61000−4−2 Waveform IEC61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Oscilloscope TVS 50 W Cable 50 W Figure 11. Diagram of ESD Test Setup 100 % OF PEAK PULSE CURRENT ESD Gun PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 12. 8 x 20 ms Pulse Waveform http://onsemi.com 6 80 EMI4192 Figure 13. ESD Clamping Voltage +8 kV per IEC6100−4−2 (external to internal pin) Figure 14. ESD Clamping Voltage −8 kV per IEC6100−4−2 (external to internal pin) http://onsemi.com 7 EMI4192 HDMI Type−A Connector TMDS Data 2+ EMI4192 D2+ 1 10 TMDS Data 2− GND D2− TMDS Data 1+ D1+ TMDS Data 1− GND D1− EMI4192 TMDS Data 0+ 10 D0+ 1 TMDS Data 0− GND D0− TMDS Clock+ CLK + TMDS Clock− GND CEC CLK− CEC SCL HEC DATA SDA SCL Hot Plug Detect SDA GND +5V Power NUP4114 5V HTP _D Black = Top layer Red = other layer Figure 15. EMI4192 HDMI Type – A Connector Application Diagram TMDS Data 2+ HDMI Type −D Connector EMI4192 1 10 PIN 1 TMDS Data 2− HTP _D Util D2+ GND TMDS Data 1+ D 2− D 1+ GND TMDS Data 1− D 1− D0+ GND TMDS Data 0+ D 0− CLK + 1 10 TMDS Data 0− GND CLK − CEC GND SCL TMDS Clock + SDA 5V TMDS Clock − EMI4192 Black = Top layer Red = other layer CEC SCL +5V Power SDA NUP4114 Figure 16. EMI4192 HDMI Type − D Connector Application Diagram http://onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WDFN10 2.5x2, 0.5P CASE 511BM−01 ISSUE O DATE 29 JUN 2010 SCALE 4:1 2X 0.10 C PIN 1 REFERENCE 0.10 C 2X 0.05 C L A B D L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L1 ÇÇÇ ÇÇÇ E DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS ÉÉ ÇÇ EXPOSED Cu TOP VIEW (A3) DETAIL B A A3 MOLD CMPD A1 ÇÇ ÉÉ DIM A A1 A3 b D E e L L1 DETAIL B ALTERNATE CONSTRUCTIONS 0.05 C NOTE 4 A1 SIDE VIEW C SEATING PLANE GENERIC MARKING DIAGRAM* DETAIL A 1 5 8X XXMG G L XX = Specific Device Code M = Date Code G = Pb−Free Package 0.10 MIN 10 6 e MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.15 0.25 2.50 BSC 2.00 BSC 0.50 BSC 0.70 0.90 0.05 0.15 9X BOTTOM VIEW (Note: Microdot may be in either location) b 0.10 M C A B 0.05 M C NOTE 3 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. RECOMMENDED MOUNTING FOOTPRINT 8X 8X 0.30 1.07 PACKAGE OUTLINE 2.30 1 0.45 0.50 PITCH DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98AON52152E WDFN10 2.5X2, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. 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