FAN5059M

www.fairchildsemi.com FAN5059 High Performance Programmable Synchronous DC-DC Controller for Multi-Voltage Platforms Features Applications • Programmable output for Vcore from 1.3V to 3.5V using an integrated 5-bit DAC • Controls adjustable linears for Vagp (selectable 1.5V/3.3V), Vclock (2.5V), and Vtt (1.5V) or Vnorthbridge (1.8V) • Meets VRM specification with as few as 5 capacitors • Meets 1.550V +40/-70mV over initial tolerance, temperature and transients • • • • • • • • • • • Remote sense Programmable Active Droop™ (Voltage Positioning) Drives N-Channel MOSFETs Overcurrent protection using MOSFET sensing 85% efficiency typical at full load Integrated Power Good and Enable/Soft Start functions 24 pin SOIC package Power supply for Pentium® III Camino Platform Power supply for Pentium III Whitney Platform VRM for Pentium III processor Programmable multi-output power supply Description The FAN5059 is a synchronous mode DC-DC controller IC which provides a highly accurate, programmable set of output voltages for multi-voltage platforms such as the Intel Camino, and provides a complete solution for the Intel Whitney and other high-performance processors. The FAN5059 features remote voltage sensing, independently adjustable current limit, and a proprietary Programmable Active Droop™ for optimal converter transient response. The FAN5059 uses a 5-bit D/A converter to program the output voltage from 1.3V to 3.5V. The FAN5059 uses a high level of integration to deliver load Block Diagram +5V VCCA 21 +3.3V 9 +1.5V + - RD PWRGD, OCL 10 VCCP 11 19 + REF OCL + - REF +12V PWRGD, OCL 12 +2.5V + OSC RS 20 24 VCCP 1 HIDRV + 15 14 + - V + Digital Control + 2 VCC 23 LODRV PWRGD, OCL 13 +5V 18 22 3.3/1.5V GNDP 5-Bit DAC 8 7 65 4 VID0 VID2 VID4 VID1 VID3 1.24V Reference Power Good 3 GNDA 17 PWRGD 16 ENABLE/SS Pentium is a registered trademark of Intel Corporation. Programmable Active Droop is a trademark of Fairchild Semiconductor. Rev. 1.0.4 FAN5059 PRODUCT SPECIFICATION currents in excess of 16A from a 5V source with minimal external circuitry. Synchronous-mode operation offers optimum efficiency over the entire specified output voltage range. An on-board precision low TC reference achieves tight tolerance voltage regulation without expensive external components, while Programmable Active Droop™ permits exact tailoring of voltage for the most demanding load transients. The FAN5059 includes linear regulator controllers for Vtt termination (1.5V), Vclock (2.5V), and Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V), each adjustable with an external divider. The FAN5059 also offers integrated functions including Power Good, Output Enable/Soft Start and current limiting, and is available in a 24 pin SOIC package. Pin Assignments HIDRV SW GNDA VID4 VID3 VID2 VID1 VID0 VTTGATE VTTFB VCKGATE VCKFB 1 2 3 4 5 6 7 8 9 10 11 12 FAN5059 24 23 22 21 20 19 18 17 16 15 14 13 VCCP LODRV GNDP VCCA VFB DROOP ILIM PWRGD SS/ENABLE TYPEDET VAGPGATE VAGPFB Pin Definitions Pin Number Pin Name 2 Pin Function Description 1 HIDRV High Side FET Driver. Connect this pin through a resistor to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be 15V. The on-resistance (RDS,ON) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation within the MOSFET and therefore significantly REV. 1.0.4 8/14/03 Choosing the value of the inductor is a tradeoff between allowable ripple voltage and required transient response. The system designer can choose any value within the allowed minimum to maximum range in order to either minimize ripple or maximize transient performance. The first order equation (close approximation) for minimum inductance is: Lmin = (Vin – Vout) x Vout Vin f ESR x Vripple where: Vin = Input Power Supply Vout = Output Voltage f = DC/DC converter switching frequency ESR = Equivalent series resistance of all output capacitors in parallel Vripple = Maximum peak to peak output ripple voltage budget. The first order equation for maximum allowed inductance is: Lmax = 2CO (Vin – Vout) Dm Vtb Ipp2 where: Co = The total output capacitance Ipp = Maximum to minimum load transient current Vtb = The output voltage tolerance budget allocated to load transient Dm = Maximum duty cycle for the DC/DC converter (usually 95%). Some margin should be maintained away from both Lmin and Lmax. Adding margin by increasing L almost always adds expense since all the variables are predetermined by system performance except for CO, which must be increased to increase L. Adding margin by decreasing L can be done by purchasing capacitors with lower ESR. The FAN5059 provides significant cost savings for the newer CPU systems that typically run at high supply current. FAN5059 Short Circuit Current Characteristics The FAN5059 protects against output short circuit on the core supply by turning off both the high-side and low-side MOSFETs and resetting softstart. The short circuit limit is set with the RS resistor, as given by the formula RS = ISC *RDS, on IDetect Note: RS cannot exceed 10.8K. If a higher current is required than 10.8K allows, a FET with lower RDSon must be used. 13 FAN5059 PRODUCT SPECIFICATION with IDetect ≈ 50µA, ISC is the desired current limit, and RDS,on the high-side MOSFET’s on resistance. Remember to make the RS large enough to include the effects of initial tolerance and temperature variation on the MOSFET’s RDS,on. Alternately, use of a sense resistor in series with the source of the MOSFET eliminates this source of inaccuracy in the current limit. As an example, Figure 4 shows the typical characteristic of the DC-DC converter circuit with an FDB6030L high-side MOSFET (RDS = 20mΩ maximum at 25°C * 1.25 at 75°C = 25mΩ) and a 8.2KΩ RS. CPU Output Voltage vs. Output Current 3.5 3.0 VOUT (V) 2.5 for the diode is that the forward voltage of the Schottky at the output current should be less than the forward voltage of the MOSFET’s body diode. Output Filter Capacitors The output bulk capacitors of a converter help determine its output ripple voltage and its transient response. It has already been seen in the section on selecting an inductor that the ESR helps set the minimum inductance, and the capacitance value helps set the maximum inductance. For most converters, however, the number of capacitors required is determined by the transient response and the output ripple voltage, and these are determined by the ESR and not the capacitance value. That is, in order to achieve the necessary ESR to meet the transient and ripple requirements, the capacitance value required is already very large. The most commonly used choice for output bulk capacitors is aluminum electrolytics, because of their low cost and low ESR. The only type of aluminum capacitor used should be those that have an ESR rated at 100kHz. Consult Application Bulletin AB-14 for detailed information on output capacitor selection. 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 Figure 4. FAN5059 Short Circuit Characteristic The converter exhibits a normal load regulation characteristic until the voltage across the MOSFET exceeds the internal short circuit threshold of 50µA * 8.2KΩ = 410mV, which occurs at 410mV/25mΩ = 16.4A. (Note that this current limit level can be as high as 410mV/15mΩ = 27A, if the MOSFET has typical RDS,on rather than maximum, and is at 25°C). At this point, the internal comparator trips and signals the controller to discharge the softstart capacitor. This causes a drastic reduction in the output voltage as the load regulation collapses into the short circuit control mode. With a 40mΩ output short, the voltage is reduced to 16.4A * 40mΩ = 650mV. The output voltage does not return to its nominal value until the output current is reduced to a value within the safe operating ranges for the DC-DC converter. If any of the linear regulator outputs are loaded heavily enough that their output voltage drops below 80% of nominal for >30µsec, all FAN5059 outputs, including the switcher, are shut off and remain off until power is recycled. The output capacitance should also include a number of small value ceramic capacitors placed as close as possible to the processor; 0.1µF and 0.01µF are recommended values. Input Filter The DC-DC converter design may include an input inductor between the system +5V supply and the converter input as shown in Figure 5. This inductor serves to isolate the +5V supply from the noise in the switching portion of the DC-DC converter, and to limit the inrush current into the input capacitors during power up. A value of 2.5µH is recommended. It is necessary to have some low ESR aluminum electrolytic capacitors at the input to the converter. These capacitors deliver current when the high side MOSFET switches on. Figure 5 shows 3 x 1000µF, but the exact number required will vary with the speed and type of the processor. For the top speed Katmai and Coppermine, the capacitors should be rated to take 9A and 6A of ripple current respectively. Capacitor ripple current rating is a function of temperature, and so the manufacturer should be contacted to find out the ripple current rating at the expected operational temperature. For details on the design of an input filter, refer to Applications Bulletin AB-15. Schottky Diode Selection The application circuit of Figure 1 shows a Schottky diode, D1, which is used as a free-wheeling diode to assure that the body-diode in Q2 does not conduct when the upper MOSFET is turning off and the lower MOSFET is turning on. It is undesirable for this diode to conduct because its high forward voltage drop and long reverse recovery time degrades efficiency, and so the Schottky provides a shunt path for the current. Since this time duration is very short, the selection criterion 14 2.5µH Vin 5V 1000µF, 10V Electrolytic 0.1µF Figure 5. Input Filter REV. 1.0.4 8/14/03 PRODUCT SPECIFICATION FAN5059 Programmable Active Droop™ Using the FAN5059 for Vnorthbridge = 1.8V The FAN5059 includes Programmable Active Droop™: as the output current increases, the output voltage drops, and the amount of this drop is user adjustable. This is done in order to allow maximum headroom for transient response of the converter. The current is typically sensed by measuring the voltage across the RDS,on of the high-side MOSFET during its on time, as shown in Figure 1. In some motherboards, Intel requires that the AGP power can not be greater than 2.2V while the chipset voltage (Vnorthbridge = 1.8V) is less than 1.0V. The FAN5059 can accomplish this by using the VTT regulator to generate Vnorthbridge. Use the circuit in Figure 6 with R = 2KΩ. Since the linear regulators on the FAN5059 all rise proportionally to one another, when Vnorthbridge = 1.0V, Vagp = 1.8V, meeting the Intel requirement. To program the amount of droop, use the formula PCB Layout Guidelines 14.4KΩ *Imax *Rsense RD VDroop *18 where Imax is the current at which the droop occurs, and Rsense is the resistance of the current sensor, either the source resistor or the high-side MOSFET’s on-resistance. For example, to get 30mV of droop with a maximum output current of 12.5A and a 10mΩ sense resistor, use RD = 14.4KΩ * 12.5A * 10mΩ/ (30mV * 18) = 3.33KΩ. Further details on use of the Programmable Active Droop™ may be found in Applications Bulletin AB-24. Remote Sense The FAN5059 offers remote sense of the output voltage to minimize the output capacitor requirements of the converter. It is highly recommended that the remote sense pin, Pin 20, be tied directly to the processor power pins, so that the effects of power plane impedance are eliminated. Further details on use of the remote sense feature of the FAN5059 may be found in Applications Bulletin AB-24. Adjusting the Linear Regulators’ Output Voltages Any or all of the linear regulators’ outputs may be adjusted high to compensate for voltage drop along traces, as shown in Figure 6. • Placement of the MOSFETs relative to the FAN5059 is critical. Place the MOSFETs such that the trace length of the HIDRV and LODRV pins of the FAN5059 to the FET gates is minimized. A long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the FET. This noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very difficult to suppress. • In general, all of the noisy switching lines should be kept away from the quiet analog section of the FAN5059. That is, traces that connect to pins 1, 2, 23, and 24 (HIDRV, SW, LODRV and VCCP) should be kept far away from the traces that connect to pins 3, 20 and 21. • Place the 0.1µF decoupling capacitors as close to the FAN5059 pins as possible. Extra lead length on these reduces their ability to suppress noise. • Each VCC and GND pin should have its own via to the appropriate plane. This helps provide isolation between pins. • Place the MOSFETs, inductor, and Schottky as close together as possible for the same reasons as in the first bullet above. Place the input bulk capacitors as close to the drains of the high side MOSFETs as possible. In addition, placement of a 0.1µF decoupling cap right on the drain of each high side MOSFET helps to suppress some of the high frequency switching noise on the input of the DC-DC converter. VGATE VOUT R VFB 10KΩ Figure 6. Adjusting the Output Voltage of the Linear Regulator • A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-11. The resistor value should be chosen as R = 10KΩ* Vout Vnom • Place the output bulk capacitors as close to the CPU as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. Additional space between the output capacitors and the CPU will allow the parasitic resistance of the board traces to degrade the DC-DC converter’s performance under severe load transient conditions, causing higher voltage deviation. For more detailed information regarding capacitor placement, refer to Application Bulletin AB-5. –1 Note: See Note 4 in Electrical Specifications Table. Additional Information For additional information contact Fairchild Semiconductor at http://www.fairchildsemi.com/cf/tsg.htm or contact an authorized representative in your area. For example, to get the VTT voltage to be 1.55V instead of 1.50V, use R = 10KΩ * [(1.55/1.50) – 1] = 333Ω. REV. 1.0.4 8/14/03 15 FAN5059 PRODUCT SPECIFICATION The value of R7 must be ≤ 8.3KΩ. If a greater value is calculated, RD must be reduced. Appendix Worst-Case Formulae for the Calculation of Cin, Cout , R5, R7 and Roffset (Circuits similar to Figure 1 only) The following formulae design the FAN5059 for worst-case operation, including initial tolerance and temperature dependence of all of the IC parameters (initial setpoint, reference tolerance and tempco, internal droop impedance, current sensor gain), the initial tolerance and temperature dependence of the MOSFET, and the ESR of the capacitors. The following information must be provided: Number of capacitors needed for Cout = the greater of: ESR * IO X = VT- + VS+ – .024 * Vnom or VS+, the value of the positive static voltage limit; ESR * IO Y= |VS-|, the absolute value of the negative static voltage limit; 14400 * IO * RD VT+ – VS+ + 18 * R5 * 1.1 VT+, the value of the positive transient voltage limit; |VT-|, the absolute value of the negative transient voltage limit; Vin, the input voltage (typically 5V); Example: Suppose that the static limits are +89mV/-79mV, transient limits are ±134mV, current I is 14.2A, and the nominal voltage is 2.000V, using MOSFET current sensing. We have VS+ = 0.089, |VS-| = 0.079, VT+ = |VT-| = 0.134, IO = 14.2, Vnom = 2.000, and ∆RD = 1.67. We calculate: Irms, the ripple current rating of the input capacitors, per cap (2A for the Sanyo parts shown in this datasheet); Since Y > X, we choose Y, and round up to find we need 7 capacitors for COUT. RD, the resistance of the current sensor (usually the MOSFET); A detailed explanation of this calculation may be found in Applications Bulletin AB-24. IO, the maximum output current; Vnom, the nominal output voltage; ∆RD, the tolerance of the current sensor (usually about 67% for MOSFET sensing, including temperature); and ESR, the ESR of the output capacitors, per cap (44mΩ for the Sanyo parts shown in this datasheet). 2.000 14.2 * 5 – 2.000 2 5 = 3.47 ⇒ 4 caps Cin = 2 IO * Vnom – Vin 2 Vnom Vin Roffset = 0.089 – .024 * 2.000 *1000 = 20.3Ω 1.01 * 2.000 Cin = Irms R7 = Roffset = VS+ – .024 * Vnom 14.2 * 0.010 * (1 + 0.67) = 5.25KΩ 45 * 10-6 * 1KΩ 1.01 * Vnom R5 = 14400 * 14.2 * 0.020 * (1 + 0.67) * 1.1 = 3.48KΩ 18 * (0.089 + 0.079 – .024 * 2.000) R7 = IO* RD * (1 + ∆RD) 45 * 10-6 14400 * IO* RD * (1 + ∆RD) *1.1 R5 = 18 * (VS+ + VS- – .024 * Vnom) 16 X= 0.044 * 14.2 = 3.57 0.134 + 0.089 – .024 * 2.00 0.044 * 14.2 = 6.14 Y = 0.134 – 0.089 + 14400 * 14.2 * 0.020 18 * 3640 * 1.1 REV. 1.0.4 8/14/03 PRODUCT SPECIFICATION FAN5059 Mechanical Dimensions 24 Lead SOIC Inches Symbol Notes: Millimeters Notes Min. Max. Min. Max. A A1 B C D .093 .004 .013 .009 .599 .104 .012 2.35 0.10 0.33 0.23 15.20 2.65 0.30 E e H h L N α ccc .290 .299 .050 BSC .394 .419 7.36 7.60 1.27 BSC 10.00 10.65 .010 .016 0.25 0.40 .020 .013 .614 .020 .050 24 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 0.51 0.32 15.60 4. Terminal numbers are shown for reference only. 5 2 2 0.51 1.27 0° 8° 0° 8° .004 — 0.10 24 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals. 3 6 24 — 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 13 E 1 H 12 h x 45° D C A1 A e B SEATING PLANE –C– α L LEAD COPLANARITY ccc C REV. 1.0.4 8/14/03 17 FAN5059 PRODUCT SPECIFICATION Ordering Information Product Number Package FAN5059M 24 pin SOIC DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 8/14/03 0.0m 012 Stock#DS30005059  2000 Fairchild Semiconductor Corporation