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FDMT80060DC
N-Channel Dual CoolTM 88 PowerTrench® MOSFET
60 V, 292 A, 1.1 mΩ
Features
General Description
Max rDS(on) = 1.1 mΩ at VGS = 10 V, ID = 43 A
Max rDS(on) = 1.3 mΩ at VGS = 8 V, ID = 37 A
Advanced Package and Silicon combination for low rDS(on)
and high efficiency
Next generation enhanced
engineered for soft recovery
body
diode
This N-Channel MOSFET is produced using Fairchild
process.
Semiconductor’s
advanced
PowerTrench®
Advancements in both silicon and Dual CoolTM package
technologies have been combined to offer the lowest rDS(on)
while maintaining excellent switching performance by extremely
low Junction-to-Ambient thermal resistance.
technology,
Low profile 8x8mm MLP package
Applications
MSL1 robust package design
OringFET / Load Switching
100% UIL tested
Synchronous Rectification
RoHS Compliant
DC-DC Conversion
Pin 1
Pin 1
G
S
S
S
S
D
Top
TM
Dual Cool
D
D
D
G
D
S
D
S
D
S
D
Bottom
88
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.
Symbol
VDS
Drain to Source Voltage
Parameter
VGS
Gate to Source Voltage
Drain Current -Continuous
TC = 25 °C
-Continuous
-Continuous
ID
TJ, TSTG
±20
V
292
TC = 100°C
(Note 5)
184
TA = 25 °C
(Note 1a)
43
-Pulsed
PD
Units
V
(Note 5)
Single Pulse Avalanche Energy
EAS
Ratings
60
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
(Note 4)
1825
(Note 3)
2400
156
(Note 1a)
Operating and Storage Junction Temperature Range
3.2
-55 to +150
A
mJ
W
°C
Thermal Characteristics
RθJC
Thermal Resistance, Junction-to-Case
(Top Source)
1.6
RθJC
Thermal Resistance, Junction-to-Case
(Bottom Drain)
0.8
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
38
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1b)
81
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1i)
15
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1j)
21
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1k)
9
°C/W
Package Marking and Ordering Information
Device Marking
80060DC
Device
FDMT80060DC
©2015 Fairchild Semiconductor Corporation
FDMT80060DC Rev. 1.1
Package
Dual CoolTM 88
1
Reel Size
13”
Tape Width
13.3 mm
Quantity
3000 units
www.fairchildsemi.com
FDMT80060DC N-Channel Dual CoolTM 88 PowerTrench® MOSFET
August 2015
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
IDSS
Zero Gate Voltage Drain Current
VDS = 48 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS = ±20 V, VDS = 0 V
±100
nA
4.0
V
60
V
30
mV/°C
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
-13
VGS = 10 V, ID = 43 A
0.87
1.1
rDS(on)
Static Drain to Source On Resistance
VGS = 8 V, ID = 37 A
1.1
1.3
VGS = 10 V, ID = 43 A, TJ = 125 °C
1.3
1.7
VDS = 5 V, ID = 43 A
134
gFS
Forward Transconductance
2.0
3.5
mV/°C
mΩ
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate Resistance
VDS = 30 V, VGS = 0 V,
f = 1 MHz
0.1
14406
20170
pF
3222
4515
pF
87
175
pF
1.8
4.5
Ω
75
120
ns
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Rise Time
td(off)
Turn-Off Delay Time
VDD = 30 V, ID = 43 A,
VGS = 10 V, RGEN = 6 Ω
47
76
ns
66
106
ns
19
34
ns
170
238
nC
137
192
tf
Fall Time
Qg(TOT)
Total Gate Charge
VGS = 0 V to 10 V
Qg(TOT)
Total Gate Charge
VGS = 0 V to 8 V
Qgs
Gate to Source Charge
Qgd
Gate to Drain “Miller” Charge
VDD = 30 V,
ID = 43 A
nC
71
nC
19
nC
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
©2015 Fairchild Semiconductor Corporation
FDMT80060DC Rev. 1.1
VGS = 0 V, IS = 2.6 A
(Note 2)
0.7
1.1
VGS = 0 V, IS = 43 A
(Note 2)
0.8
1.2
IF = 43 A, di/dt = 100 A/μs
2
V
84
135
ns
89
143
nC
www.fairchildsemi.com
FDMT80060DC N-Channel Dual CoolTM 88 PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted.
RθJC
Thermal Resistance, Junction-to-Case
(Top Source)
1.6
RθJC
Thermal Resistance, Junction-to-Case
(Bottom Drain)
0.8
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
38
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1b)
81
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1c)
26
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1d)
34
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1e)
14
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1f)
16
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1g)
26
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1h)
60
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1i)
15
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1j)
21
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1k)
9
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1l)
11
°C/W
NOTES:
1. RθJA is determined with the device mounted on a FR-4 board using a specified pad of 2 oz copper as shown below. RθCA is determined by the user's board design.
b. 81 °C/W when mounted on
a minimum pad of 2 oz copper
a. 38 °C/W when mounted on
a 1 in2 pad of 2 oz copper
DS
SS
SF
G
DS
DF
SS
SF
G
c. Still air, 20.9x10.4x12.7mm Aluminum Heat Sink, 1 in2 pad of 2 oz copper
d. Still air, 20.9x10.4x12.7mm Aluminum Heat Sink, minimum pad of 2 oz copper
e. Still air, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, 1 in2 pad of 2 oz copper
f. Still air, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, minimum pad of 2 oz copper
g. 200FPM Airflow, No Heat Sink,1 in2 pad of 2 oz copper
h. 200FPM Airflow, No Heat Sink, minimum pad of 2 oz copper
i. 200FPM Airflow, 20.9x10.4x12.7mm Aluminum Heat Sink, 1 in2 pad of 2 oz copper
j. 200FPM Airflow, 20.9x10.4x12.7mm Aluminum Heat Sink, minimum pad of 2 oz copper
k. 200FPM Airflow, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, 1 in2 pad of 2 oz copper
l. 200FPM Airflow, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. EAS of 2400 mJ is based on starting TJ = 25 °C; N-ch: L = 3 mH, IAS = 40 A, VDD = 60 V, VGS = 10 V. 100% test at L = 0.3mH, IAS = 87 A.
4. Pulsed Id please refer to Fig 11 SOA graph for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
©2015 Fairchild Semiconductor Corporation
FDMT80060DC Rev. 1.1
3
www.fairchildsemi.com
FDMT80060DC N-Channel Dual CoolTM 88 PowerTrench® MOSFET
Thermal Characteristics
320
VGS = 8 V
240
VGS = 6.5 V
160
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 6 V
80
VGS = 5.5 V
0
0
1
2
3
4
6
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
VGS = 10 V
VGS = 5.5 V
VGS = 6 V
4
3
VGS = 6.5 V
2
VGS = 8 V
1
0
5
VGS = 10 V
0
80
VDS, DRAIN TO SOURCE VOLTAGE (V)
rDS(on), DRAIN TO
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
-75
-50
IS, REVERSE DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
TJ = 25
80
oC
TJ = -55 oC
0
3
4
5
6
ID = 43 A
3
TJ = 125 oC
2
1
TJ = 25 oC
5
6
7
8
9
320
100
VGS = 0 V
10
TJ = 150 oC
1
TJ = 25 oC
0.1
TJ = -55 oC
0.01
0.001
0.0
7
0.2
0.4
0.6
0.8
1.0
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode
Forward Voltage vs. Source Current
©2015 Fairchild Semiconductor Corporation
FDMT80060DC Rev. 1.1
10
Figure 4. On-Resistance vs. Gate to
Source Voltage
TJ = 150 oC
160
4
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VDS = 5 V
240
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
-25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. Normalized On Resistance
vs. Junction Temperature
320
320
5
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
1.5
240
Figure 2. Normalized On-Resistance
vs. Drain Current and Gate Voltage
ID = 43 A
VGS = 10 V
1.6
160
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
1.7
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
5
4
1.2
www.fairchildsemi.com
FDMT80060DC N-Channel Dual CoolTM 88 PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted.
50000
ID = 43 A
Ciss
VDD = 20 V
8
10000
VDD = 30 V
6
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
10
VDD = 40 V
4
Coss
1000
Crss
100
2
0
f = 1 MHz
VGS = 0 V
0
36
72
108
144
10
0.1
180
1
10
60
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs. Drain
to Source Voltage
320
300
o
100
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
RθJC = 0.8 C/W
TJ = 25 oC
TJ = 100 oC
10
TJ = 125 oC
1
0.1
1
10
100
1000
240
VGS = 10 V
VGS = 8 V
160
80
0
25
10000
50
P(PK), PEAK TRANSIENT POWER (W)
ID, DRAIN CURRENT (A)
150
100000
1000
10 μs
100
100 μs
THIS AREA IS
LIMITED BY rDS(on)
1 ms
SINGLE PULSE
TJ = MAX RATED
RθJC = 0.8 oC/W
TC = 25 oC
0.1
0.1
125
Figure 10. Maximum Continuous Drain
Current vs. Case Temperature
3000
1
100
TC, CASE TEMPERATURE ( C)
Figure 9. Unclamped Inductive
Switching Capability
10
75
o
tAV, TIME IN AVALANCHE (ms)
10 ms
CURVE BENT TO
MEASURED DATA
1
10
DC
100
400
TC = 25 oC
10000
1000
100
10 -5
10
-4
10
-3
10
-2
10
-1
10
1
t, PULSE WIDTH (sec)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
©2015 Fairchild Semiconductor Corporation
FDMT80060DC Rev. 1.1
SINGLE PULSE
RθJC = 0.8 oC/W
Figure 12. Single Pulse Maximum
Power Dissipation
5
www.fairchildsemi.com
FDMT80060DC N-Channel Dual CoolTM 88 PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted.
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
2
1
0.1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
t2
NOTES:
0.01
ZθJC(t) = r(t) x RθJC
RθJC = 0.8 oC/W
Peak TJ = PDM x ZθJC(t) + TC
Duty Cycle, D = t1 / t2
SINGLE PULSE
0.001
-5
10
-4
10
-3
-2
10
10
-1
10
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Case Transient Thermal Response Curve
©2015 Fairchild Semiconductor Corporation
FDMT80060DC Rev. 1.1
6
www.fairchildsemi.com
FDMT80060DC N-Channel Dual CoolTM 88 PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted.
(2X)
0.05 C
8.00±0.10
8
A
5
8
B
8.00
6.90
2.00
5
1.10
KEEP OUT
AREA
5.23
4.24
3.94
PKG
CL
8.00±0.10
9.00
(1.83)
1.55
(2.41)
1
4
PKG
CL
4.03
3.68
0.05 C
1.13
1
(2X)
1.10
(1.56)
(8X)
SEE DETAIL A
(1.00)
5.10
7.10
4
0.48
LAND PATTERN
RECOMMENDATION
0.30
0.20
0.95
0.75
0.10
.05
6.00
2.00
(0.50)
PIN #1
IDENT
1
(0.40)
2
3
4
C A B
C
1.10 8X
0.90
0.70
0.50
1.68
1.48
1.20
(0.91)
2.78
(1.23)
8
(0.60)
7
7.00
6.80
6
5
0.45
0.25
(4X)
5.33
5.13
0.05
0.00
C
SEATING
PLANE
SCALE: 2X
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE IS NOT PRESENTLY REGISTERED
WITH ANY STANDARDS COMMITTEE.
B) DIMENSIONS ARE INCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR PROTRUSIONS.
C) ALL DIMENSIONS ARE IN MILLIMETERS.
D) DRAWING CONFORMS TO ASME Y14.5M-2009.
E) IT IS RECOMMENDED TO HAVE NO TRACES OR
VIAS WITHIN THE KEEP OUR AREA.
F) DRAWING FILENAME: MKT-PQFN08RREV2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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