Ordering
Orderingnumber
number: :ENA1028D
ENA1951
LC87F2G08A
CMOS IC
8K-byte FROM and 256-byte RAM integrated
http://onsemi.com
8-bit 1-chip Microcontroller
Overview
The LC87F2G08A is an 8-bit microcomputer that, integrates on a single chip a number of hardware features such as
8K-byte flash ROM, 256-byte RAM, an On-chip-debugger, a 16-bit timers/counters, two 8-bit timers, a base timer
serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface, an
asynchronous/synchronous SIO interface, a UART interface, a 12-bit/8-bit 8-channel AD converter, a system clock
frequency divider, an internal reset and an interrupt feature.
Features
Package Dimensions
Flash ROM
• 8192 × 8 bits
• Capable of On-board programming with
wide range (2.2 to 5.5V) of voltage source.
• Block-erasable in 128 byte units
• Writable in 2-byte units
unit : mm (typ)
3419
13.0
0.45
1 2
1.0
0.15
0.4
1.9 MAX
(1.0)
0.1 (1.5)
Package Form
• MFP24SJ (300mil): Lead-/Halogen-free type
• SSOP24 (225mil): Lead-free type
• VCT24 (3.5×3.5): Lead-/Halogen-free type (build-to-order)
• MFP24S (300mil): Lead-free type (discontinued)
6.0
RAM
• 256 × 9 bits
8.0
24
SANYO : MFP24SJ(300mil)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.4
D0512HK/O0312HKIM 20120913-S00008 No.A1028-1/29
LC87F2G08A
Package Dimensions
Package Dimensions
unit : mm (typ)
3287
unit : mm (typ)
3322A
(Build-to-order)
TOP VIEW
24
SIDE VIEW
BOTTOM VIEW
(0.125)
3.5
13
(0.13)
6.5
0.5
0.4
3.5
6.4
4.4
(C0.17)
24
12
1
2 1
0.5
0.15
0.22
0.5
(0.5)
SIDE VIEW
(1.3)
0.25
(0.035)
1.5max
0.8
(0.5)
0.1
SANYO : VCT24(3.5X3.5)
SANYO : SSOP24(225mil)
Package Dimensions
unit : mm (typ)
3112B
(Discontinued)
12.5
0.63
7.6
13
5.4
24
1
12
1.0
0.15
0.35
1.7max
0.1
(1.5)
(0.75)
SANYO : MFP24S(300mil)
Minimum Bus Cycle
• 83.3ns (12MHz at VDD=2.7V to 5.5V)
• 100ns (10MHz at VDD=2.2V to 5.5V)
• 250ns (4MHz at VDD=1.8V to 5.5V)
Note: The bus cycle time here refers to the ROM read speed.
Minimum Instruction Cycle Time
• 250ns (12MHz at VDD=2.7V to 5.5V)
• 300ns (10MHz at VDD=2.2V to 5.5V)
• 750ns (4MHz at VDD=1.8V to 5.5V)
No.A1028-2/29
LC87F2G08A
Ports
• Normal withstand voltage I/O ports
Ports I/O direction can be designated in 1-bit units
Ports I/O direction can be designated in 4-bit units
• Dedicated oscillator ports/input ports
• Reset pin
• Power pins
11 (P1n, P20, P21, P70)
8 (P0n)
2 (CF1/XT1, CF2/XT2)
1 (RES)
2 (VSS1, VDD1)
Timers
• Timer 0: 16-bit timer/counter with a capture register.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/
counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM)
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts are programmable in 5 different time schemes
High-Speed Clock Counter
• Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
• Can generate output real time.
SIO
• SIO0: 8-bit Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3tCYC)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
UART
• Full Duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2 bits in continuous data transmission)
• Built-in baudrate generator
AD Converter: 12 bits/8 bits × 8 channels
• 12 bits/8 bits AD converter resolution selectable
Remote Control Receiver Circuit (sharing pins with P15, SCK1, INT3, and T0IN)
• Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
No.A1028-3/29
LC87F2G08A
Clock Output Function
• Can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as
the system clock.
• Can generate the source clock for the subclock
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Interrupts
• 18 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/base timer
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0/UART1 receive
8
0003BH
H or L
SIO1/UART1 transmit
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 128levels (The stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
Oscillation Circuits
• Internal oscillation circuits
Low-speed RC oscillation circuit :
For system clock (100kHz)
Medium-speed RC oscillation circuit : For system clock (1MHz)
Multifrequency RC oscillation circuit : For system clock (8MHz)
• External oscillation circuits
Hi-speed CF oscillation circuit:
For system clock, with internal Rf
Low speed crystal oscillation circuit:
For low-speed system clock, with internal Rf
1) The CF and crystal oscillation circuits share the same pins. The active circuit is selected under program control.
2) Both the CF and crystal oscillator circuits stop operation on a system reset. When the reset is released, only the
CF oscillation circuit resumes operation.
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and
76.8μs (at a main clock rate of 10MHz).
No.A1028-4/29
LC87F2G08A
Internal Reset Function
• Power-on reset (POR) function
1) POR reset is generated only at power-on time.
2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and
4.35V) through option configuration.
• Low-voltage detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a certain level.
2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V,
2.81V, 3.79V, 4.28V).
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer or low-voltage detection
(3) Occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) System resetting by watchdog timer or low-voltage detection
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0.
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level.
(2) System resetting by watchdog timer or low-voltage detection.
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0.
(5) Having an interrupt source established in the base timer circuit.
Note: Available only when X’tal oscillation is selected.
Onchip Debugger
• Supports software debugging with the IC mounted on the target board.
• Two channels of on-chip debugger pins are available to be compatible with small pin count devices.
DBGP0 (P0), DBGP1 (P1)
Data Security Function (flash versions only)
• Protects the program data stored in flash memory from unauthorized read or copy.
Note: This data security function does not necessarily provide absolute data security.
Development Tools
• On-chip debugger: (1) TCB87 type B + LC87D2G08A
(2) TCB87 TypeB + LC87F2G08A
(3) TCB87 TypeC (3 wire version) + LC87D2G08A
(4) TCB87 TypeC (3 wire version) + LC87F2G08A
Note: LC87F2G08A has an On-chip debugger but its function is limited.
No.A1028-5/29
LC87F2G08A
Flash ROM Programming Boards
Package
Programming boards
MFP24S(300mil)
W87F2GM
MFP24SJ(300mil)
W87F2GMJ
SSOP24(225mil)
W87F2GS
VCT24(3.5×3.5)
(build-to-order)
Flash ROM Programmer
Maker
Model
Single
Programmer
Flash Support Group, Inc.
(FSG)
Programmer
AF9709/AF9709B/AF9709C
(Including Ando Electric Co., Ltd. models)
AF9833(Unit)
(Including Ando Electric Co., Ltd. models)
Flash Support Group, Inc.
(FSG)
+
Our company
Rev 02.72 or later
LC87F2H08A
-
-
-
-
(Note 2)
LC87F2G08A
AF9101/AF9103(Main body)
In-circuit
Programmer
(FSG models)
SIB87(Inter Face Driver)
(Our company model)
(Note 1)
Our company
Device
(Including Ando Electric Co., Ltd. models)
AF9723/AF9723B(Main body)
Gang
Supported version
AF9708
Single/Gang
SKK/SKK Type B
Programmer
(SanyoFWS)
1.04 or later
In-circuit/Gang
SKK-DBG Type B
Chip Data Version
Programmer
(SanyoFWS)
2.10 or later
Application Version
LC87F2G08A
For information about AF-Series:
Flash Support Group, Inc.
TEL: +81-53-459-1050
E-mail: sales@j-fsg.co.jp
Note1: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from Our company (SIB87)
together can give a PC-less, standalone on-board-programming capabilities.
Note2: It needs a special programming devices and applications depending on the use of programming environment.
Please ask FSG or Our company for the information.
No.A1028-6/29
LC87F2G08A
Pin Assignment
P70/INT0/T0LCP/AN8
1
24
P07/T7O/DBGP02
RES
2
23
P06/AN6/T6O/DBGP01
VSS1
3
22
P05/AN5/CKO/DBGP00
CF1/XT1
4
21
P04/AN4
CF2/XT2
5
20
P03/AN3
VDD1
6
19
P02/AN2
P10/SO0
7
18
P01/AN1
P11/SI0/SB0
8
17
P00/AN0
P12/SCK0
9
16
P21/URX/INT4/T1IN
P13/SO1/DBGP12
10
15
P20/UTX/INT4/T1IN
P14/SI1/SB1/DBGP11
11
14
P17/T1PWMH/BUZ/INT1/T0HCP
P15/SCK1/INT3/T0IN/DBGP10
12
13
P16/T1PWML/INT2/T0IN
LC87F2G08A
Top view
MFP24S (300mil) “Lead-free Type”
MFP24SJ (300mil) “Lead-/Halogen-free Type”
SSOP24 (225mil) “Lead-free Type”
MFP24S/
MFP24SJ/
MFP24S/
NAME
SSOP24
MFP24SJ/
NAME
SSOP24
1
P70/INT0/T0LCP/AN8
13
P16/T1PWML/INT2/T0IN
2
RES
14
P17/T1PWMH/BUZ/INT1/T0HCP
3
VSS1
15
P20/UTX/INT4/T1IN
4
CF1/XT1
16
P21/URX/INT4/T1IN
5
CF2/XT2
17
P00/AN0
6
VDD1
18
P01/AN1
7
P10/SO0
19
P02/AN2
8
P11/SI0/SB0
20
P03/AN3
9
P12/SCK0
21
P04/AN4
10
P13/SO1/DBGP12
22
P05/AN5/CKO/DBGP00
11
P14/SI1/SB1/DBGP11
23
P06/AN6/T6O/DBGP01
12
P15/SCK1/INT3/T0IN/DBGP10
24
P07/T7O/DBGP02
No.A1028-7/29
13 P20/UTX/INT4/T1IN
14 P21/URX/INT4/T1IN
15 P00/AN0
16 P01/AN1
17 P02/AN2
18 P03/AN3
LC87F2G08A
12 P17/T1PWMH/BUZ/INT1/T0HCP
P04/AN4 19
11 P16/T1PWML/INT2/T0IN
P05/AN5/CKO/DBGP00 20
P06/AN6/T6O/DBGP01 21
10 P15/SCK1/INT3/T0IN/DBGP10
LC87F2G08A
9 P14/SI1/SB1/DBGP11
P07/T7O/DBGP02 22
8 P13/SO1/DBGP12
P70/INT0/T0LCP/AN8 23
RES 24
P11/SI0/SB0 6
P10/SO0 5
VDD1 4
CF2/XT2 3
CF1/XT1 2
VSS1 1
7 P12/SCK0
Top view
VCT24(3.5×3.5) “Lead-/Halogen-free Type” (build-to-order)
VCT24
NAME
VCT24
NAME
1
VSS1
13
P20/UTX/INT4/T1IN
2
CF1/XT1
14
P21/URX/INT4/T1IN
3
CF2/XT2
15
P00/AN0
4
VDD1
16
P01/AN1
5
P10/SO0
17
P02/AN2
6
P11/SI0/SB0
18
P03/AN3
7
P12/SCK0
19
P04/AN4
8
P13/SO1/DBGP12
20
P05/AN5/CKO/DBGP00
9
P14/SI1/SB1/DBGP11
21
P06/AN6/T6O/DBGP01
10
P15/SCK1/INT3/T0IN/DBGP10
22
P07/T7O/DBGP02
11
P16/T1PWML/INT2/T0IN
23
P70/INT0/T0LCP/AN8
12
P17/T1PWMH/BUZ/INT1/T0HCP
24
RES
No.A1028-8/29
LC87F2G08A
System Block Diagram
Interrupt control
IR
PLA
Flash ROM
Standby control
SRC
RC
Clock
generator
CF/
X'tal
PC
MRC
ACC
WDT
Reset circuit
(LVD/POR)
SIO0
Reset control
RES
B register
C register
Bus interface
SIO1
Port 0
Timer 0
Port 1
Timer 1
Port 2
Timer 6
Port 7
Timer 7
ADC
Base timer
INT0 to 2 INT3
(Noise filter)
UART1
Port 2 INT4
ALU
PSW
RAR
RAM
Stack pointer
On-chip debugger
No.A1028-9/29
LC87F2G08A
Pin Description
Pin Name
I/O
Description
Option
VSS1
-
- Power supply pin
No
VDD1
-
+ Power supply pin
No
Port 0
I/O
• 8-bit I/O port
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4-bit units.
• HOLD reset input
• Port 0 interrupt input
• Pin functions
Yes
P05: System clock output
P06: Timer 6 toggle output
P07: Timer 7 toggle output
P00(AN0) to P06(AN6): AD converter input
P05(DBGP00) to P07(DBGP02): On-chip debugger 0 port
Port 1
I/O
• 8-bit I/O port
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input / bus I/O
P15: SIO1 clock I/O / INT3 input (with noise filter) / timer 0 event input / timer 0H capture input
P16: Timer 1PWML output / INT2 input/HOLD reset input/timer 0 event input / timer 0L capture
Yes
input
P17: Timer 1PWMH output / beeper output / INT1 input / HOLD reset input / timer 0H capture
input
P15(DBGP10) to P13(DBGP12): On-chip-debugger 1 port
Interrupt acknowledge type
Port 2
P20 to P21
I/O
Rising &
Rising
Falling
INT1
enable
enable
disable
enable
enable
INT2
enable
enable
enable
disable
disable
INT3
enable
enable
enable
disable
disable
Falling
H level
L level
• 2-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P20: UART transmit
P21: UART receive
P20 to P21: INT4 input / HOLD reset input / timer 1 event input / timer 0L capture input / timer
Yes
0H capture input
Interrupt acknowledge types
INT4
Rising
Falling
enable
enable
Rising &
Falling
enable
H level
L level
disable
disable
Continued on next page.
No.A1028-10/29
LC87F2G08A
Continued from preceding page.
Pin Name
Port 7
I/O
Description
Option
• 1-bit I/O port
I/O
• I/O specifiable in 1-bit units
P70
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P70: INT0 input / HOLD reset input / timer 0L capture input / watchdog timer output
P70(AN8): AD converter input
No
Interrupt acknowledge types
INT0
RES
CF1/XT1
I/O
Rising
Falling
enable
enable
Rising &
Falling
disable
H level
L level
enable
enable
External reset input / internal reset output
No
• Ceramic resonator or 32.768kHz crystal oscillator input pin
I
• Pin function
No
General-purpose input port
CF2/XT2
• Ceramic resonator or 32.768kHz crystal oscillator output pin
I/O
• Pin function
No
General-purpose input port
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
P00 to P07
P10 to P17
P20 to P21
P70
Option selected in
units of
1 bit
1 bit
1 bit
-
Option type
Output type
Pull-up resistor
1
CMOS
Programmable (Note 1)
2
Nch-open drain
No
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
2
Nch-open drain
Programmable
No
Nch-open drain
Programmable
Note 1: The control of the presence or absence of the programmable pull-up resistors for port 0 and the switching
between low-and high-impedance pull-up connection is exercised in nibble (4-bit) units (P00 to 03 or
P04 to 07).
No.A1028-11/29
LC87F2G08A
User Option Table
Option Name
Option to be Applied on
Flash-ROM Version
Option Selected in Units of
P00 to P07
1 bit
CMOS
Option Selection
P10 to P17
1 bit
CMOS
P20 to P21
1 bit
CMOS
-
-
Nch-open drain
Port output type
Nch-open drain
Nch-open drain
Program start
00000h
address
01E00h
Low-voltage
Detect function
-
Enable:Use
detection reset
function
Power-on reset
Disable:Not Used
Detect level
-
Power-On reset level
-
7-level
8-level
function
Recommended Unused Pin Connections
Recommended Unused Pin Connections
Port Name
Board
Software
P00 to P07
Open
Output low
P10 to P17
Open
Output low
P20 to P21
Open
Output low
P70
Open
Output low
CF1/XT1
Pulled low with a 100kΩ resistor or less
General-purpose input port
CF2/XT2
Pulled low with a 100kΩ resistor or less
General-purpose input port
Notes on CF1/XT1 and CF2/XT2 pins
• When using as general-purpose input ports
Since the CF1/XT1 and CF2/XT2 pins are configured as CF oscillator pins at system reset time, it is necessary to
add a current limiting resistor of 1kΩ or greater to the CF2/XT2 pin in series when using them as general-purpose
input pins.
• Differences between flash and mask ROM version
System Reset Time State
After System Reset is Released
CF1/XT1
Set high via the internal Rf resistor
CF oscillation state
CF2/XT2
Set high
CF oscillation state
Mask ROM version
CF1/XT1
Set low via the internal Rf resistor
CF oscillation state
LC872G08A/06A/04A
CF2/XT2
Set low
CF oscillation state
Flash ROM version LC87F2G08A
On-chip Debugger Pin Connection Requirements
For the treatment of the on-chip debugger pins, refer to the separately available documents entitled "RD87 on-chip
debugger installation manual" and "LC872000 series on-chip debugger pin connection requirements"
No.A1028-12/29
LC87F2G08A
Absolute Maximum Ratings at Ta = 25°C, VSS1 =0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Maximum supply
VDD max
VDD1
Input voltage
VI
CF1, CF2
Input/output
VIO
Ports 0, 1, 2,
voltage
voltage
High level output current
Peak output
P70
IOPH
Mean output
CMOS output select
Per 1 applicable pin
IOMH
Ports 0, 1, 2
current
typ
max
-0.3
+6.5
-0.3
VDD+0.3
-0.3
VDD+0.3
unit
V
-10
CMOS output select
Per 1 applicable pin
-7.5
-20
(Note 1-1)
Total output
ΣIOAH(1)
P10 to P14
Total of all applicable pins
current
ΣIOAH(2)
Ports 0, 2
Total of all applicable pins
P15 to P17
Peak output
ΣIOAH(3)
Ports 0, 1, 2
Total of all applicable pins
IOPL(1)
P02 to P07
Per 1 applicable pin
current
Low level output current
Ports 0, 1, 2
current
min
Mean output
-25
20
Ports 1, 2
IOPL(2)
P00, P01
Per 1 applicable pin
30
IOPL(3)
P70
Per 1 applicable pin
10
IOML(1)
P02 to P07
Per 1 applicable pin
IOML(2)
P00, P01
Per 1 applicable pin
20
IOML(3)
P70
Per 1 applicable pin
7.5
50
Total output
ΣIOAL(1)
P10 to P14
Total of all applicable pins
current
ΣIOAL(2)
Port 0, 2,
Total of all applicable pins
60
P15 to P17
Power
ΣIOAL(3)
Ports 0, 1, 2
Total of all applicable pins
70
ΣIOAL(4)
P70
Total of all applicable pins
7.5
Pd max(1)
MFP24S(300mil)
Ta=-40 to +85°C
Dissipation
129
Package only
Pd max(2)
mA
15
Ports 1, 2
current
(Note 1-1)
-20
Ta=-40 to +85°C
Package with thermal
229
resistance board
(Note 1-2)
Pd max(3)
MFP24SJ(300mil)
Ta=-40 to +85°C
171
Package only
Pd max(4)
Ta=-40 to +85°C
mW
Package with thermal
393
resistance board
(Note 1-2)
Pd max(5)
SSOP24(225mil)
Ta=-40 to +85°C
111
Package only
Pd max(6)
Ta=-40 to +85°C
Package with thermal
334
resistance board
(Note 1-2)
Pd max(7)
VCT24(3.5×3.5)
Ta=-40 to +85°C
T.B.D
Package only
Pd max(8)
Ta=-40 to +85°C
Package with thermal
T.B.D
resistance board
Operating ambient
Topr
temperature
Storage ambient
temperature
Tstg
-40
+85
-55
+125
°C
Note 1-1: The mean output current is a mean value measured over 100ms.
Note 1-2: SEMI standards thermal resistance board (size: 76.1×114.3×1.6tmm, glass epoxy) is used.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A1028-13/29
LC87F2G08A
Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
max
unit
2.7
5.5
VDD(2)
0.294μs ≤ tCYC ≤ 200μs
2.2
5.5
VDD(3)
0.735μs ≤ tCYC ≤ 200μs
1.8
5.5
VDD(1)
supply voltage
Memory
typ
0.245μs ≤ tCYC ≤ 200μs
Operating
(Note 2-1)
min
VHD
VDD1
VDD1
sustaining
RAM and register contents sustained
in HOLD mode.
1.6
supply voltage
High level
VIH(1)
input voltage
Ports 1, 2,
P70 port input/
1.8 to 5.5
0.3VDD+0.7
VDD
1.8 to 5.5
0.3VDD+0.7
VDD
1.8 to 5.5
0.9VDD
VDD
interrupt side
VIH(2)
Ports 0
VIH(3)
Port 70 watchdog
timer side
Low level
VIH(4)
CF1, RES
1.8 to 5.5
0.75VDD
VDD
VIL(1)
Ports 1, 2,
4.0 to 5.5
VSS
0.1VDD+0.4
1.8 to 4.0
VSS
0.2VDD
4.0 to 5.5
VSS
0.15VDD+0.4
1.8 to 4.0
VSS
0.2VDD
1.8 to 5.5
VSS
0.8VDD-1.0
input voltage
P70 port input/
interrupt side
VIL(2)
VIL(3)
Ports 0
Port 70 watchdog
timer side
VIL(4)
CF1, RES
1.8 to 5.5
VSS
0.25VDD
Instruction
tCYC
2.7 to 5.5
0.245
200
cycle time
(Note 2-2)
2.2 to 5.5
0.294
200
(Note 2-1)
External
V
FEXCF
CF1
• CF2 pin open
1.8 to 5.5
0.735
200
2.7 to 5.5
0.1
12
1.8 to 5.5
0.1
4
3.0 to 5.5
0.2
24.4
2.0 to 5.5
0.2
8
μs
• System clock frequency division
system clock
frequency
ratio=1/1
• External system clock duty=50±5%
• CF2 pin open
MHz
• System clock frequency division
ratio=1/2
• External system clock duty=50±5%
Oscillation
FmCF(1)
CF1, CF2
frequency
range
12MHz ceramic oscillation.
See Fig. 1.
FmCF(2)
CF1, CF2
(Note 2-3)
10MHz ceramic oscillation.
See Fig. 1.
FmCF(3)
CF1, CF2
2.7 to 5.5
12
2.2 to 5.5
10
1.8 to 5.5
4
4MHz ceramic oscillation.
CF oscillation normal amplifier size selected.
(CFLAMP=0) See Fig. 1.
4MHz ceramic oscillation.
CF oscillation low amplifier size
selected. (CFLAMP=1)
MHz
2.2 to 5.5
4
See Fig. 1.
FmMRC
Frequency variable RC oscillation. 1/2
frequency division ration. (RCCTD=0)
2.7 to 5.5
7.44
8.0
8.56
Internal medium-speed RC oscillation
1.8 to 5.5
0.5
1.0
2.0
Internal low-speed RC oscillation
1.8 to 5.5
50
100
200
(Note 2-4)
FmRC
FmSRC
FsX’tal
XT1, XT2
32.768kHz crystal oscillation
See Fig. 2.
kHz
1.8 to 5.5
32.768
Note 2-1: VDD must be held greater than or equal to 2.2V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
Note 2-4: When switching the system clock, allow an oscillation stabilization time of 100μs or longer after the
multifrequency RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state.
No.A1028-14/29
LC87F2G08A
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
High level input
IIH(1)
current
Ports 0, 1, 2,
Output disabled
P70, RES
Pull-up resistor off
VIN=VDD
(Including output Tr's off leakage
min
typ
max
unit
1.8 to 5.5
1
1.8 to 5.5
15
current)
Low level input
IIH(2)
CF1
VIN=VDD
IIL(1)
Ports 0, 1, 2,
Output disabled
P70, RES
Pull-up resistor off
current
VIN=VSS
(Including output Tr's off leakage
1.8 to 5.5
-1
1.8 to 5.5
-15
μA
current)
IIL(2)
CF1
VIN=VSS
High level output
VOH(1)
Ports 0, 1, 2
IOH=-1mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
IOH=-0.35mA
2.7 to 5.5
VDD-0.4
VOH(3)
IOH=-0.15mA
1.8 to 5.5
VDD-0.4
Low level output
VOL(1)
voltage
VOL(2)
Ports 0, 1, 2
VOL(3)
4.5 to 5.5
1.5
2.7 to 5.5
0.4
IOL=0.8mA
1.8 to 5.5
0.4
IOL=1.4mA
2.7 to 5.5
0.4
IOL=0.8mA
1.8 to 5.5
0.4
IOL=25mA
4.5 to 5.5
1.5
VOL(7)
IOL=4mA
2.7 to 5.5
0.4
VOL(8)
IOL=2mA
1.8 to 5.5
0.4
VOH=0.9VDD
When Port 0 selected
4.5 to 5.5
15
35
80
low-impedance pull-up.
1.8 to 4.5
18
50
230
VOH=0.9VDD
When Port 0 selected
1.8 to 5.5
VOL(4)
P70
VOL(5)
VOL(6)
Pull-up resistance
IOL=10mA
IOL=1.4mA
Rpu(1)
Rpu(2)
Rpu(3)
P00, P01
Ports 0, 1, 2
P70
Port 0
V
kΩ
100
210
400
high-impedance pull-up.
Hysteresis voltage
Pin capacitance
VHYS(1)
Ports 1, 2, P70,
2.7 to 5.5
0.1VDD
VHYS(2)
RES
1.8 to 2.7
0.07VDD
CP
All pins
1.8 to 5.5
10
V
For pins other than that under test:
VIN=VSS
f=1MHz
pF
Ta=25°C
No.A1028-15/29
LC87F2G08A
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Input clock
Symbol
Frequency
tSCK(1)
Low level
tSCKL(1)
Specification
Pin/
Conditions
Remarks
SCK0(P12)
VDD[V]
• See Fig. 5.
tSCK(2)
Low level
tSCKL(2)
tCYC
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 5.
1/2
1.8 to 5.5
tSCK
tSCKH(2)
1/2
Serial input
pulse width
Data setup time
SB0(P11),
SI0(P11)
Data hold time
• Must be specified with
respect to rising edge of
SIOCLK.
thDI(1)
0.05
1.8 to 5.5
0.05
• See Fig. 5.
Input clock
Output delay
tdD0(1)
time
SO0(P10),
SB0(P11)
• Continuous data
(1/3)tCYC
transmission/reception mode
+0.08
(Note 4-1-2)
tdD0(2)
• Synchronous 8-bit mode
tdD0(3)
(Note 4-1-2)
(Note 4-1-2)
Output clock
Serial output
tsDI(1)
unit
1
pulse width
High level
max
1
tSCKH(1)
Frequency
typ
2
1.8 to 5.5
pulse width
High level
min
pulse width
Output clock
Serial clock
Parameter
1tCYC
μs
+0.08
1.8 to 5.5
(1/3)tCYC
+0.08
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 5.
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Input clock
Symbol
Frequency
tSCK(3)
Low level
tSCKL(3)
Specification
Pin/
Conditions
Remarks
SCK1(P15)
VDD[V]
See Fig. 5.
1.8 to 5.5
pulse width
High level
Frequency
SCK1(P15)
• CMOS output selected
tSCKL(4)
2
1/2
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 5.
Data hold time
thDI(2)
0.05
1.8 to 5.5
0.05
Output delay time
Serial output
tsDI(2)
unit
1
1.8 to 5.5
pulse width
High level
max
1
• See Fig. 5.
Low level
typ
tCYC
tSCKH(3)
tSCK(4)
min
2
pulse width
Output clock
Serial clock
Parameter
tdD0(4)
SO1(P13),
SB1(P14)
μs
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the time
to the beginning of output state
1.8 to 5.5
change in open drain output
(1/3)tCYC
+0.08
mode.
• See Fig. 5.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A1028-16/29
LC87F2G08A
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
High/low level
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P17),
• Event inputs for timer 0 or 1 are
INT2(P16),
enabled.
min
typ
1.8 to 5.5
1
1.8 to 5.5
2
max
unit
INT4(P20 to P21)
tPIH(2)
INT3(P15) when noise
• Interrupt source flag can be set.
tPIL(2)
filter time constant is
• Event inputs for timer 0 are
1/1
enabled.
tPIH(3)
INT3(P15) when noise
• Interrupt source flag can be set.
tPIL(3)
filter time constant is
• Event inputs for timer 0 are
1/32
INT3(P15) when noise
• Interrupt source flag can be set.
tPIL(4)
filter time constant is
• Event inputs for timer 0 are
tPIL(5)
RES
1.8 to 5.5
64
1.8 to 5.5
256
1.8 to 5.5
200
nabled.
tPIH(4)
1/128
tCYC
enabled.
• Resetting is enabled.
μs
No.A1028-17/29
LC87F2G08A
AD Converter Characteristics at VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute
ET
AN6(P06)
AN8(P70)
accuracy
(Note 6-1)
• See Conversion time calculation
TCAD
typ
2.4 to 5.5
(Note 6-1)
• Ta=-10 to +50°C
Conversion time
min
formulas. (Note 6-2)
max
unit
12
bit
3.0 to 5.5
±16
2.4 to 3.6
±20
4.0 to 5.5
32
115
3.0 to 5.5
64
115
2.4 to 3.6
410
425
2.4 to 5.5
VSS
VDD
LSB
μs
• See Conversion time calculation
formulas. (Note 6-2)
• Ta=-10 to +50°C
Analog input
VAIN
voltage range
Analog port
IAINH
VAIN=VDD
2.4 to 5.5
input current
IAINL
VAIN=VSS
2.4 to 5.5
V
1
μA
-1
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute
ET
AN6(P06)
Conversion time
max
formulas. (Note 6-2)
unit
8
bit
±1.5
2.4 to 5.5
• See Conversion time calculation
TCAD
typ
2.4 to 5.5
(Note 6-1)
AN8(P70)
accuracy
min
4.0 to 5.5
20
90
3.0 to 5.5
40
90
LSB
μs
• See Conversion time calculation
formulas. (Note 6-2)
2.4 to 3.6
250
265
2.4 to 5.5
VSS
VDD
• Ta=-10 to +50°C
Analog input
VAIN
voltage range
Analog port
IAINH
VAIN=VDD
2.4 to 5.5
input current
IAINL
VAIN=VSS
2.4 to 5.5
1
-1
V
μA
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit
conversion mode.
Conversion time calculation formulas:
12bits AD Converter Mode: TCAD(Conversion time) = ((52/(AD division ratio))+2)×(1/3)×tCYC
8bits AD Converter Mode: TCAD(Conversion time) = ((32/(AD division ratio))+2)×(1/3)×tCYC
External
Operating supply
oscillation
voltage range
(FmCF)
(VDD)
System division ratio
Cycle time
(SYSDIV)
(tCYC)
AD division
AD conversion time
(TCAD)
ratio
(ADDIV)
12bit AD
8bit AD
21.5μs
4.0V to 5.5V
1/1
250ns
1/8
34.8μs
3.0V to 5.5V
1/1
250ns
1/16
69.5μs
42.8μs
4.0V to 5.5V
1/1
300ns
1/8
41.8μs
25.8μs
3.0V to 5.5V
1/1
300ns
1/16
83.4μs
51.4μs
3.0V to 5.5V
1/1
750ns
1/8
104.5μs
64.5μs
2.4V to 3.6V
1/1
750ns
1/32
416.5μs
256.5μs
CF-12MHz
CF-10MHz
CF-4MHz
No.A1028-18/29
LC87F2G08A
Power-on Reset (POR) Characteristics at Ta = -40°C to +85°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Option selected
voltage
POR release
PORRL
voltage
Detection
min
typ
max
• Select from option.
1.67V
1.55
1.67
1.79
(Note 7-1)
1.97V
1.85
1.97
2.09
2.07V
1.95
2.07
2.19
2.37V
2.25
2.37
2.49
2.57V
2.45
2.57
2.69
2.87V
2.75
2.87
2.99
3.86V
3.73
3.86
3.99
4.35V
4.21
4.35
4.49
0.7
0.95
unit
V
• See Fig. 7.
POUKS
(Note 7-2)
voltage
unknown state
Power supply
• Power supply rise
PORIS
rise time
100
time from 0V to 1.6V.
ms
Note7-1: The POR release level can be selected out of 8 levels only when the LVD reset function is disabled.
Note7-2: POR is in an unknown state before transistors start operation.
Low Voltage Detection Reset (LVD) Characteristics at Ta = -40°C to +85°C, VSS1=0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Option selected
voltage
LVD reset voltage
LVDET
(Note 8-2)
• Select from option.
(Note 8-1)
(Note 8-3)
• See Fig. 8.
LVD hysteresys
LVHYS
width
Detection voltage
LVUKS
unknown state
Low voltage
detection
minimum width
min
max
1.91V
1.81
1.91
2.01
2.01V
1.91
2.01
2.11
2.31V
2.21
2.31
2.41
2.51V
2.41
2.51
2.61
2.81V
2.71
2.81
2.91
3.79V
3.69
3.79
3.89
4.28V
4.18
4.28
4.38
1.91V
55
2.01V
55
2.31V
55
2.51V
55
2.81V
60
3.79V
65
4.28V
65
unit
V
mV
• See Fig. 8.
(Note 8-4)
TLVDW
typ
0.7
0.95
V
• LVDET-0.5V
• See Fig. 9.
0.2
ms
(Reply sensitivity)
Note8-1: The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled.
Note8-2: LVD reset voltage specification values do not include hysteresis voltage.
Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large
current flows through port.
Note8-4: LVD is in an unknown state before transistors start operation.
No.A1028-19/29
LC87F2G08A
Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = 0V
Parameter
Normal mode
Symbol
IDDOP(1)
Specification
Pin/
Conditions
Remarks
VDD1
VDD[V]
min
typ
max
unit
• FmCF=12MHz ceramic oscillation mode
consumption
• System clock set to 12MHz side
current
• Internal low speed and medium speed RC
2.7 to 5.5
7.4
13.0
2.7 to 3.6
4.4
8.1
3.0 to 5.5
9.7
16.2
3.0 to 3.6
5.3
8.7
2.2 to 5.5
6.6
11.9
2.2 to 3.6
4.0
7.4
1.8 to 5.5
2.9
6.5
1.8 to 3.6
2.2
4.2
2.2 to 5.5
1.1
2.5
2.2 to 3.6
0.6
1.3
1.8 to 5.5
0.6
1.7
1.8 to 3.6
0.3
0.9
2.7 to 5.5
5.0
9.1
2.7 to 3.6
3.6
5.8
1.8 to 5.5
75
370
1.8 to 3.6
46
192
5.0
75
176
3.3
46
115
2.5
35
85
oscillation stopped.
(Note 9-1)
• Frequency variable RC oscillation stopped.
(Note 9-2)
• 1/1 frequency division ratio
IDDOP(2)
• CF1=24MHz external clock
• System clock set to CF1 side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDOP(3)
• FmCF=10MHz ceramic oscillation mode
• System clock set to 10MHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(4)
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
mA
• 1/1 frequency division ratio
IDDOP(5)
• CF oscillation low amplifier size selected.
(CFLAMP=1)
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/4 frequency division ratio
IDDOP(6)
• FsX’tal=32.768kHz crystal oscillation mode
• Internal low speed RC oscillation stopped.
• System clock set to internal medium speed
RC oscillation.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDOP(7)
• FsX’tal=32.768kHz crystal oscillation mode
• Internal low speed and medium speed RC
oscillation stopped.
• System clock set to 8MHz with
frequency variable RC oscillation
• 1/1 frequency division ratio
IDDOP(8)
• External FsX’tal and FmCF oscillation stopped.
• System clock set to internal low speed RC
oscillation.
• Internal medium speed RC oscillation sopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(9)
• External FsX’tal and FmCF oscillation stopped.
• System clock set to internal low speed RC
μA
oscillation.
• Internal medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• Ta=-10 to +50°C
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note9-2: The consumption current values do not include operational current of LVD function if not specified.
Continued on next page.
No.A1028-20/29
LC87F2G08A
Continued from preceding page.
Parameter
Normal mode
Symbol
IDDOP(10)
Specification
Pin/
Conditions
Remarks
VDD1
VDD[V]
consumption
• System clock set to 32.768kHz side
current
• Internal low speed and medium speed RC
(Note 9-1)
min
typ
max
unit
• FsX’tal=32.768kHz crystal oscillation mode
1.8 to 5.5
38
139
1.8 to 3.6
15
66
5.0
38
101
3.3
15
46
2.5
9.0
28
2.7 to 5.5
3.1
5.6
2.7 to 3.6
1.6
2.9
3.0 to 5.5
4.9
8.6
3.0 to 3.6
2.3
3.8
2.2 to 5.5
2.7
5.3
2.2 to 3.6
1.4
2.6
1.8 to 5.5
1.4
3.5
1.8 to 3.6
0.7
1.3
2.2 to 5.5
0.7
1.8
2.2 to 3.6
0.3
0.7
1.8 to 5.5
0.4
1.1
1.8 to 3.6
0.2
0.5
oscillation stopped.
• Frequency variable RC oscillation stopped.
(Note 9-2)
• 1/2 frequency division ratio
IDDOP(11)
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
μA
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
• Ta=-10 to +50°C
HALT mode
IDDHALT(1)
• HALT mode
consumption
• FmCF=12MHz ceramic oscillation mode
current
• System clock set to 12MHz side
(Note 9-1)
• Internal low speed and medium speed RC
(Note 9-2)
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(2)
• HALT mode
• CF1=24MHz external clock
• System clock set to CF1 side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDHALT(3)
• HALT mode
• FmCF=10MHz ceramic oscillation mode
• System clock set to 10MHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(4)
• HALT mode
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
mA
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(5)
• HALT mode
• CF oscillation low amplifier size selected.
(CFLAMP=1)
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/4 frequency division ratio
IDDHALT(6)
• HALT mode
• FsX’tal=32.768kHz crystal oscillation mode
• Internal low speed RC oscillation stopped.
• System clock set to internal medium speed
RC oscillation
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note9-2: The consumption current values do not include operational current of LVD function if not specified.
Continued on next page.
No.A1028-21/29
LC87F2G08A
Continued from preceding page.
Parameter
HALT mode
Symbol
IDDHALT(7)
Specification
Pin/
Conditions
remarks
VDD1
VDD[V]
consumption
• FsX’tal=32.768kHz crystal oscillation mode
current
• Internal low speed and medium speed RC
(Note 9-1)
min
typ
max
unit
• HALT mode
2.7 to 5.5
1.8
3.5
oscillation stopped.
mA
• System clock set to 8MHz with
(Note 9-2)
frequency variable RC oscillation
2.7 to 3.6
1.1
2.0
1.8 to 5.5
23
260
1.8 to 3.6
13
119
5.0
23
65
3.3
13
35
2.5
9.2
25
1.8 to 5.5
25
112
1.8 to 3.6
8.5
56
5.0
25
69
• 1/1 frequency division ratio
IDDHALT(8)
• HALT mode
• External FsX’tal and FmCF oscillation stopped.
• System clock set to internal low speed RC
oscillation.
• Internal medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(9)
• HALT mode
• External FsX’tal and FmCF oscillation stopped.
• System clock set to internal low speed RC
oscillation.
• Internal medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• Ta=-10 to +50°C
IDDHALT(10)
• HALT mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDHALT(11)
• HALT mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal low speed and medium speed RC
μA
3.3
8.5
29
2.5
4.2
15
HOLD mode
1.8 to 5.5
0.04
30
• CF1=VDD or open (External clock mode)
1.8 to 3.6
0.02
21
HOLD mode
5.0
0.04
2.3
• CF1=VDD or open (External clock mode)
3.3
0.02
1.5
2.5
0.017
1.2
1.8 to 5.5
3.2
35
1.8 to 3.6
2.7
24
HOLD mode
5.0
3.2
6.5
• CF1=VDD or open (External clock mode)
3.3
2.7
4.5
2.5
2.5
4.2
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
• Ta=-10 to +50°C
HOLD mode
IDDHOLD(1)
consumption
current
(Note 9-1)
IDDHOLD(2)
(Note 9-2)
• Ta=-10 to +50°C
IDDHOLD(3)
HOLD mode
• CF1=VDD or open (External clock mode)
• LVD option selected
IDDHOLD(4)
• Ta=-10 to +50°C
• LVD option selected
Timer HOLD
IDDHOLD(5)
mode
consumption
current
(Note 9-1)
(Note 9-2)
IDDHOLD(6)
Timer HOLD mode
1.8 to 5.5
22
106
• FsX’tal=32.768 kHz crystal oscillation mode
1.8 to 3.6
7.5
45
Timer HOLD mode
5.0
22
62
• FsX’tal=32.768kHz crystal oscillation mode
3.3
7.5
23
2.5
2.9
12
• Ta=-10 to +50°C
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note9-2: The consumption current values do not include operational current of LVD function if not specified.
No.A1028-22/29
LC87F2G08A
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Onboard
IDDFW(1)
VDD1
min
typ
max
unit
• Only current of the Flash block.
programming
2.2 to 5.5
5
10
mA
20
30
ms
40
60
µs
current
Programming
tFW(1)
• Erasing time
time
tFW(2)
• Programming time
2.2 to 5.5
UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Transfer rate
UBR
UTX(P20)
1.8 to 5.5
URX(P21)
Data length:
Stop bits :
Parity bits:
min
typ
16/3
max
unit
8192/3
tCYC
7/8/9 bits (LSB first)
1 bit (2-bit in continuous data transmission)
None
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H)
Start bit
Start of
transmission
Stop bit
End of
transmission
Transmit data (LSB first)
UBR
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H)
Start bit
Start of
reception
Stop bit
Receive data (LSB first)
End of
reception
UBR
No.A1028-23/29
LC87F2G08A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
• CF oscillation normal amplifier size selected (CFLAMP=0)
MURATA
Nominal
Frequency
12MHz
Circuit Constant
Type
SMD
SMD
Oscillator Name
CSTCE12M0G52-R0
CSTCE10M0G52-R0
C1
C2
Rf
Operating
Rd
Voltage Range
[V]
Oscillation
Stabilization Time
typ
max
[ms]
[ms]
[pF]
[pF]
[Ω]
[Ω]
(10)
(10)
Open
1.0k
2.7 to 5.5
0.1
0.5
Open
680
2.2 to 3.6
0.1
0.5
Open
1.0k
2.3 to 5.5
0.1
0.5
(10)
Remarks
(10)
10MHz
LEAD
CSTLS10M0G53-B0
(15)
(15)
Open
1.0k
2.5 to 5.5
0.1
0.5
SMD
CSTCE8M00G52-R0
(10)
(10)
Open
1.5k
2.2 to 5.5
0.1
0.5
Open
1.0k
2.2 to 3.6
0.1
0.5
LEAD
CSTLS8M00G53-B0
(15)
(15)
Open
1.5k
2.4 to 5.5
0.1
0.5
8MHz
Internal C1, C2
SMD
CSTCR6M00G53-R0
(15)
(15)
Open
2.2k
2.2 to 5.5
0.1
0.5
LEAD
CSTLS6M00G53-B0
(15)
(15)
Open
2.2k
2.2 to 5.5
0.1
0.5
SMD
CSTCR4M00G53-R0
(15)
(15)
6MHz
4MHz
LEAD
CSTLS4M00G53-B0
(15)
(15)
Open
1.5k
1.8 to 2.7
0.2
0.6
Open
3.3k
1.9 to 5.5
0.2
0.6
Open
3.3k
1.9 to 5.5
0.2
0.6
• CF oscillation low amplifier size selected (CFLAMP=1)
MURATA
Nominal
Frequency
Circuit Constant
Type
Oscillator Name
C1
C2
[pF]
[pF]
CSTCR4M00G53-R0
(15)
(15)
CSTCR4M00G53095-R0
(15)
(15)
SMD
Rf
Rd
Operating
Oscillation
Voltage
Stabilization Time
Range
typ
max
[Ω]
[Ω]
[V]
[ms]
[ms]
Open
1.0k
2.3 to 2.7
0.2
0.6
Open
2.2k
2.5 to 5.5
0.2
0.6
Open
1.0k
2.1 to 2.7
0.2
0.7
Internal
Open
1.0k
2.3 to 2.7
0.2
0.6
C1,C2
Open
2.2k
2.5 to 5.5
0.2
0.6
Open
1.0k
2.1 to 2.7
0.2
0.7
4MHz
CSTLS4M00G53-B0
(15)
(15)
CSTLS4M00G53095-B0
(15)
(15)
LEAD
Remarks
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Figure 3).
No.A1028-24/29
LC87F2G08A
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
EPSON TOYOCOM
Nominal
Frequency
Type
Circuit Constant
Oscillator
Name
Operating
Oscillation
Voltage
Stabilization Time
C1
C2
Rf
Rd
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
9
9
Open
330k
1.8 to 5.5
1.4
4.0
Remarks
Applicable
32.768kHz
SMD
MC-306
CL value =
7.0pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 3).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF2/XT2
CF1/XT1
Rf
Rd
C1
CF/X’tal
C2
Figure 1 CF and XT Oscillator Circuit
0.5VDD
Figure 2 AC Timing Measurement Point
No.A1028-25/29
LC87F2G08A
VDD
Operating VDD
lower limit
0V
Power supply
Reset time
RES
Internal medium speed
RC oscillation
tmsCF/tmsX’tal
CF1, CF2
Operating
mode
Reset
Unpredictable
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset
signal
HOLD reset signal
absent
HOLD reset signal valid
Internal medium speed
RC oscillation or
low speed RC oscillation
tmsCF/tmsX’tal
CF1, CF2
(Note)
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Note: External oscillation circuit is selected.
Figure 3 Oscillation Stabilization Times
No.A1028-26/29
LC87F2G08A
VDD
Note:
External circuits for reset may vary
depending on the usage of POR and LVD.
Please refer to the user’s manual for more
information.
RRES
RES
CRES
Figure 4 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
tSCK
tSCKL
tSCKH
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 5 Serial I/O Output Waveforms
tPIL
tPIH
Figure 6 Pulse Input Timing Signal Waveform
No.A1028-27/29
LC87F2G08A
(a)
POR release voltage
(PORRL)
(b)
VDD
Reset period
100μs or longer
Reset period
Unknown-state
(POUKS)
RES
Figure 7 Waveform observed when only POR is used (LVD not used)
(RESET pin: Pull-up resistor RRES only)
• The POR function generates a reset only when power is turned on starting at the VSS level.
• No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level
as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an
external reset circuit.
• A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on
again after this condition continues for 100μs or longer.
LVD hysteresis width
(LVHYS)
LVD release voltage
(LVDET+LVHYS)
VDD
LVD reset voltage
(LVDET)
Reset period
Reset period
Reset period
Unknown-state
(LVUKS)
RES
Figure 8 Waveform observed when both POR and LVD functions are used
(RESET pin: Pull-up resistor RRES only)
• Resets are generated both when power is turned on and when the power level lowers.
• A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection
level.
No.A1028-28/29
LC87F2G08A
VDD
LVD release voltage
LVD reset voltage
LVDET-0.5V
TLVDW
VSS
Figure 9 Low voltage detection minimum width
(Example of momentary power loss/Voltage variation waveform)
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of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at
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warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for
any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
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PS No.A1028-29/29
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