LC87BK08A

Ordering number : ENA1984 LC87BK08A LC87BK06A LC87BK04A Overview CMOS IC 8K/6K/4K-byte ROM and 256-byte RAM integrated 8-bit 1-chip Microcontroller The SANYO LC87BK08A/06A/04A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 8K/6K/4K-byte ROM, 256-byte RAM, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), two 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, an asynchronous/synchronous SIO interface, a 12-bit/8-bit 8-channel AD converter, a system clock frequency divider, an internal reset and a 15-source 9-vector interrupt feature. Features ROM • 8192 × 8 bits (LC87BK08A) • 6144 × 8 bits (LC87BK06A) • 4096 × 8 bits (LC87BK04A) RAM • 256 × 9 bits Minimum Bus Cycle • 83.3ns (12MHz at VDD=2.7V to 5.5V) Note: The bus cycle time here refers to the ROM read speed. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. Ver.1.02 O1911HKIM 20110929-S00001 No.A1984-1/27 LC87BK08A/06A/04A Minimum Instruction Cycle Time • 250ns (12MHz at VDD=2.7V to 5.5V) Ports • Normal withstand voltage I/O ports Ports I/O direction can be designated in 1-bit units Ports I/O direction can be designated in 4-bit units • Dedicated oscillator ports/input ports • Reset pin • Power pins 12 (P1n, P20, P21, P70, CF2/XT2) 8 (P0n) 1 (CF1/XT1) 1 (RES) 2 (VSS1, VDD1) Timers • Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) • Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/ counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM) • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts are programmable in 5 different time schemes SIO • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) AD Converter: 12 bits/8 bits × 8 channels • 12 bits/8 bits AD converter resolution selectable Remote Control Receiver Circuit (sharing pins with P15, SCK1, INT3, and T0IN) • Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) Clock Output Function • Capable generating clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as the system clock. • Capable generating the source clock for the subclock Watchdog Timer • Capable generating an internal reset on an overflow of a timer running on the low-speed RC oscillator clock or subclock. • Operating mode at standby is selectable from 3 modes (continue counting/stop operation/stop counting with a count value held). No.A1984-2/27 LC87BK08A/06A/04A Interrupts • 15 sources, 9 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4 INT3/base timer T0H T1L/T1H None SIO1 ADC/T6/T7 Port 0 Interrupt Source • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 128levels (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation Circuits • Internal oscillation circuits Low-speed RC oscillation circuit : For system clock (100kHz) Medium-speed RC oscillation circuit : For system clock (1MHz) Frequency variable RC oscillation circuit : For system clock (8MHz) • External oscillation circuits Hi-speed CF oscillation circuit: For system clock, with internal Rf Low speed crystal oscillation circuit: For low-speed system clock, with internal Rf 1) The CF and crystal oscillation circuits share the same pins. The active circuit is selected under program control. 2) Both the CF and crystal oscillator circuits stop operation on a system reset. After reset is released, oscillation is stopped so start the oscillation operation by program. System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs (at a main clock rate of 10MHz). Internal Reset Function • Power-on reset (POR) function 1) POR reset is generated only at power-on time. 2) The POR release level can be selected from 4 levels (2.57V, 2.87V, 3.86V, and 4.35V) through option configuration. • Low-voltage detection reset (LVD) function 1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) The use or disuse of the LVD function and the low voltage threshold level (3 levels: 2.81V, 3.79V, 4.28V) can be selected by optional configuration. No.A1984-3/27 LC87BK08A/06A/04A Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are three ways of resetting the HALT mode. (1) Setting the reset pin to the low level (2) System resetting by watchdog timer or low-voltage detection (3) Occurrence of an interrupt • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, and crystal oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) System resetting by watchdog timer or low-voltage detection (3) Having an interrupt source established at either INT0, INT1, INT2, INT4 * INT0 and INT1 HOLD mode reset is available only when level detection is set. (4) Having an interrupt source established at port 0. • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The RC oscillator automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level. (2) System resetting by watchdog timer or low-voltage detection. (3) Having an interrupt source established at either INT0, INT1, INT2, INT4 * INT0 and INT1 HOLD mode reset is available only when level detection is set. (4) Having an interrupt source established at port 0. (5) Having an interrupt source established in the base timer circuit. Note: Available only when X’tal oscillation is selected. Package Form • MFP24S (300mil) : Lead-/Halogen-free type • SSOP24 (225mil) : Lead-/Halogen-free type • SSOP24 (275mil) : Lead-/Halogen-free type (build-to-order ) • VCT24 (3×3) : Lead-/Halogen-free type (build-to-order ) Development Tools • On-chip-debugger : (1) TCB87 TypeB + LC87FBK08A (2) TCB87 TypeC (3 wire version) + LC87FBK08A Flash ROM Version • LC87FBK08A No.A1984-4/27 LC87BK08A/06A/04A Package Dimensions unit : mm (typ) 3112B 12.5 24 13 Package Dimensions unit : mm (typ) 3287 6.5 24 13 5.4 7.6 4.4 0.63 6.4 1 1.0 (0.75) 0.35 12 0.15 1 0.5 (0.5) 1.7max 12 0.22 0.15 0.1 SANYO : MFP24S(300mil) SANYO : SSOP24(225mil) Package Dimensions unit : mm (typ) 3175C 7.8 24 13 Package Dimensions unit : mm (typ) 3366 TOP VIEW SIDE VIEW BOTTOM VIEW 0.1 (1.3) 1.5max (1.5) 5.6 7.6 (C0.14) 0.5 3.0 1 0.65 (0.33) 0.22 12 0.15 0.4 24 21 0.19 SIDE VIEW (1.3) 1.5max 0.4 0.8 (0.5) (0.035) 0.1 SANYO : VCT24(3.0X3.0) SANYO : SSOP24(275mil) No.A1984-5/27 (0.09) 3.0 0.5 (0.125) LC87BK08A/06A/04A Pin Assignment P70/INT0/T0LCP/AN8 RES VSS1 CF1/XT1 CF2/XT2 VDD1 P10 P11 P12 P13/SO1 P14/SI1/SB1 P15/SCK1/INT3/T0IN 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 P07/T7O P06/AN6/T6O P05/AN5/CKO P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 P21/INT4/T1IN P20/INT4/T1IN P17/T1PWMH/BUZ/INT1/T0HCP P16/T1PWML/INT2/T0IN LC87BK08A LC87BK06A LC87BK04A 20 19 18 17 16 15 14 13 Top view SANYO: MFP24S(300mil)/SSOP24(225mil) “Lead-/Halogen-free Type” SSOP24(275mil) “Lead-/Halogen-free Type” (build-to-order ) MFP24S SSOP24 1 2 3 4 5 6 7 8 9 10 11 12 NAME P70/INT0/T0LCP/AN8 RES VSS1 CF1/XT1 CF2/XT2 VDD1 P10 P11 P12 P13/SO1 P14/SI1/SB1 P15/SCK1/INT3/T0IN MFP24S SSOP24 13 14 15 16 17 18 19 20 21 22 23 24 NAME P16/T1PWML/INT2/T0IN P17/T1PWMH/BUZ/INT1/T0HCP P20/INT4/T1IN P21/INT4/T1IN P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5/CKO P06/AN6/T6O P07/T7O No.A1984-6/27 LC87BK08A/06A/04A 14 P21/INT4/T1IN 13 P20/INT4/T1IN 12 P17/T1PWMH/BUZ/INT1/T0HCP 11 P16/T1PWML/INT2/T0IN 10 P15/SCK1/INT3/T0IN 9 P14/SI1/SB1 8 P13/SO1 7 P12 P11 6 18 P03/AN3 17 P02/AN2 16 P01/AN1 CF2/XT2 3 P04/AN4 19 P05/AN5/CKO 20 P06/AN6/T6O 21 P07/T7O 22 P70/INT0/T0LCP/AN8 23 RES 24 VSS1 1 CF1/XT1 2 VDD1 4 P10 5 LC87BK08A LC87BK06A LC87BK04A 15 P00/AN0 Top view SANYO: VCT24(3×3) “Lead-/Halogen-free Type” (build-to-order ) VCT24 1 2 3 4 5 6 7 8 9 10 11 12 NAME VSS1 CF1/XT1 CF2/XT2 VDD1 P10 P11 P12 P13/SO1 P14/SI1/SB1 P15/SCK1/INT3/T0IN P16/T1PWML/INT2/T0IN P17/T1PWMH/BUZ/INT1/T0HCP VCT24 13 14 15 16 17 18 19 20 21 22 23 24 NAME P20/INT4/T1IN P21/INT4/T1IN P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5/CKO P06/AN6/T6O P07/T7O P70/INT0/T0LCP/AN8 RES No.A1984-7/27 LC87BK08A/06A/04A System Block Diagram Interrupt control IR PLA Standby control ROM CF/ X'tal SRC RC MRC RES Reset control ACC Clock generator PC WDT Reset circuit (LVD/POR) B register C register Bus interface ALU SIO1 Port 0 Timer 0 Port 1 PSW Timer 1 Port 2 RAR Timer 6 Port 7 RAM Timer 7 ADC Stack pointer Base timer INT0 to 2 INT3 (Noise filter) Port 2 INT4 No.A1984-8/27 LC87BK08A/06A/04A Pin Description Pin Name VSS1 VDD1 Port 0 P00 to P07 I/O I/O - Power supply pin + Power supply pin • 8-bit I/O port • I/O specifiable in 4-bit units • Pull-up resistors can be turned on and off in 4-bit units. • HOLD reset input • Port 0 interrupt input • Pin functions P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output P00(AN0) to P06(AN6): AD converter input Port 1 P10 to P17 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P13: SIO1 data output P14: SIO1 data input / bus I/O P15: SIO1 clock I/O / INT3 input (with noise filter) / timer 0 event input / timer 0H capture input P16: Timer 1PWML output / INT2 input/HOLD reset input/timer 0 event input / timer 0L capture input P17: Timer 1PWMH output / beeper output / INT1 input / HOLD reset input / timer 0H capture input Interrupt acknowledge type Rising INT1 INT2 INT3 Port 2 P20 to P21 I/O • 2-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P20 to P21: INT4 input / HOLD reset input / timer 1 event input / timer 0L capture input / timer 0H capture input Interrupt acknowledge types Rising INT4 Port 7 P70 I/O • 1-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P70: INT0 input / HOLD reset input / timer 0L capture input P70(AN8): AD converter input Interrupt acknowledge types Rising INT0 enable Falling enable Rising & Falling disable H level enable L level enable No enable Falling enable Rising & Falling enable H level disable L level disable Yes enable enable enable Falling enable enable enable Rising & Falling disable enable enable H level enable disable disable L level enable disable disable Yes Yes Description Option No No Continued on next page. No.A1984-9/27 LC87BK08A/06A/04A Continued from preceding page. Pin Name RES CF1/XT1 I/O I/O I External reset input / internal reset output • Ceramic resonator or 32.768kHz crystal oscillator input pin • Pin function General-purpose input port CF2/XT2 I/O • Ceramic resonator or 32.768kHz crystal oscillator output pin • Pin function General-purpose I/O port No No Description Option No Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 Option selected in units of 1 bit Option type 1 2 P10 to P17 1 bit 1 2 P20 to P21 1 bit 1 2 P70 CF2/XT2 No No CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain Ceramic resonator/32.768kHz crystal resonator output Nch-open drain (N-channel open drain when set to general-purpose output port) Output type Pull-up resistor Programmable (Note 1) No Programmable Programmable Programmable Programmable Programmable No Note 1: The control of the presence or absence of the programmable pull-up resistors for port 0 and the switching between low-and high-impedance pull-up connection is exercised in nibble (4-bit) units (P00 to 03 or P04 to 07). User Option Table Option Name Port output type Option to be Applied on P00 to P07 Mask version *1 Flash-ROM Version Option Selected in Units of 1 bit CMOS Nch-open drain P10 to P17 1 bit CMOS Nch-open drain P20 to P21 1 bit CMOS Nch-open drain Program start address Low-voltage detection reset function Power-on reset function Detect level Power-On reset level Detect function × *2 00000h 01E00h Enable:Use Disable:Not Used 3-level 4-level Option Selection *1: Mask option selection - No change possible after mask is completed. *2: Program start address of the mask version is 00000h. No.A1984-10/27 LC87BK08A/06A/04A Recommended Unused Pin Connections Recommended Unused Pin Connections Port Name Board P00 to P07 P10 to P17 P20 to P21 P70 CF1/XT1 CF2/XT2 Open Open Open Open Pulled low with a 100kΩ resistor or less Pulled low with a 100kΩ resistor or less Software Output low Output low Output low Output low General-purpose input port General-purpose input port Power Pin Treatment Recommendations (VDD1, VSS1) Connect bypass capacitors that meet the following conditions between the VDD1 and VSS1 pins: • Connect among the VDD1 and VSS1 pins and bypass capacitors C1 and C2 with the shortest possible heavy lead wires, making sure that the impedances between the both pins and the bypass capacitors are as possible (L1=L1’ , L2=L2’). • Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel. The capacitance of C2 should approximately 0.1μF. L2 L1 VSS1 C1 C2 VDD1 L1’ L2’ No.A1984-11/27 LC87BK08A/06A/04A Absolute Maximum Ratings at Ta = 25°C, VSS1 =0V Parameter Maximum supply voltage Input voltage Input/output voltage Peak output High level output current current Mean output current (Note 1-1) Total output current Peak output current Low level output current IOPL(2) IOPL(3) Mean output current (Note 1-1) IOML(2) IOML(3) Total output current Power dissipation Pd max(2) Pd max(1) ΣIOAL(1) IOML(1) IOPL(1) P02 to P07 Ports 1, 2 P00, P01 P70, CF2 P02 to P07 Ports 1, 2 P00, P01 P70, CF2 Ports 0, 1, Ports 2, 7, CF2 MFP24S(300mil) Ta=-40 to +85°C Package only Ta=-40 to +85°C Package with thermal resistance board (Note 1-2) Pd max(3) Pd max(4) SSOP24(225mil) Ta=-40 to +85°C Package only Ta=-40 to +85°C Package with thermal resistance board (Note 1-2) Operating ambient temperature Storage ambient temperature Tstg Topr -40 -55 +85 °C +125 334 111 229 mW Per 1 applicable pin Per 1 applicable pin Total of all applicable pins Per 1 applicable pin Per 1 applicable pin Per 1 applicable pin Per 1 applicable pin ΣIOAH(1) Ports 0, 1, 2 Total of all applicable pins -25 IOMH Ports 0, 1, 2 IOPH VI VIO CF1 Ports 0, 1, 2, P70, CF2, RES Ports 0, 1, 2 CMOS output select Per 1 applicable pin CMOS output select Per 1 applicable pin -7.5 -10 Symbol VDD max Pin/Remarks VDD1 Conditions VDD[V] min -0.3 -0.3 -0.3 Specification typ max +6.5 VDD+0.3 VDD+0.3 V unit 20 30 10 15 20 7.5 70 129 mA Note 1-1: The mean output current is a mean value measured over 100ms. Note 1-2: SEMI standards thermal resistance board (size: 76.1×114.3×1.6tmm, glass epoxy) is used. No.A1984-12/27 LC87BK08A/06A/04A Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = 0V Parameter Operating supply voltage Memory sustaining supply voltage High level input voltage VIH(1) VIH(2) VIH(3) Low level input voltage VIL(2) Ports 0 VIL(1) Ports 1, 2, 7 Ports 0 CF1, CF2, RES Ports 1, 2, 7 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 4.0 to 5.5 2.7 to 4.0 4.0 to 5.5 2.7 to 4.0 VIL(3) High level output current IOH(1) IOH(2) IOH(3) IOH(4) ∑IOH(1) ∑IOH(2) Low level output current IOL(1) IOL(2) IOL(3) IOL(4) IOL(5) ∑IOL(1) ∑IOL(2) ∑IOL(3) ∑IOL(4) ∑IOL(5) Instruction cycle time (Note 2-1) External system clock frequency FEXCF CF1 • CF2 pin open • System clock frequency division ratio=1/1 • External system clock duty=50±5% • CF2 pin open • System clock frequency division ratio=1/2 • External system clock duty=50±5% 3.0 to 5.5 0.2 24.4 2.7 to 5.5 0.1 12 MHz tCYC 2.7 to 5.5 0.245 200 μs Ports 7 Total of all applicable pins Ports 0, 1, 2, CF2 Total of all applicable pins Ports 0 Total of all applicable pins P70, CF2 P00, P01 Per 1 applicable pin Per 1 applicable pin Ports 0, 1, 2 Per 1 applicable pin P05 (System clock output function used) Ports 0, 1, 2 Total of all applicable pins 2.7 to 4.5 4.5 to 5.5 2.7 to 4.5 4.5 to 5.5 2.7 to 4.5 2.7 to 5.5 4.5 to 5.5 2.7 to 4.5 4.5 to 5.5 2.7 to 4.5 4.5 to 5.5 2.7 to 4.5 2.7 to 5.5 -1.4 -25 -8.0 7 1 1 15 2 40 10 70 21 1 mA Per 1 applicable pin CF1, CF2, RES Ports 0, 1, 2 Per 1 applicable pin 2.7 to 5.5 4.5 to 5.5 2.7 to 4.5 4.5 to 5.5 0.3VDD+0.7 0.3VDD+0.7 0.75VDD VSS VSS VSS VSS VSS -1.0 -0.35 -6.0 VDD VDD VDD 0.1VDD+0.4 0.2VDD 0.15VDD+0.4 0.2VDD 0.25VDD V VHD VDD1 RAM and register contents sustained in HOLD mode. 1.6 Symbol VDD Pin/Remarks VDD1 Conditions VDD[V] 0.245μs ≤ tCYC ≤ 200μs min 2.7 Specification typ max 5.5 unit Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Continued on next page. No.A1984-13/27 LC87BK08A/06A/04A Continued from preceding page. Parameter Oscillation frequency range (Note 2-2) FmCF(3) CF1, CF2 FmCF(2) CF1, CF2 Symbol FmCF(1) Pin/Remarks CF1, CF2 Conditions VDD[V] 12MHz ceramic oscillation. See Fig. 1. 10MHz ceramic oscillation. See Fig. 1. 4MHz ceramic oscillation. CF oscillation normal amplifier size selected. (CFLAMP=0) See Fig. 1. 4MHz ceramic oscillation. CF oscillation low amplifier size selected. (CFLAMP=1) See Fig. 1. FmMRC(1) FmMRC(2) Frequency variable RC oscillation. (Note 2-3) Frequency variable RC oscillation. • Ta=-10 to +85°C (Note 2-3) FmRC FmSRC FsX’tal Oscillation stabilization time tmsMRC XT1, XT2 Internal medium-speed RC oscillation Internal low-speed RC oscillation 32.768kHz crystal oscillation See Fig. 1. When Frequency variable RC oscillation state is switched from stopped to enabled. See Fig. 3. 2.7 to 5.5 100 μs 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 0.5 50 1.0 100 32.768 2.0 200 kHz 2.7 to 5.5 7.80 8.0 8.20 2.7 to 5.5 7.76 8.0 8.24 2.7 to 5.5 4 MHz 2.7 to 5.5 4 2.7 to 5.5 2.7 to 5.5 min Specification typ 12 10 max unit Note 2-2: See Tables 1 and 2 for the oscillation constants. Note 2-3: When switching the system clock, allow an oscillation stabilization time of 100μs or longer after the frequency variable RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state. No.A1984-14/27 LC87BK08A/06A/04A Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = 0V Parameter High level input current Symbol IIH(1) Pin/Remarks Ports 0, 1, 2, P70, RES Conditions VDD[V] Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) IIH(2) IIH(3) CF1, CF2 Input port selected VIN=VDD CF1 Reset state VIN=VDD Low level input current IIL(1) Ports 0, 1, 2, P70, RES Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) IIL(2) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) Pull-up resistance Rpu(1) Rpu(2) Rpu(3) Ports 0, 1, 2 P70 Port 0 Ports7, CF2 P00, P01 P05 (System clock output function used) Ports 0, 1, 2 IOH=-1.4mA IOL=7mA IOL=1mA IOL=1mA IOL=15mA IOL=2mA VOH=0.9VDD When Port 0 selected low-impedance pull-up. VOH=0.9VDD When Port 0 selected high-impedance pull-up. Hysteresis voltage Pin capacitance VHYS CP Ports 1, 2, P70, RES All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25°C 2.7 to 5.5 10 pF 2.7 to 5.5 0.1VDD V 2.7 to 5.5 4.5 to 5.5 2.7 to 5.5 2.7 to 5.5 4.5 to 5.5 2.7 to 5.5 4.5 to 5.5 2.7 to 4.5 15 18 35 50 CF1, CF2 Input port selected VIN=VSS Ports 0, 1, 2 IOH=-1mA IOH=-0.35mA IOH=-6mA 2.7 to 5.5 4.5 to 5.5 2.7 to 5.5 4.5 to 5.5 -1 VDD-1 VDD-0.4 VDD-1 VDD-0.4 1.5 0.4 0.4 1.5 0.4 80 150 kΩ V 2.7 to 5.5 -1 2.7 to 5.5 1 μA 2.7 to 5.5 1 min Specification typ max unit 2.7 to 5.5 15 2.7 to 5.5 100 200 300 No.A1984-15/27 LC87BK08A/06A/04A SIO1 Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = 0V (Note 4) Parameter Frequency Input clock Low level pulse width High level pulse width Output clock Frequency Low level pulse width High level pulse width Serial input Data setup time Data hold time Output delay time Serial output tsDI(2) thDI(2) tdD0(4) SO1(P13), SB1(P14) SB1(P14), SI1(P14) • Must be specified with respect to rising edge of SIOCLK. • See Fig. 5. • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig. 5. 2.7 to 5.5 (1/2)tCYC +0.05 μs 2.7 to 5.5 (1/3)tCYC +0.01 0.01 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) • CMOS output selected • See Fig. 5. 2.7 to 5.5 1/2 tSCK 1/2 tSCKH(3) Symbol tSCK(3) tSCKL(3) 2.7 to 5.5 Pin/ Remarks SCK1(P15) Conditions VDD[V] • See Fig. 5. min 2 1 tCYC 1 2 Specification typ max unit Note 4: These specifications are theoretical values. Add margin depending on its use. Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = 0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pin/Remarks INT0(P70), INT1(P17), INT2(P16), INT4(P20 to P21) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) INT3(P15) when noise filter time constant is 1/1 INT3(P15) when noise filter time constant is 1/32 INT3(P15) when noise filter time constant is 1/128 RES • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Resetting is enabled. 2.7 to 5.5 200 μs 2.7 to 5.5 256 2.7 to 5.5 64 2.7 to 5.5 2 tCYC Conditions VDD[V] • Interrupt source flag can be set. • Event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 min Specification typ max unit Serial clock No.A1984-16/27 LC87BK08A/06A/04A AD Converter Characteristics at VSS1 = 0V Parameter Resolution Absolute accuracy Conversion time TCAD Symbol N ET Pin/Remarks AN0(P00) to AN6(P06), AN8(P70) • See Conversion time calculation formulas. (Note 6-2) (Note 6-1) Conditions VDD[V] 2.7 to 5.5 3.0 to 5.5 2.7 to 5.5 4.0 to 5.5 3.0 to 5.5 2.7 to 5.5 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 -1 32 64 134 VSS min Specification typ 12 ±16 ±20 115 115 215 VDD 1 V μA μs max unit bit LSB Parameter Resolution Absolute accuracy Conversion time TCAD Symbol N ET Pin/Remarks AN0(P00) to AN6(P06), AN8(P70) • See Conversion time calculation formulas. (Note 6-2) (Note 6-1) Conditions VDD[V] 2.7 to 5.5 2.7 to 5.5 4.0 to 5.5 3.0 to 5.5 2.7 to 5.5 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 -1 20 40 80 VSS min Specification typ 8 ±1.5 90 90 135 VDD 1 V μA μs max unit bit LSB Conversion time calculation formulas: 12bits AD Converter Mode: TCAD(Conversion time) = ((52/(AD division ratio))+2)×(1/3)×tCYC 8bits AD Converter Mode: TCAD(Conversion time) = ((32/(AD division ratio))+2)×(1/3)×tCYC External oscillation (FmCF) Operating supply voltage range (VDD) 4.0V to 5.5V CF-12MHz 3.0V to 5.5V 2.7V to 5.5V 4.0V to 5.5V CF-8MHz 3.0V to 5.5V 2.7V to 5.5V 3.0V to 5.5V CF-4MHz 2.7V to 5.5V System division ratio (SYSDIV) 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 Cycle time (tCYC) 250ns 250ns 250ns 375ns 375ns 375ns 750ns 750ns AD division ratio (ADDIV) 1/8 1/16 1/32 1/8 1/16 1/32 1/8 1/16 12bit AD 34.8μs 69.5μs 138.8μs 52.25μs 104.25μs 208.25μs 104.5μs 208.5μs AD conversion time (TCAD) 8bit AD 21.5μs 42.8μs 85.5μs 32.25μs 64.25μs 128.25μs 64.5μs 128.5μs Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: • The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode. No.A1984-17/27 LC87BK08A/06A/04A Power-on Reset (POR) Characteristics at Ta = -40°C to +85°C, VSS1 = 0V Specification Parameter POR release voltage Symbol PORRL Pin/Remarks Conditions • Select from option. (Note 7-1) Option selected voltage 2.57V 2.87V 3.86V 4.35V Detection voltage unknown state Power supply rise time PORIS • Power supply rise time from 0V to 1.6V. 100 ms POUKS • See Fig. 7. (Note 7-2) 0.7 0.95 min 2.45 2.75 3.73 4.21 typ 2.57 2.87 3.86 4.35 max 2.69 2.99 3.99 4.49 V unit Note7-1: The POR release level can be selected out of 4 levels only when the LVD reset function is disabled. Note7-2: POR is in an unknown state before transistors start operation. Low Voltage Detection Reset (LVD) Characteristics at Ta = -40°C to +85°C, VSS1=0V Specification Parameter LVD reset voltage (Note 8-2) Symbol LVDET Pin/Remarks Conditions • Select from option. (Note 8-1) (Note 8-3) LVD hysteresys width LVHYS • See Fig. 8. Option selected voltage 2.81V 3.79V 4.28V 2.81V 3.79V 4.28V Detection voltage unknown state Low voltage detection minimum width (Reply sensitivity) TLVDW LVUKS • See Fig. 8. (Note 8-4) • LVDET-0.5V • See Fig. 9. 0.2 ms 0.7 0.95 V min 2.71 3.67 4.15 typ 2.81 3.79 4.28 60 65 65 mV max 2.91 3.91 4.41 V unit Note8-1: The LVD reset level can be selected out of 3 levels only when the LVD reset function is enabled. Note8-2: LVD reset voltage specification values do not include hysteresis voltage. Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. Note8-4: LVD is in an unknown state before transistors start operation. No.A1984-18/27 LC87BK08A/06A/04A Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = 0V Parameter Normal mode consumption current (Note 9-1) (Note 9-2) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD1 Conditions VDD[V] • FmCF=12MHz ceramic oscillation mode • System clock set to 12MHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio • CF1=24MHz external clock • System clock set to CF1 side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio IDDOP(3) • FmCF=10MHz ceramic oscillation mode • System clock set to 10MHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDOP(4) • FmCF=4MHz ceramic oscillation mode • System clock set to 4MHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDOP(5) • CF oscillation low amplifier size selected. (CFLAMP=1) • FmCF=4MHz ceramic oscillation mode • System clock set to 4MHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/4 frequency division ratio IDDOP(6) • FsX’tal=32.768kHz crystal oscillation mode • Internal low speed RC oscillation stopped. • System clock set to internal medium speed RC oscillation. • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio IDDOP(7) • FsX’tal=32.768kHz crystal oscillation mode • Internal low speed and medium speed RC oscillation stopped. • System clock set to 8MHz with frequency variable RC oscillation • 1/1 frequency division ratio IDDOP(8) • External FsX’tal and FmCF oscillation stopped. • System clock set to internal low speed RC oscillation. • Internal medium speed RC oscillation sopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDOP(9) • External FsX’tal and FmCF oscillation stopped. • System clock set to internal low speed RC oscillation. • Internal medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio • Ta=-10 to +50°C 3.3 29 74 5.0 48 124 μA 2.7 to 3.6 29 82 2.7 to 5.5 48 149 2.7 to 3.6 1.8 3.2 2.7 to 5.5 2.8 5.1 2.7 to 3.6 0.21 0.60 2.7 to 5.5 0.40 1.3 2.7 to 3.6 0.38 0.91 2.7 to 5.5 0.84 2.2 2.7 to 3.6 1.1 2.2 mA 2.7 to 5.5 2.0 4.4 2.7 to 3.6 2.3 4.2 2.7 to 5.5 4.1 7.8 3.0 to 3.6 2.9 5.5 3.0 to 5.5 5.0 9.6 2.7 to 3.6 2.4 4.7 2.7 to 5.5 4.8 8.7 min Specification typ max unit Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note9-2: The consumption current values do not include operational current of LVD function if not specified. Continued on next page. No.A1984-19/27 LC87BK08A/06A/04A Continued from preceding page. Parameter Normal mode consumption current (Note 9-1) (Note 9-2) IDDOP(11) Symbol IDDOP(10) Pin/ Remarks VDD1 Conditions VDD[V] • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio • Ta=-10 to +50°C HALT mode consumption current (Note 9-1) (Note 9-2) IDDHALT(1) • HALT mode • FmCF=12MHz ceramic oscillation mode • System clock set to 12MHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDHALT(2) • HALT mode • CF1=24MHz external clock • System clock set to CF1 side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio IDDHALT(3) • HALT mode • FmCF=10MHz ceramic oscillation mode • System clock set to 10MHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDHALT(4) • HALT mode • FmCF=4MHz ceramic oscillation mode • System clock set to 4MHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDHALT(5) • HALT mode • CF oscillation low amplifier size selected. (CFLAMP=1) • FmCF=4MHz ceramic oscillation mode • System clock set to 4MHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/4 frequency division ratio IDDHALT(6) • HALT mode • FsX’tal=32.768kHz crystal oscillation mode • Internal low speed RC oscillation stopped. • System clock set to internal medium speed RC oscillation • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio 2.7 to 3.6 0.19 0.40 2.7 to 5.5 0.29 0.87 2.7 to 3.6 0.27 0.57 2.7 to 5.5 0.6 1.4 2.7 to 3.6 0.4 0.91 2.7 to 5.5 1.0 2.5 mA 2.7 to 3.6 0.89 1.6 2.7 to 5.5 1.6 3.4 3.0 to 3.6 1.2 2.2 3.0 to 5.5 2.0 4.7 2.7 to 3.6 0.99 1.7 2.7 to 5.5 2.0 3.7 3.3 8.2 23 5.0 24 64 μA 2.7 to 3.6 8.2 35 2.7 to 5.5 24 82 min Specification typ max unit Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note9-2: The consumption current values do not include operational current of LVD function if not specified. Continued on next page. No.A1984-20/27 LC87BK08A/06A/04A Continued from preceding page. Parameter HALT mode consumption current (Note 9-1) (Note 9-2) Symbol IDDHALT(7) Pin/ remarks VDD1 • HALT mode • FsX’tal=32.768kHz crystal oscillation mode • Internal low speed and medium speed RC oscillation stopped. • System clock set to 8MHz with frequency variable RC oscillation • 1/1 frequency division ratio IDDHALT(8) • HALT mode • External FsX’tal and FmCF oscillation stopped. • System clock set to internal low speed RC oscillation. • Internal medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDHALT(9) • HALT mode • External FsX’tal and FmCF oscillation stopped. • System clock set to internal low speed RC oscillation. • Internal medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio • Ta=-10 to +50°C IDDHALT(10) • HALT mode • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio IDDHALT(11) • HALT mode • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio • Ta=-10 to +50°C HOLD mode consumption current (Note 9-1) (Note 9-2) IDDHOLD(3) IDDHOLD(2) IDDHOLD(1) HOLD mode • CF1=VDD or open (External clock mode) HOLD mode • CF1=VDD or open (External clock mode) • Ta=-10 to +50°C HOLD mode • CF1=VDD or open (External clock mode) • LVD option selected IDDHOLD(4) HOLD mode • CF1=VDD or open (External clock mode) • Ta=-10 to +50°C • LVD option selected Timer HOLD mode consumption current (Note 9-1) (Note 9-2) IDDHOLD(6) IDDHOLD(5) Timer HOLD mode • FsX’tal=32.768 kHz crystal oscillation mode Timer HOLD mode • FsX’tal=32.768kHz crystal oscillation mode • Ta=-10 to +50°C 2.7 to 5.5 2.7 to 3.6 5.0 3.3 2.7 to 5.5 2.7 to 3.6 5.0 3.3 2.7 to 5.5 2.7 to 3.6 5.0 3.3 0.012 0.008 0.012 0.008 2.0 1.6 2.0 1.6 16 4.2 16 4.2 20 8.0 1.2 0.59 23 10 3.8 2.8 70 25 42 11 3.3 5.6 17 5.0 20 51 μA 2.7 to 3.6 5.6 30 2.7 to 5.5 20 85 3.3 9.0 23 5.0 15 39 2.7 to 3.6 9.0 35 2.7 to 5.5 15 68 2.7 to 3.6 0.66 1.1 2.7 to 5.5 0.92 1.6 mA Conditions VDD[V] min Specification typ max unit Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note9-2: The consumption current values do not include operational current of LVD function if not specified. No.A1984-21/27 LC87BK08A/06A/04A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator • CF oscillation normal amplifier size selected (CFLAMP=0) MURATA Nominal Frequency 12MHz 10MHz Circuit Constant Type Oscillator Name C1 [pF] SMD SMD LEAD 8MHz SMD LEAD 6MHz SMD LEAD 4MHz SMD LEAD CSTCE12M0G52-R0 CSTCE10M0G52-R0 CSTLS10M0G53-B0 CSTCE8M00G52-R0 CSTLS8M00G53-B0 CSTCR6M00G53-R0 CSTLS6M00G53-B0 CSTCR4M00G53-R0 CSTLS4M00G53-B0 (10) (10) (15) (10) (15) (15) (15) (15) (15) C2 [pF] (10) (10) (15) (10) (15) (15) (15) (15) (15) Rf [Ω] Open Open Open Open Open Open Open Open Open Rd [Ω] 680 680 680 1.0k 1.0k 1.5k 1.5k 1.5k 1.5k Operating Voltage Range [V] 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 Oscillation Stabilization Time typ [ms] 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.03 0.02 max [ms] 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.45 0.3 Internal C1, C2 Remarks • CF oscillation low amplifier size selected (CFLAMP=1) MURATA Nominal Frequency 12MHz Circuit Constant Type Oscillator Name C1 [pF] SMD SMD 10MHz LEAD SMD 8MHz LEAD SMD 6MHz LEAD SMD LEAD CSTCE12M0G52-R0 CSTCE10M0G52-R0 CSTLS10M0G53-B0 CSTLS10M0G53095-B0 CSTCE8M00G52-R0 CSTLS8M00G53-B0 CSTLS8M00G53093-B0 CSTCR6M00G53-R0 CSTLS6M00G53-B0 CSTLS6M00G53093-B0 4MHz CSTCR4M00G53-R0 CSTLS4M00G53-B0 (10) (10) (15) (15) (10) (15) (15) (15) (15) (15) (15) (15) C2 [pF] (10) (10) (15) (15) (10) (15) (15) (15) (15) (15) (15) (15) Rf [Ω] Open Open Open Open Open Open Open Open Open Open Open Open Rd [Ω] 470 470 470 470 680 680 680 1.0k 1.0k 1.0k 1.0k 1.0k Operating Voltage Range [V] 3.9 to 5.5 2.9 to 5.5 3.6 to 5.5 2.7 to 5.5 2.7 to 5.5 3.0 to 5.5 2.7 to 5.5 2.7 to 5.5 2.8 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 Oscillation Stabilization Time typ [ms] 0.04 0.03 0.03 0.02 0.03 0.03 0.02 0.03 0.03 0.02 0.04 0.02 max [ms] 0.6 0.45 0.45 0.3 0.45 0.45 0.3 0.45 0.45 0.3 0.6 0.3 Internal C1, C2 Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in follwing cases (see Figure 3). • The time interval that is required for the oscillation to get stabilized after the instruction for starting the mainclock oscillation circuit is executed. • The time interval that is required for the oscillation to get stabilized after the HOLD mode is reset and oscillation is started. • The time interval that is required for the oscillation to get stabilized after the X’tal Hold mode, under the state which the main clock oscillation is enabled, is reset and oscillation is started. No.A1984-22/27 LC87BK08A/06A/04A Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator EPSON TOYOCOM Nominal Frequency Type Oscillator Name C1 [pF] 32.768kHz SMD MC-306 9 Circuit Constant C2 [pF] 9 Rf [Ω] Open Rd [Ω] 330k Operating Voltage Range [V] 2.7 to 5.5 Oscillation Stabilization Time typ [s] 1.4 max [s] 4.0 Applicable CL value = 7.0pF Remarks SEIKO INSTRUMENTS Nominal Frequency Type Oscillator Name C1 [pF] 32.768kHz SMD SSP-T7-F 18 Circuit Constant C2 [pF] 18 Rf [Ω] Open Rd [Ω] 0 Operating Voltage Range [V] 2.7 to 5.5 Oscillation Stabilization Time typ [s] 0.75 max [s] 2.0 Applicable CL value = 12.5pF Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 3). • The time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed. • The time interval that is required for the oscillation to get stabilized after the Hold mode, under the state which the subclock oscillation is enabled, is reset and oscillation is started. (Notes on the implementation of the oscillator circuit) • Oscillation is influenced by the circuit pattern layout of printed circuit board. Place the oscillation-related components as close to the CPU chip and to each other as possible with the shortest possible pattern length. • Keep the signal lines whose state changes suddenly or in which large current flows as far away from the oscillator circuit as possible and make sure that they do not cross one another. • Be sure to insert a current limiting resistor (Rd) so that the oscillation amplitude never exceeds the input voltage level that is specified as the absolute maximum rating. • The oscillator circuit constants shown above are sample characteristic values that are measured using the SANYOdesignated oscillation evaluation board. Since the accuracy of the oscillation frequency and other characteristics vary according to the board on which the IC is installed, it is recommended that the user consult the resonator vendor for oscillation evaluation of the IC on a user's production board when using the IC for applications that require high oscillation accuracy. For further information, contact your resonator vendor or SANYO Semiconductor sales representative serving your locality. • It must be noted, when replacing the flash ROM version of a microcontroller with a mask ROM version, that their operating voltage ranges may differ even when the oscillation constant of the external oscillator is the same. CF1/XT1 Rf CF2/XT2 Rd C1 CF/X’tal C2 0.5VDD Figure 1 CF and XT Oscillator Circuit Figure 2 AC Timing Measurement Point No.A1984-23/27 LC87BK08A/06A/04A VDD Operating VDD lower limit 0V Reset time RES Power supply Internal medium speed RC oscillation tmsCF/tmsXtal CF1/XT1 CF2/XT2 tmsMRC Frequency variable RC oscillation Instruction for enabling oscillation executed Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal absent HOLD reset signal valid HALT reset signal valid Internal medium speed RC oscillation or low speed RC oscillation tmsCF/tmsXtal CF1/XT1, CF2/XT2 (Note) tmsMRC Frequency variable RC oscillation Instruction for enabling oscillation executed State HOLD HALT Instruction execution HOLD Reset Signal and Oscillation Stabilization Time Note: External oscillation circuit is selected. Figure 3 Oscillation Stabilization Times No.A1984-24/27 LC87BK08A/06A/04A VDD RRES RES CRES Note: External circuits for reset may vary depending on the usage of POR and LVD. Please refer to the user’s manual for more information. Figure 4 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKH Figure 5 Serial I/O Output Waveforms tPIL tPIH Figure 6 Pulse Input Timing Signal Waveform No.A1984-25/27 LC87BK08A/06A/04A POR release voltage (PORRL) (a) (b) VDD Reset period Unknown-state (POUKS) RES 100μs or longer Reset period Figure 7 Waveform observed when only POR is used (LVD not used) (RESET pin: Pull-up resistor RRES only) • The POR function generates a reset only when power is turned on starting at the VSS level. • No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an external reset circuit. • A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on again after this condition continues for 100μs or longer. LVD hysteresis width (LVHYS) LVD release voltage (LVDET+LVHYS) VDD LVD reset voltage (LVDET) Reset period Unknown-state (LVUKS) RES Reset period Reset period Figure 8 Waveform observed when both POR and LVD functions are used (RESET pin: Pull-up resistor RRES only) • Resets are generated both when power is turned on and when the power level lowers. • A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection level. No.A1984-26/27 LC87BK08A/06A/04A VDD LVD release voltage LVD reset voltage TLVDW LVDET-0.5V VSS Figure 9 Low voltage detection minimum width (Example of momentary power loss/Voltage variation waveform) SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of September, 2011. Specifications and information herein are subject to change without notice. PS No.A1984-27/27