DATA SHEET
www.onsemi.com
Low Offset Voltage
Dual Comparators
8
LM393, LM393E, LM293,
LM2903, LM2903E, LM2903V,
NCV2903
The LM393 series are dual independent precision voltage
comparators capable of single or split supply operation. These devices
are designed to permit a common mode range−to−ground level with
single supply operation. Input offset voltage specifications as low as
2.0 mV make this device an excellent selection for many applications
in consumer, automotive, and industrial electronics.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Wide Single−Supply Range: 2.0 Vdc to 36 Vdc
Split−Supply Range: ±1.0 Vdc to ±18 Vdc
Very Low Current Drain Independent of Supply Voltage: 0.4 mA
Low Input Bias Current: 25 nA
Low Input Offset Current: 5.0 nA
Low Input Offset Voltage: 5.0 mV (max) LM293/393
Input Common Mode Range to Ground Level
Differential Input Voltage Range Equal to Power Supply Voltage
Output Voltage Compatible with DTL, ECL, TTL, MOS, and CMOS
Logic Levels
ESD Clamps on the Inputs Increase the Ruggedness of the Device
without Affecting Performance
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
© Semiconductor Components Industries, LLC, 2016
August, 2021 − Rev. 33
PDIP−8
N SUFFIX
CASE 626
1
1
SOIC−8
D SUFFIX
CASE 751
8
1
8
Micro8E
DM SUFFIX
CASE 846A
1
PIN CONNECTIONS
Output A
Inputs A
GND
1
8
2
7
4
−
+ 5
−
+
3
VCC
Output B
6
Inputs B
(Top View)
DEVICE MARKING AND ORDERING
INFORMATION
See detailed marking information and ordering and shipping
information on page 7 of this data sheet.
Publication Order Number:
LM393/D
LM393, LM393E, LM293, LM2903, LM2903E, LM2903V, NCV2903
VCC
+ Input
- Input
Output
R2
2.1 k
Q3
Q4
R4
Q5
Q6
Q14
2.0 k
F1
Q10
Q1
Q8
Q9
Q16
Q12
Q2
R1
4.6 k
Q15
Q11
Figure 1. Representative Schematic Diagram
(Diagram shown is for 1 comparator)
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2
LM393, LM393E, LM293, LM2903, LM2903E, LM2903V, NCV2903
MAXIMUM RATINGS
Symbol
Value
Unit
Power Supply Voltage
Rating
VCC
+36 or ±18
V
Input Differential Voltage
VIDR
36
V
Input Common Mode Voltage Range
VICR
−0.3 to +36
V
Output Voltage
VO
36
V
Output Short Circuit−to−Ground
Output Sink Current (Note 1)
ISC
ISink
Continuous
20
mA
Power Dissipation @ TA = 25°C
Derate above 25°C
PD
1/RJA
570
5.7
mW
mW/°C
Operating Ambient Temperature Range
LM293
LM393, LM393E
LM2903, LM2903E
LM2903V, NCV2903 (Note 2)
TA
°C
−25 to +85
0 to +70
−40 to +105
−40 to +125
Maximum Operating Junction Temperature
LM393, LM393E, LM2903, LM2903E, LM2903V
LM293, NCV2903
TJ(max)
Storage Temperature Range
Tstg
150
150
−65 to +150
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The maximum output current may be as high as 20 mA, independent of the magnitude of VCC, output short circuits to VCC can cause
excessive heating and eventual destruction.
2. NCV2903 is qualified for automotive use.
ESD RATINGS
Rating
ESD Protection at any Pin (Human Body Model − HBM, Machine Model − MM)
NCV2903 (Note 2)
LM393E, LM2903E
LM393DG/DR2G, LM2903DG/DR2G
All Other Devices
www.onsemi.com
3
HBM
MM
Unit
2000
1500
250
1500
200
150
100
150
V
V
V
V
LM393, LM393E, LM293, LM2903, LM2903E, LM2903V, NCV2903
ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, Tlow ≤ TA ≤ Thigh, unless otherwise noted.)
LM2903/E/V,
NCV2903
LM293, LM393, LM393E
Characteristic
Symbol
Input Offset Voltage (Note 4)
TA = 25°C
Tlow ≤ TA ≤ Thigh
VIO
Input Offset Current
TA = 25°C
Tlow ≤ TA ≤ Thigh
IIO
Input Bias Current (Note 5)
TA = 25°C
Tlow ≤ TA ≤ Thigh
IIB
Min
Typ
Max
Min
Typ
Max
−
−
±1.0
−
±5.0
±9.0
−
−
±2.0
±9.0
±7.0
±15
−
−
±5.0
−
±50
±150
−
−
±5.0
±50
±50
±200
−
−
20
−
250
400
−
−
20
20
250
500
0
0
−
−
VCC −1.5
VCC −2.0
0
0
−
−
VCC −1.5
VCC −2.0
Unit
mV
nA
nA
Input Common Mode Voltage Range (Note 6)
TA = 25°C
Tlow ≤ TA ≤ Thigh
VICR
V
Voltage Gain
RL ≥ 15 k, VCC = 15 Vdc, TA = 25°C
AVOL
50
200
−
25
200
−
V/mV
Large Signal Response Time
Vin = TTL Logic Swing, Vref = 1.4 Vdc
VRL = 5.0 Vdc, RL = 5.1 k, TA = 25°C
−
−
300
−
−
300
−
ns
Response Time (Note 7)
VRL = 5.0 Vdc, RL = 5.1 k, TA = 25°C
tTLH
−
1.3
−
−
1.5
−
s
Input Differential Voltage (Note 8)
All Vin ≥ GND or V− Supply (if used)
VID
−
−
VCC
−
−
VCC
V
Output Sink Current
Vin ≥ 1.0 Vdc, Vin+ = 0 Vdc, VO ≤ 1.5 Vdc TA = 25°C
ISink
6.0
16
−
6.0
16
−
mA
Output Saturation Voltage
Vin ≥ 1.0 Vdc, Vin+ = 0, ISink ≤ 4.0 mA, TA = 25°C
Tlow ≤ TA ≤ Thigh
VOL
−
−
150
−
400
700
−
−
−
200
400
700
Output Leakage Current
Vin− = 0 V, Vin+ ≥ 1.0 Vdc, VO = 5.0 Vdc, TA = 25°C
Vin− = 0 V, Vin+ ≥ 1.0 Vdc, VO = 30 Vdc,
Tlow ≤ TA ≤ Thigh
IOL
−
0.1
−
−
0.1
−
−
−
1000
−
−
1000
Supply Current
RL = ∞ Both Comparators, TA = 25°C
RL = ∞ Both Comparators, VCC = 30 V
ICC
−
−
0.4
−
1.0
2.5
−
−
0.4
−
1.0
2.5
mV
nA
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
LM293 Tlow = −25°C, Thigh = +85°C
LM393, LM393E Tlow = 0°C, Thigh = +70°C
LM2903, LM2903E Tlow = −40°C, Thigh = +105°C
LM2903V & NCV2903 Tlow = −40°C, Thigh = +125°C
NCV2903 is qualified for automotive use.
3. The maximum output current may be as high as 20 mA, independent of the magnitude of VCC, output short circuits to VCC can cause
excessive heating and eventual destruction.
4. At output switch point, VO]1.4 Vdc, RS = 0 with VCC from 5.0 Vdc to 30 Vdc, and over the full input common mode range
(0 V to VCC = −1.5 V).
5. Due to the PNP transistor inputs, bias current will flow out of the inputs. This current is essentially constant, independent of the output state,
therefore, no loading changes will exist on the input lines.
6. Input common mode of either input should not be permitted to go more than 0.3 V negative of ground or minus supply. The upper limit of
common mode range is VCC −1.5 V.
7. Response time is specified with a 100 mV step and 5.0 mV of overdrive. With larger magnitudes of overdrive faster response times are
obtainable.
8. The comparator will exhibit proper output state if one of the inputs becomes greater than VCC, the other input must remain within the common
mode range. The low input state must not be less than −0.3 V of ground or minus supply.
www.onsemi.com
4
LM393, LM393E, LM293, LM2903, LM2903E, LM2903V, NCV2903
LM293/393
14
TA = 0°C
23
TA = +25°C
21
19
TA = +125°C
17
TA = +105°C
TA = +85°C
15
TA = 0°C
TA = -40°C
IIB , INPUT BIAS CURRENT (nA)
IIB , INPUT BIAS CURRENT (nA)
25
LM2903
TA = +70°C
12
TA = +25°C
TA = +70°C
11
10
TA = +125°C
9
TA = +105°C
8
TA = +85°C
7
13
0
5
10
15
20
25
30
VCC, SUPPLY VOLTAGE (Vdc)
35
0
40
Figure 2. Input Bias Current versus
Power Supply Voltage
10
TA = +125°C
TA = +25° C
TA = -55° C
0.01
0.001
0.01
0.1
10
15
20
25
VCC, SUPPLY VOLTAGE (Vdc)
10
Out of
Saturation
1.0
0.1
5
1.0
30
10
1.0
TA = +85° C
0.1
TA = +25° C
0.01
TA = 0° C
TA = -40° C
0.001
0.01
100
0.1
1.0
10
ISink, OUTPUT SINK CURRENT (mA)
Figure 4. Output Saturation Voltage
versus Output Sink Current
Figure 5. Output Saturation Voltage
versus Output Sink Current
TA = -55° C
ICC , SUPPLY CURRENT (mA)
ICC , SUPPLY CURRENT (mA)
100
ISink, OUTPUT SINK CURRENT (mA)
TA = 0° C
0.8
TA = +25° C
0.6
TA = +70° C
0.4
TA = +125°C
0.2
RL = R
5.0
10
15
20
25
30
40
Out of
Saturation
1.0
0
35
Figure 3. Input Bias Current versus
Power Supply Voltage
VOL , SATURATION VOLTAGE (Vdc)
VOL , SATURATION VOLTAGE (Vdc)
TA = -40°C
13
TA = -40° C
1.2
TA = 0° C
1.0
TA = +25° C
0.8
TA = +85° C
0.6
RL = R
0.4
35
0
40
VCC, SUPPLY VOLTAGE (Vdc)
5.0
10
15
20
25
30
35
VCC, SUPPLY VOLTAGE (Vdc)
Figure 6. Power Supply Current versus
Power Supply Voltage
Figure 7. Power Supply Current versus
Power Supply Voltage
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5
40
LM393, LM393E, LM293, LM2903, LM2903E, LM2903V, NCV2903
APPLICATIONS INFORMATION
The addition of positive feedback (< 10 mV) is also
recommended. It is good design practice to ground all
unused pins.
Differential input voltages may be larger than supply
voltage without damaging the comparator’s inputs. Voltages
more negative than −0.3 V should not be used.
These dual comparators feature high gain, wide
bandwidth characteristics. This gives the device oscillation
tendencies if the outputs are capacitively coupled to the
inputs via stray capacitance. This oscillation manifests
itself during output transitions (VOL to VOH). To alleviate
this situation, input resistors < 10 k should be used.
+15 V
Vin
R1
8.2 k
R4
220 k
R1
D1
6.8 k
R2
R5
220 k
*
LM393
+VCC
)
10 k
*
15 k
R3
10 m
LM393
Vin
VCC
)
D1 prevents input from going negative by more than 0.6 V.
R3 ≤
R1 + R2 = R3
R5
for small error in zero crossing.
10
Vin(min) [ 0.4 V peak for 1% phase distortion ().
Figure 9. Zero Crossing Detector
(Split Supply)
51 k
VCC
R
+
LM393
VC
-
RL
10 k
0.001 F LM393
51 k
t
VCC
-
- VEE
VCC
1.0 m
VO
-VEE
Figure 8. Zero Crossing Detector
(Single Supply)
VCC
Vin(min)
Vin
10 k
RL
C
LM393
+
VO
VO
+ Vref
+
51 k
``ON'' for t tO + t
where:
Vref
)
t = RC ȏ n (
VCC
VCC
VO
Vin
VO
0
VC
0
tO
0
t
VCC
RS = R1 | | R2
RL
-
Vth1 = Vref +
LM393
+
Vref
Vref
ȏ
Figure 11. Time Delay Generator
Figure 10. Free−Running Square−Wave Oscillator
RS
Vref
0
Vth2 = Vref -
R1
R2
Figure 12. Comparator with Hysteresis
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6
(VCC -Vref) R1
R1 + R2 + RL
(Vref -VO Low) R1
R1 + R2
t
LM393, LM393E, LM293, LM2903, LM2903E, LM2903V, NCV2903
MARKING DIAGRAMS
PDIP−8
CASE 626
8
8
8
LM393NG
AWL
YYWW
1
Micro8
CASE 846A
8
x93
AYW G
G
LM2903N
AWL
YYWWG
1
1
8
2903
AYW G
G
1
SOIC−8
CASE 751
8
8
1
1
*
2903V
ALYW
G
1
8
8
2903E
ALYW
G
393E
ALYW
G
1
8
2903
ALYW
G
LMx93
ALYW
G
1
x
A
WL, L
YY, Y
WW, W
G, G
= 2 or 3
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This marking diagram also applies to NCV2903DR2G
www.onsemi.com
7
903V
AYW G
G
1
LM393, LM393E, LM293, LM2903, LM2903E, LM2903V, NCV2903
ORDERING INFORMATION
Device
Operating Temperature
Range
LM293DG
LM293DR2G
−25°C to +85°C
Package
Shipping†
SOIC−8
(Pb−Free)
98 Units / Rail
LM293DMR2G
Micro8
(Pb−Free)
LM393DG
SOIC−8
(Pb−Free)
LM393DR2G
LM393EDR2G
2500 / Tape & Reel
4000 / Tape and Reel
98 Units / Rail
2500 / Tape & Reel
SOIC−8
(Pb−Free)
2500 / Tape & Reel
LM393NG
PDIP−8
(Pb−Free)
50 Units / Rail
LM393DMR2G
Micro8
(Pb−Free)
4000 / Tape and Reel
LM2903DG
SOIC−8
(Pb−Free)
0°C to +70°C
LM2903DR2G
LM2903EDR2G
98 Units / Rail
2500 / Tape & Reel
SOIC−8
(Pb−Free)
2500 / Tape & Reel
LM2903DMR2G
Micro8
(Pb−Free)
4000 / Tape and Reel
LM2903NG
PDIP−8
(Pb−Free)
50 Units / Rail
LM2903VDG
SOIC−8
(Pb−Free)
−40°C to +105°C
LM2903VDR2G
LM2903VNG
98 Units / Rail
2500 / Tape & Reel
PDIP−8
(Pb−Free)
50 Units / Rail
NCV2903DR2G*
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCV2903DMR2G*
Micro8
(Pb−Free)
4000 / Tape & Reel
−40°C to +125°C
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
8
XXXX
AYWG
G
1
XXXX
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14087C
MICRO8
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
N-SOURCE
N-GATE
P-SOURCE
P-GATE
P-DRAIN
P-DRAIN
N-DRAIN
N-DRAIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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