Ordering number : ENA1271
LV8105W
Bi-CMOS IC
Three-Phase Brushless Motor Predriver
for Variable Speed Control
http://onsemi.com
Overview
The LV8105W is a predriver IC designed for variable speed control of 3-phase brushless motors. It can be used to
implement a high- and low-side output n-channel power FET drive circuit using a built-in charge pump circuit.
High-efficiency drive is possible through the use of low noise PWM drive and synchronous rectifying systems.
Functions
Speed discriminator and PLL speed control system
Built-in VCO circuit for generating the speed discriminator reference signal
Speed lock detection output
Hall bias switch
Braking circuit (short braking)
Full complement of on-chip protection circuits, including current limiter and lock protection circuits.
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
VCC max
VCC = VG
42
V
Charge pump output voltage
VG max
VG pin
42
V
Output current
IO max1
Pins UL, VL, WL
-15 to 15
mA
IO max2
Pins UH, VH, WH, UOUT, VOUT and WOUT
-20 to 20
mA
Pd max1
Independent IC
0.45
W
Pd max2
Mounted on the specified board *
1.30
W
Allowable power dissipation
Operating temperature
Topr
-20 to +80
C
Storage temperature
Tstg
-55 to +150
C
* Specified board:114.3mm × 76.1mm × 1.6mm, glass epoxy board.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
SQFP48(7X7)
ORDERING INFORMATION
See detailed ordering and shipping information on page 21 of this data sheet.
Semiconductor Components Industries, LLC, 2013
July, 2013
82008MSPC 20080710-S00008 No.A1271-1/21
LV8105W
Allowable Operating range at Ta = 25C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage range
VCC
16 to 28
V
5V constant voltage output current
IREG
0 to -10
mA
HB pin output current
IHB
0 to -25
mA
LD pin applied voltage
VLD
ILD
0 to 6
V
0 to 5
mA
VFGS
IFGS
0 to 6
V
0 to 5
mA
LD pin output current
FGS pin applied voltage
FGS pin output current
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Electrical Characteristics at Ta 25C, VCC = 24V
Parameter
Symbol
Supply current 1
ICC1
Supply current 2
ICC2
Conditions
Ratings
min
typ
At stop
Unit
max
7
8.8
mA
3
3.8
mA
5.6
6.0
V
10
50
mV
10
50
mV
5V Constant-voltage Output (VREG pin)
Output voltage
VREG
Line regulation
V (REG1)
Load regulation
V (REG2)
IO = 5mA
VCC = 16 to 28V
IO = -5 to -10mA
5.2
Output block / Conditions : apply a VG voltage of 33V
High level output voltage 1
VOH1
Pins UL, VL and WL
VREG-0.65
VREG-0.5
VREG-0.35
V
Low level output voltage 1
VOL1
VOH2
Pins UL, VL and WL
0.35
0.5
0.65
V
VG-0.65
VG-0.5
VG-0.35
V
0.45
0.6
0.8
V
51
64
77
kHz
1.65
2.05
2.45
MHz
VCC+8.0
VCC+9.0
VCC+10.0
V
VCC-1.35
0.5
VCC-1.0
VCC-0.7
0.8
V
0.65
102
128
154
-2
-0.1
High level output voltage 2
Low level output voltage 2
PWM frequency
VOL2
f (PWM)
IOH = -2mA
IOL = 2mA
Pins UH, VH and WH IOH = -2mA
Pins UH, VH and WH
IOL = 2mA
Internal Oscillator
Oscillation frequency
f (REF)
Charge Pump Output (VG pin)
Output voltage
VGOUT
CP1 pin
High level output voltage
VOH (CP1)
ICP1 = -2mA
Low level output voltage
VOL (CP1)
f (CP1)
ICP1 = 2mA
Charge pump frequency
V
kHz
Hall Amplifier
Input bias current
IHB (HA)
Common-mode input voltage range 1
VICM1
When using Hall elements
Common-mode input voltage range 2
VICM2
At one-side input bias (Hall IC application)
Hall input sensitivity
SIN wave
Input voltage Low High
VIN (HA)
VSLH
Input voltage High Low
VSHL
Hysteresis width
A
0.3
3.5
V
0
VREG
V
50
mVp-p
5
13
24
mV
2
7
12
mV
-12
-6
-2
mV
VCC-0.8
-10
VCC-0.5
VCC-0.35
HB pin
Output voltage
VHBO
IHB = -15mA
Output leakage current
IL (HB)
VO = 0V
V
A
FG Amplifier
Input offset voltage
VIO (FG)
IB (FG)
-10
10
mV
Input bias current
-1
1
A
Reference voltage
VB (FG)
-5%
VREG/2
5%
V
High level output voltage
VOH (FG)
IFGI = -0.1mA, No load
3.95
4.4
4.85
V
Low level output voltage
VOL (FG)
IFGI = 0.1mA, No load
0.75
1.2
1.65
FG input sensitivity
GAIN : 100 times
Schmitt width of the next stage
One-side hysteresis comparator
3
120
200
Operation frequency range
Open-loop gain
fFG = 2kHz
45
V
mV
48
280
mV
3
kHz
dB
Continued on next page.
No.A1271-2/21
LV8105W
Continued from preceding page.
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
FGS output
Output saturation voltage
VOL (FGS)
IFGS = 2mA
Output leakage current
IL (FGS)
VO = 6V
0.2
0.4
V
10
A
3.9
V
CSD oscillator
High level output voltage
VOH (CSD)
Low level output voltage
VOL (CSD)
Amplitude
V (CSD)
External capacitor charge current
ICHG1
External capacitor discharge current
ICHG2
Oscillation frequency
f (CSD)
2.9
3.4
1.6
2.0
2.4
V
1.15
1.4
1.65
Vp-p
-13
-10
-7
A
7.5
10.5
13.5
A
C = 0.047F
78
Hz
Speed Discriminator output
High level output voltage 1
VOH1 (D)
VREG-1.25
VREG-1.0
VREG-0.75
V
V
Low level output voltage 1
VOL1 (D)
0.65
0.9
1.15
High level output voltage 2
VOH2 (D)
VREG-2.0
VREG-1.7
VREG-1.4
V
Low level output voltage 2
VOL2 (D)
1.3
1.6
1.9
V
0.4
V
10
A
+6.25
%
Counts
512
LD output
Output saturation voltage
VOL (LD)
ILD = 2mA
Output leakage current
IL (LD)
VO = 6V
Lock range
0.2
-6.25
Speed control PLL output
High level output voltage
VOH (P)
VREG-2.0
VREG-1.7
VREG-1.4
V
Low level output voltage
VOL (P)
1.3
1.6
1.9
V
GDF
0.20
0.25
0.32
VRF
0.23
0.25
0.275
Current control circuit
Drive gain
Current limiter operation
Limiter voltage
V
Integrator
Input offset voltage
VIO (INT)
Input bias current
IB (INT)
Reference voltage
VB (INT)
High level output voltage
VOH (INT)
Low level output voltage
VOL (INT)
Open-loop gain
-10
10
mV
-1
1
A
-5%
VREG/2
5%
V
IINTI = -0.1mA, No load
3.95
4.4
4.85
V
IINTI = 0.1mA, No load
0.75
1.2
1.65
45
48
fINT = 2kHz
V
dB
VCO Oscillator (C pin)
Oscillation frequency range
f (C)
C = 120pF, R = 24k
0.15
High level output voltage
VOH (C)
FIL = 2.5V
2.71
3.16
1.54
MHz
3.61
V
Low level output voltage
VOL (C)
FIL = 2.5V
2.20
2.60
3.00
V
Amplitude
V (C)
FIL = 2.5V
0.44
0.56
0.68
Vp-p
FIL pin
Output source current
IOH (FIL)
-15
-11
-6
A
Output sink current
IOL (FIL)
6
10
15
A
VREG0.59
VREG0.60
VREG0.61
V
RC pin
Comparator voltage
VRC
Low-voltage protection circuit
Operation voltage
VLVSD
8.00
8.54
9.00
V
Hysteresis width
VLVSD
0.25
0.34
0.45
V
150
175
C
30
C
Thermal shutdown operation
Thermal shutdown operation
TSD
Design target value*
TSD
Design target value*
temperature
Hysteresis width
Note : * These items are design target values and are not tested.
Continued on next page.
No.A1271-3/21
LV8105W
Continued from preceding page.
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
CLK pin
Input frequency
fI (CLK)
3
kHz
High level input voltage range
VIH (CLK)
2.0
VREG
V
Low level input voltage range
VIL (CLK)
0
1.0
V
Input open voltage
VIO (CLK)
VREG-0.5
VREG
V
Hysteresis width
VIS (CLK)
Design target value*
0.18
0.27
0.36
V
High level input current
IIH (CLK)
VCLK = 5V
-22
-10
-3
A
Low level input current
IIL (CLK)
VCLK = 0V
-133
-93
-70
A
Pull-up resistance
RU (CLK)
45
60
75
k
High level input voltage range
VIH (S/S)
2.0
VREG
V
Low level input voltage range
VIL (S/S)
0
1.0
V
Input open voltage
VIO (S/S)
VREG-0.5
VREG
V
Hysteresis width
VIS (S/S)
0.18
0.27
0.36
V
High level input current
IIH (S/S)
VS/S = 5V
-22
-10
-3
A
Low level input current
IIL (S/S)
VS/S = 0V
-133
-93
-70
A
Pull-up resistance
RU (S/S)
45
60
75
k
High level input voltage range
VIH (F/R)
2.0
VREG
V
Low level input voltage range
VIL (F/R)
0
1.0
V
Input open voltage
VIO (F/R)
VREG-0.5
VREG
V
S/S pin
F/R pin
Hysteresis width
VIS (F/R)
0.18
0.27
0.36
V
High level input current
IIH (F/R)
VF/R = 5V
-22
-10
-3
A
Low level input current
IIL (F/R)
VF/R = 0V
-133
-93
-70
A
Pull-up resistance
RU (F/R)
45
60
75
k
High level input voltage range
VIH (BR)
2.0
VREG
V
Low level input voltage range
VIL (BR)
0
1.0
V
Input open voltage
VIO (BR)
VREG-0.5
VREG
V
Hysteresis width
VIS (BR)
0.18
0.27
0.36
V
High level input current
IIH (BR)
VBR = 5V
-22
-10
-3
A
Low level input current
IIL (BR)
VBR = 0V
-133
-93
-70
A
Pull-up resistance
RU (BR)
45
60
75
k
BR pin
Note : * These items are design target values and are not tested.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
No.A1271-4/21
LV8105W
Package Dimensions
unit : mm (typ)
SQFP48(7X7)
Pd max – Ta
36
0.5
9.0
7.0
Allowable power dissipation, Pd max – W
1.5
25
24
7.0
9.0
37
48
13
1
12
0.5
0.15
0.18
Specified board : 114.3 × 76.1 × 1.6mm3
glass epoxy
Mounted on a board
1.3
1.0
0.73
Independent IC
0.5
0.45
0.25
0
– 20
(0.75)
0
20
40
60
80
100
(1.5)
0.1
1.7max
Ambient temperature, Ta – °C
WH
WOUT
WL
VH
VOUT
VL
UH
UOUT
UL
NC
RF
RFGND
Pin Assignment
36
35
34
33
32
31
30
29
28
27
26
25
24 HB
NC 37
VCC 38
23 IN3+
VG 39
22 IN3-
CP2 40
21 IN2+
CP1 41
20 IN2-
NC 42
19 IN1+
LV8105
VREG 43
18 IN1-
GND2 44
17 FGIN+
GND1 45
16 FGIN-
C 46
15 FGOUT
R 47
14 LD
1
2
3
4
5
6
7
8
9
10
11
12
NC
RC
INTOUT
INTIN
INTREF
DOUT
POUT
S/S
CLK
F/R
BR
13 FGS
CSD
FIL 48
No.A1271-5/21
LV8105W
Three-phase logic truth table (A high level input is the state where IN+ > IN-.)
F/R = “L”
F/R = “H”
IN1
Drive output
IN1
IN2
IN3
IN2
IN3
Upper gate
Lower gate
1
H
L
H
L
H
L
VH
UL
2
H
L
L
L
H
H
WH
UL
3
H
H
L
L
L
H
WH
VL
4
L
H
L
H
L
H
UH
VL
5
L
H
H
H
L
L
UH
WL
6
L
L
H
H
H
L
VH
WL
When F/R is “L”, the Hall input while the motor is rotating must be input in order from 1 to 6 of the above table.
When the Hall input is performed by the reverse order, it will not become the soft current-carrying output.
(The motor is driven by the 120 degrees current-carrying only.)
Also, when F/R is “H”, the Hall input while the motor is rotating must be input in order from 6 to 1 of the above table.
When the Hall input is performed by the reverse order, it will not become the soft current-carrying output.
(The motor is driven by the 120 degrees current-carrying only.)
S/S Input
BR Input
Input
Mode
Input
Mode
High or Open
Stop
High or Open
Brake
Low
Start
Low
Release
Current Control Characteristics
0.3
RF – INTOUT (typical characteristics)
0.25
GAIN = 0.25
RF – V
0.2
0.1
0
1.5
2.0
2.2
2.5
3.0
3.2
3.5
4.0
INTOUT – V
No.A1271-6/21
C
±5%
24kΩ R
FGIN+
0.022μF
CLK
FIL
51kΩ 0.22μF
±5%
120pF
0.1μF
FGIN-
510kΩ
8.2kΩ
0.082μF
FGS
LD
FGOUT
150pF
3kΩ
VREG
3kΩ
VREG
CLK
VCO
VREG
VCO
PLL
1/512
+
SPEED
DISCRI
SPEED
PLL
VREG
+
FGS
LD
INT
REF
RC
RC
COMP
2000pF
±5%
1μF
0.047μF
0.047μF
BR F/R
BR
F/R
CONTROL
AMP
RST
CSD
CSD
OSC
+
51kΩ
INT
INT
IN
OUT
VREG
680kΩ ±2%
FG
FIL
33kΩ
DOUT
POUT DOUT
1MΩ
POUT
0.1μF
DRIVE
LOGIC
RF
CURR
COMP
LATCH
S/S RFGND
S/S
3-HALL
MIX
EDGES
DETECT
HALL
FIL
INT
OSC
1/32
1/16
HB
110Ω
WH
62Ω
WOUT 62Ω
WL 100Ω
VH
62Ω
VOUT 62Ω
VL
100Ω
UH
UOUT
UL
0.068μF
VG
CP2
0.01μF
CP1
VREG
0.1μF
0.1μF
VCC
HB
GND1
PRE
DRIVER
CHARGE
PUMP
VREG
GND2
LVSD
HALL
HYS COMP
4700pF
4700pF
4700pF
IN1+ IN1- IN2+ IN2- IN3+ IN3-
1kΩ 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ
FREQUENCY
MULTIPLY
4700pF
1.8kΩ
51kΩ
680pF
51kΩ
180pF
100kΩ
680pF
180pF
100kΩ
51kΩ
180pF
100kΩ
680pF
100Ω
62Ω
62Ω
24V
0.1Ω
0.1μF
0.1μF
0.1μF
FW217 × 3
0.1μF 47μF
+
LV8105W
Block Diagram
(Referance constants)
No.A1271-7/21
LV8105W
Relations Hall input with Drive output
(1) When F/R = ”L” and the soft current-carrying output.
IN1
IN2
IN3
(UH)
(VH)
(WH)
120 degrees
Current-carrying
(UL)
(VL)
(WL)
UH
VH
WH
Soft
Current-carrying
UL
VL
WL
PWM control output
Synchronous rectification output
No.A1271-8/21
LV8105W
(2) When F/R = ”H” and the soft current-carrying output.
IN1
IN2
IN3
(UH)
(VH)
(WH)
120 degrees
Current-carrying
(UL)
(VL)
(WL)
UH
VH
WH
Soft
Current-carrying
UL
VL
WL
PWM control output
Synchronous rectification output
No.A1271-9/21
LV8105W
(3) When F/R = ”L” and the 120 degrees current-carrying only.
IN1
IN2
IN3
UH
VH
WH
UL
VL
WL
PWM control output
Synchronous rectification output
(4) When F/R=”H” and the 120 degrees current-carrying only.
IN1
IN2
IN3
UH
VH
WH
UL
VL
WL
PWM control output
Synchronous rectification output
No.A1271-10/21
LV8105W
Pin Functions
Pin No.
Pin name
1
CSD
Pin function
Equivalent circuit
Pin to set the operating time of the constraint
Reset circuit
VREG
protection.
Connect a capacitor between this pin and GND.
This pin combines also functions as the logic circuit
block initial reset pin.
500Ω
1
3
RC
Pin to set the speed discriminator output amplitude
switching circuit.
VREG
Connect a capacitor between this pin and GND. And
connect a resistor between VREG and this pin.
1kΩ
4
INTOUT
Integrating amplifier output pin.
3
VREG
4
105kΩ
5
INTIN
Integrating amplifier inverting input pin.
500Ω
VREG
INTOUT
30kΩ
6
INTREF
Integrating amplifier non-inverting input pin.
1/2 VREG potential.
6
500Ω
500Ω
5
Connect a capacitor between this pin and GND.
30kΩ
7
DOUT
Speed discriminator output pin.
Acceleration high, deceleration low.
VREG
7
Continued on next page.
No.A1271-11/21
LV8105W
Continued from preceding page.
Pin No.
Pin name
8
POUT
Pin function
Speed control PLL output pin.
Equivalent circuit
VREG
Outputs the phase comparison result for CLK and
FG.
8
9
S/S
Start / Stop control pin.
VREG
Low : 0V to 1.0V
High : 2.0V to VREG
Goes high when left open.
55kΩ
Low for start.
The hysteresis width is about 0.27V.
10
CLK
External clock signal input pin.
5kΩ
9
VREG
Low : 0V to 1.0V
High : 2.0V to VREG
Goes high when left open.
55kΩ
The hysteresis width is about 0.27V.
f = 3kHz, maximum.
11
F/R
Forward / reverse control pin.
5kΩ
10
VREG
Low : 0V to 1.0V
High : 2.0V to VREG
Goes high when left open.
55kΩ
Low for forward.
The hysteresis width is about 0.27V.
12
BR
Brake pin (short braking operation).
5kΩ
11
VREG
Low : 0V to 1.0V
High : 2.0V to VREG
Goes high when left open.
55kΩ
High or open for brake mode operation.
The hysteresis width is about 0.27V.
5kΩ
12
Continued on next page.
No.A1271-12/21
LV8105W
Continued from preceding page.
Pin No.
Pin name
13
FGS
Pin function
Equivalent circuit
FG amplifier Schmitt output pin.
VREG
This is an open collector output.
13
14
LD
Lock detection output pin.
VREG
This is an open collector output.
Goes low when the motor speed is within the speed
lock range (6.25%).
15
FGOUT
14
FG amplifier output pin.
VREG
This pin is connected to the FG Schmitt comparator
circuit internally in the IC.
15
105kΩ
FG Schmitt comparator
16
FGIN-
FG amplifier inverting input pin.
500Ω
VREG
FGOUT
30kΩ
17
FGIN+
FG amplifier non-inverting input pin.
1/2 VREG potential.
17
500Ω
500Ω
16
Connect a capacitor between this pin and GND.
30kΩ
IN1IN1+
IN2-
Hall input pins.
22
IN2+
IN3-
If noise on the Hall signals is a problem, insert
capacitors between the corresponding IN+ and IN-
23
IN3+
inputs.
18
19
20
21
The input is seen as a high level input when IN+ >
IN-, and as a low level input for the opposite state.
VREG
18 20 22
19 21 23
Continued on next page.
No.A1271-13/21
LV8105W
Continued from preceding page.
Pin No.
Pin name
24
HB
Pin function
Equivalent circuit
Hall bias switch pin.
VCC
Goes off when the S/S pin is the stop state.
24
25
RFGND
Output current detection reference pin.
Connect to GND side of the current detection
VREG
resistor Rf.
2kΩ
25
26
RF
Output current detection pin.
Connect to the current detection resistor Rf.
VREG
Sets the the maximum output current IOUT to be
0.25/Rf.
5kΩ
28
UL
Output pins for gate drive of the lower side N
31
VL
channel power FET.
34
WL
26
VREG
28 31 34
Continued on next page.
No.A1271-14/21
LV8105W
Continued from preceding page.
Pin No.
Pin name
30
UH
Output pins for gate drive of the upper side N
Pin function
33
VH
channel power FET.
36
WH
Equivalent circuit
VG
100Ω
30 33 36
29
UOUT
Pins to detect the source voltage of the upper side N
32
VOUT
channel power FET.
35
WOUT
100Ω
29 32 35
38
VCC
Power supply pin.
Connect a capacitor between this pin and GND for
stabilization.
39
VG
Charge pump output pin.
Connect a capacitor between this pin and VCC.
VCC
400Ω
100Ω
40
CP2
Pin to connect the capacitor for charge pump.
Connect a capacitor between this pin and CP1.
39
41
CP1
Pin to connect the capacitor for charge pump.
Connect a capacitor between this pin and CP2.
40
VCC
41
43
VREG
5V constant voltage output pin (5.6V).
Connect a capacitor between this pin and GND.
VCC
43
Continued on next page.
No.A1271-15/21
LV8105W
Continued from preceding page.
Pin No.
Pin name
44
GND2
45
GND1
46
C
Pin function
Equivalent circuit
GND pins.
GND1 and GND2 are connected in the IC.
VCO oscillation pin.
VREG
Connect a capacitor between this pin and GND.
500Ω
47
R
Pin to set the charge/discharge current of the VCO
46
VREG
circuit.
Connect a resistor between this pin and GND.
500Ω
48
FIL
VCO PLL output filter pin.
VREG
48
2
NC
47
500Ω
No connection pins.
27
37
42
No.A1271-16/21
LV8105W
Description of LV8105W
1. Speed control circuit
This IC controls the speed with a combination of the speed discriminator circuit and the PLL circuit. Therefore, when a
motor that has large load variation is used, it is possible to prevent the rotation variation as compared with the speed
control method only the speed discriminator. The speed discriminator circuit and the PLL circuit outputs an error signal
once every one FG period. The FG servo frequency signal (fFG) is controlled to have the equal frequency with the
clock signal (fCLK) which is input through the CLK pin.
fFG = fCLK
2. VCO circuit
This IC has the VCO circuit to generate the reference signal of the speed discriminator circuit. The reference signal
frequency is calculated as follows.
fVCO = fCLK 512
fVCO : Reference signal frequency, fCLK : Clock signal frequency
The components connected to the R, C and FIL pins must be connected to the GND1 pin (pin 45) with a line that is as
short as possible to reduce influence of noise.
3. Output drive circuit
This IC adopts a direct PWM drive method to reduce power loss in the output. An external output transistor is always
saturated while the transistor is on and driving force of the motor is adjusted by changing the duty that the output
transistor is on. The waveform of the coil current becomes trapezoidal with the current control and the overlap
switching of about 15 degrees. Therefore, it is possible to reduce the motor noise and the torque ripple when switching
the phase to which power is applied (Soft current-carrying).
When the 120 degrees current-carrying, the PWM switching is performed on the UL, VL and WL pins only. Also,
when the soft current-carrying, the PWM switching is performed on any the outputs (the UL, VL, WL, UH, VH and
WH pins). The PWM frequency is determined with 64kHz (typical) in the IC.
When the PWM switching of the upper side output is off, the lower side output is turned on. Also, when the PWM
switching of the lower side output is off, the upper side output is turned on (Synchronous rectification). The off-time of
the synchronous rectification is determined in the IC and varies from 1.2s to 3.1s.
4. Current limiter circuit
The current limiter circuit limits the (peak) current at the value I = VRF/Rf (VRF = 0.25V (typical), Rf : current
detection resistor). The current limitation operation consists of reducing the PWM output on-duty to suppress the
current.
High accuracy detection can be achieved by connecting the RF and RFGND pins lines near at the ends of the current
detection resistor (Rf).
5. Speed lock range
The speed lock range is less than 6.25% of the fixes speed. When the motor speed is in the lock range, the LD pin (an
open collector output) goes low. If the motor speed goes out of the lock range, the on-duty of the motor drive output is
adjusted according to the speed error to control the motor speed to be within the lock range.
As for the 120 degrees current-carrying and the soft current-carrying, when the motor speed goes out of the lock range,
the current-carrying becomes the 120 degrees current-carrying. When the motor speed is within the lock range, the
current-carrying becomes the soft current-carrying.
No.A1271-17/21
LV8105W
6. Speed discriminator output amplitude switching circuit
By the magnitude relation between the time t that is set by using the capacitor and resistor connected with the RC pin
and the clock period which is input through the CLK pin, the output amplitude of the speed discriminator switches as
follows.
When the clock period is smaller than t
VREG-1.0V
0.9V
When the clock period is bigger than t
VREG-1.7V
1.6V
When connect a resistor R between the RC pin and VREG and a capacitor C between the RC pin and GND, the above
time t is calculated as follows.
t = 0.91 R C
By the variance of the IC, “0.91” of the above formula has varied from 0.885 to 0.935.
When switching the output amplitude of the speed discriminator by the input voltage to the RC pin is performed, input
that voltage to the RC pin through the resistor of 20k.
The output amplitude of the speed discriminator is switched by the input voltage as follows.
Low level input (0V to 2V),
VREG-1.0V
0.9V
High level input (4V to 6V),
VREG-1.7V
1.6V
When there is no need for the speed discriminator output amplitude switching, connect the RC pin with GND. In this
instance, the high level output voltage of the speed discriminator becomes VREC-1.0V and the low level output voltage
of the speed discriminator becomes 0.9V.
7. Hall input signal
The input amplitude of 100mVp-p or more (differential) is desirable in the Hall sensor inputs. The closer the input
wave-form is to a square wave, the lower the required input amplitude. Inversely, a higher input amplitude is required
the closer the input waveform is to a triangular wave. Also, note that the input DC voltage must be set to be within the
common-mode input voltage range.
If a Hall sensor IC is used to provide the Hall inputs, those signals can be input to one side (either the + or - side) of the
Hall sensor signal inputs as 0 to VREG level signals if the other side is held fixed at a voltage within the common-mode
input voltage range that applies when the Hall sensors are used.
If noise on the Hall inputs is a problem, that noise must be excluded by inserting capacitors across the inputs. Those
capacitors must be located as close as possible to the input pins.
When the Hall inputs for all three phases are in the same state, all the outputs will be in the off state.
The bias of the Hall element can be cut by supplying the bias of the Hall element from the HB pin while the S/S pin is
a stop mode(Hall bias switch).
The Hall input frequency range possible for the soft current-carrying is determined from 30Hz to 500Hz (IN1
frequency).
8. S/S switching circuit
When the S/S pin is set to the low level, S/S switching circuit is the start mode. Inversely, when the S/S pin is set to the
high level or open, S/S switching circuit is the stop mode. At the stop mode, all the outputs will be in the off state.
This IC will be in the power save state of decreasing the supply current at the stop mode.
9. Braking circuit
When the BR pin is set to the high level or open, the brake is on. Inversely, when the BR pin is set to the low level, the
brake is released. The brake becomes a short brake that turns on the lower side output transistors for all phases (the UL,
VL and WL side) and turns off the upper side output transistors for all phases (the UH, VH and WH side). Note that the
current limiter does not operate during braking. During braking, the duty is set to 100%, regardless of the motor speed.
The current that flows in the output transistors during braking is determined by the motor back EMF voltage and the
coil resistance. Applications must be designed so that this current does not exceed the ratings of the output transistors
used. (The higher the motor speed at which braking is applied, the more severe this problem becomes).
The braking function can be applied and released with the IC at the start mode. This means that motor startup and stop
control can be performed using the BR pin with the S/S pin held at the low level (the start mode). If the startup time
becomes excessive, it can be reduced by controlling the motor startup and stop with the BR pin rather than with the S/S
pin (Since the IC will be in the power save state at the stop mode, enough time for the VCO circuit to stabilize will be
required at the beginning of the motor start operation).
No.A1271-18/21
LV8105W
10. Forward/Reverse switching circuit
The motor rotation direction can be switched by using the F/R pin. However, the following notes must be observed if
the motor direction is switched while the motor is turning.
• This IC is designed to avoid through currents when switching directions. However, increases in the motor supply
voltage (due to instantaneous return of the motor current to the power supply) during direction switching may cause
problems. The values of the capacitors inserted between power and ground must be increased if this increase is
excessive.
• If the motor current after direction switching exceeds the current limit value, the PWM drive side outputs will be
turned off, but the opposite side output will be in the short-circuit braking state, and a current determined by the motor
back EMF voltage and the coil resistance will flow. Applications must be designed so that this current does not exceed
the ratings of the output transistors used. (The higher the motor speed at which the direction is switched, the more
severe this problem becomes.)
11. Constraint protection circuit
The LV8105W includes an on-chip constraint protection circuit to protect the motor and the output transistors in motor
constraint mode. If the LD output remains high (indicating the unlocked state) for a fixed period in the motor drive state
(the S/S pin : start, the BR pin : brake release), the lower side output transistors (the UL, VL and WL side) are turned off.
This time can be set by adjusting the oscillation frequency of the CSD pin by using a external capacitor. By the
capacitance of the capacitor attached to the CSD pin, the set time is calculated as follows.
The set time (sec) = 60.8 C (F)
When a 0.047F capacitor is connected with the CSD pin, the set time becomes about 2.9sec.
By the variance of the IC, “60.8” of the above formula has varied from 40.8 to 80.8.
To restart a motor by cancelling the constraint protection function, any of the following operation is necessary.
• Put the S/S pin into the start state again after the stop state (about 1ms or more).
• Put the BR pin into the brake release state again after the braking state (about 1ms or more).
• Turn on the power supply again after the turn off state.
When the clock disconnect protection function, the thermal shutdown function and the low-voltage protection function
are operating, the constraint protection function does not operate even if the motor does not rotate.
The oscillation waveform of the CSD pin is used as the reference signal for some circuits in addition to the motor
constraint protection circuit. Therefore, it is desirable to oscillate the CSD pin even if the constraint protection function
is unnecessary. If the constraint protection circuit is not used, the oscillation of the CSD pin must be stopped by
connecting a 220k resistor and a 0.01F capacitor in parallel between the CSD pin and GND. However, in that case,
the clock disconnection protection circuit will no longer function. Also, the synchronous rectification does not operate
in any of the following cases.
• When the motor does not rotate in the motor constrained state since the motor is started up by the S/S or the BR input,
the PWM switching is performed by using the current limiter circuit. But, the synchronous rectification does not
operate when the oscillation of the CSD pin is stopped.
The CSD pin combines also functions as the initial reset pin. The time that the CSD pin voltage is charged to about
1.25V is determined as the initial reset. At the initial reset, all the outputs will be in the off state.
12. Clock disconnection protection circuit
If the clock input through the CLK pin goes to the no input state in the motor drive state (the S/S pin : start, the BR pin :
brake release), the lower side output transistors (the UL, VL and WL side) are turned off. If the clock is resupplied, the
clock disconnection protection function is cancelled.
When the clock period is longer than about thirty-fourth part of the constraint protection set time, the clock
disconnection protection circuit judges the clock input to be the no input state and this protection function will operate.
13. Thermal shutdown circuit
If the junction temperature rises to the specified temperature (TSD) in the motor drive state (the S/S pin : start, the BR
pin : brake release), the lower side output transistors (the UL, VL and WL side) are turned off. If the junction
temperature falls to more than the hysteresis width (TSD), the thermal shutdown function is cancelled.
No.A1271-19/21
LV8105W
14. Low-voltage protection circuit
The LV8105W includes a low-voltage protection circuit to protect against incorrect operation when the VCC power is
applied or if the power supply voltage falls below its operating level. When the VCC voltage falls under the specified
voltage (VLVSD), all the outputs will be in the off state. If the VCC voltage rises to more than the hysteresis width
(VLVSD), the low-voltage protection function is cancelled.
15. Power supply stabilization
Since this IC is used in applications that flow the large output current, the power supply line is subject to fluctuations.
Therefore, capacitors with capacitance adequate to stabilize the power supply voltage must be connected between the
VCC pin and GND. If diodes are inserted in the power supply line to prevent the IC destruction due to reverse power
supply connection, since this makes the power supply voltage even more subject to fluctuations, even larger
capacitance will be required.
16. Ground lines
The signal system GND and the output system GND must be separated, and connected to one GND at the connector. As
the large current flows to the output system GND, this GND line must be made as short as possible.
Output system GND : GND for Rf and VCC line capacitors
Signal system GND : GND for the IC and external components
17. Integrating amplifier
The integrating amplifier integrates the speed error pulses and phase error pulses and converts them to the speed
command voltage. At that time it also sets the control loop gain and the frequency characteristics. External components
of the integrating amplifier must be placed as close to the IC as possible to reduce influence of noise.
18. FG amplifier
The FG amplifier normally makes up a filter amplifier to reject noise. Since a clamp circuit has been added at the FG
amplifier output, the output amplitude is clamped at about 3.2Vp-p, even if the amplifier gain is increased.
After the FG amplifier, the Schmitt comparator on one side hysteresis(200mV (typical)) is inserted. The Schmitt
comparator output (FGS output) becomes high level when the FG amplifier output is lower than the FGIN+ voltage,
and becomes low level when the FG amplifier output is higher to more than Schmitt width as compared with the FGIN+
voltage. Therefore, it is desirable that the amplifier gain be set so that the output amplitude is over 1.0Vp-p at the lowest
controlled speed to be used.
The capacitor connected between the FGIN+ pin and GND is required for bias voltage stabilization. This capacitor
must be connected to the GND1 pin (pin 45) with a line that is as short as possible to reduce influence of noise.
As the FG amplifier and the FGS output are operating even if the S/S pin is the stop state, it is possible to monitor the
motor rotation by the FGS output.
No.A1271-20/21
LV8105W
ORDERING INFORMATION
Device
LV8105W-MPB-E
Package
SQFP48(7X7)
(Pb-Free)
LV8105W-TLM-E
SQFP48(7X7)
(Pb-Free)
Shipping (Qty / Packing)
50 / Tray Foam
1000 / Tape & Reel
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