LV8105W

Ordering number : ENA1271 Bi-CMOS IC LV8105W Overview For Variable Speed Control Three-Phase Brushless Motor Predriver The LV8105W is a predriver IC designed for variable speed control of 3-phase brushless motors. It can be used to implement a high- and low-side output n-channel power FET drive circuit using a built-in charge pump circuit. High-efficiency drive is possible through the use of low noise PWM drive and synchronous rectifying systems. Functions • Speed discriminator and PLL speed control system • Built-in VCO circuit for generating the speed discriminator reference signal • Speed lock detection output • Hall bias switch • Braking circuit (short braking) • Full complement of on-chip protection circuits, including current limiter and lock protection circuits. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage Charge pump output voltage Output current Symbol VCC max VG max IO max1 IO max2 Allowable power dissipation Pd max1 Pd max2 Operating temperature Storage temperature Topr Tstg VCC = VG VG pin Pins UL, VL, WL Pins UH, VH, WH, UOUT, VOUT and WOUT Independent IC Mounted on the specified board * Conditions Ratings 42 42 -15 to 15 -20 to 20 0.45 1.30 -20 to +80 -55 to +150 Unit V V mA mA W W °C °C * Specified board:114.3mm × 76.1mm × 1.6mm, glass epoxy board. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 82008 MS PC 20080710-S00008 No.A1271-1/21 LV8105W Allowable Operating range at Ta = 25°C Parameter Supply voltage range 5V constant voltage output current HB pin output current LD pin applied voltage LD pin output current FGS pin applied voltage FGS pin output current Symbol VCC IREG IHB VLD ILD VFGS IFGS Conditions Ratings 16 to 28 0 to -10 0 to -25 0 to 6 0 to 5 0 to 6 0 to 5 Unit V mA mA V mA V mA Electrical Characteristics at Ta = 25°C, VCC = 24V Parameter Supply current 1 Supply current 2 Symbol ICC1 ICC2 At stop Conditions min Ratings typ 7 3 max 8.8 3.8 mA mA Unit 5V Constant-voltage Output (VREG pin) Output voltage Line regulation Load regulation VREG ∆V (REG1) ∆V (REG2) IO = 5mA VCC = 16 to 28V IO = -5 to -10mA 5.2 5.6 10 10 6.0 50 50 V mV mV Output block / Conditions : apply a VG voltage of 33V High level output voltage 1 Low level output voltage 1 High level output voltage 2 Low level output voltage 2 PWM frequency Internal Oscillator Oscillation frequency Charge Pump Output (VG pin) Output voltage CP1 pin High level output voltage Low level output voltage Charge pump frequency Hall Amplifier Input bias current Common-mode input voltage range 1 Common-mode input voltage range 2 Hall input sensitivity Hysteresis width Input voltage Low → High Input voltage High → Low HB pin Output voltage Output leakage current FG Amplifier Input offset voltage Input bias current Reference voltage High level output voltage Low level output voltage FG input sensitivity Schmitt width of the next stage Operation frequency range Open-loop gain fFG = 2kHz 45 48 VIO (FG) IB (FG) VB (FG) VOH (FG) VOL (FG) IFGI = -0.1mA, No load IFGI = 0.1mA, No load GAIN : 100 times One-side hysteresis comparator -10 -1 -5% 3.95 0.75 3 120 200 280 3 VREG/2 4.4 1.2 10 1 5% 4.85 1.65 mV µA V V V mV mV kHz dB VHBO IL (HB) IHB = -15mA VO = 0V VCC-0.8 -10 VCC-0.5 VCC-0.35 V µA ∆VIN (HA) VSLH VSHL IHB (HA) VICM1 VICM2 When using Hall elements At one-side input bias (Hall IC application) SIN wave -2 0.3 0 50 5 2 -12 13 7 -6 24 12 -2 -0.1 3.5 VREG µA V V mVp-p mV mV mV VOH (CP1) VOL (CP1) f (CP1) ICP1 = -2mA ICP1 = 2mA VCC-1.35 0.5 102 VCC-1.0 0.65 128 VCC-0.7 0.8 154 V V kHz VGOUT VCC+8.0 VCC+9.0 VCC+10.0 V f (REF) 1.65 2.05 2.45 MHz VOH1 VOL1 VOH2 VOL2 f (PWM) Pins UL, VL and WL Pins UL, VL and WL Pins UH, VH and WH Pins UH, VH and WH IOH = -2mA IOL = 2mA IOH = -2mA IOL = 2mA VREG-0.65 0.35 VG-0.65 0.45 51 VREG-0.5 0.5 VG-0.5 0.6 64 VREG-0.35 0.65 VG-0.35 0.8 77 V V V V kHz Continued on next page. No.A1271-2/21 LV8105W Continued from preceding page. Parameter FGS output Output saturation voltage Output leakage current CSD oscillator High level output voltage Low level output voltage Amplitude External capacitor charge current External capacitor discharge current Oscillation frequency Speed Discriminator output High level output voltage 1 Low level output voltage 1 High level output voltage 2 Low level output voltage 2 Counts LD output Output saturation voltage Output leakage current Lock range Speed control PLL output High level output voltage Low level output voltage Current control circuit Drive gain Current limiter operation Limiter voltage Integrator Input offset voltage Input bias current Reference voltage High level output voltage Low level output voltage Open-loop gain VCO Oscillator (C pin) Oscillation frequency range High level output voltage Low level output voltage Amplitude FIL pin Output source current Output sink current RC pin Comparator voltage Low-voltage protection circuit Operation voltage Hysteresis width Thermal shutdown operation Thermal shutdown operation temperature Hysteresis width ∆TSD Design target value* 30 °C TSD Design target value* 150 175 °C VLVSD ∆VLVSD 8.00 0.25 8.54 0.34 9.00 0.45 V V VRC VREG×0.59 VREG×0.60 VREG×0.61 V IOH (FIL) IOL (FIL) -15 6 -11 10 -6 15 µA µA f (C) VOH (C) VOL (C) V (C) C = 120pF, R = 24kΩ FIL = 2.5V FIL = 2.5V FIL = 2.5V 0.15 2.71 2.20 0.44 3.16 2.60 0.56 1.54 3.61 3.00 0.68 MHz V V Vp-p VIO (INT) IB (INT) VB (INT) VOH (INT) VOL (INT) IINTI = -0.1mA, No load IINTI = 0.1mA, No load fINT = 2kHz -10 -1 -5% 3.95 0.75 45 VREG/2 4.4 1.2 48 10 1 5% 4.85 1.65 mV µA V V V dB VRF 0.23 0.25 0.275 V GDF 0.20 0.25 0.32 VOH (P) VOL (P) VREG-2.0 1.3 VREG-1.7 1.6 VREG-1.4 1.9 V V VOL (LD) IL (LD) ILD = 2mA VO = 6V -6.25 0.2 0.4 10 +6.25 V µA % VOH1 (D) VOL1 (D) VOH2 (D) VOL2 (D) VREG-1.25 0.65 VREG-2.0 1.3 VREG-1.0 0.9 VREG-1.7 1.6 512 VREG-0.75 1.15 VREG-1.4 1.9 V V V V VOH (CSD) VOL (CSD) V (CSD) ICHG1 ICHG2 f (CSD) C = 0.047µF 2.9 1.6 1.15 -13 7.5 3.4 2.0 1.4 -10 10.5 78 3.9 2.4 1.65 -7 13.5 V V Vp-p µA µA Hz VOL (FGS) IL (FGS) IFGS = 2mA VO = 6V 0.2 0.4 10 V µA Symbol Conditions min Ratings typ max Unit Note : * These items are design target values and are not tested. Continued on next page. No.A1271-3/21 LV8105W Continued from preceding page. Parameter CLK pin Input frequency High level input voltage range Low level input voltage range Input open voltage Hysteresis width High level input current Low level input current Pull-up resistance S/S pin High level input voltage range Low level input voltage range Input open voltage Hysteresis width High level input current Low level input current Pull-up resistance F/R pin High level input voltage range Low level input voltage range Input open voltage Hysteresis width High level input current Low level input current Pull-up resistance BR pin High level input voltage range Low level input voltage range Input open voltage Hysteresis width High level input current Low level input current Pull-up resistance VIH (BR) VIL (BR) VIO (BR) VIS (BR) IIH (BR) IIL (BR) RU (BR) VBR = 5V VBR = 0V 2.0 0 VREG-0.5 0.18 -22 -133 45 0.27 -10 -93 60 VREG 1.0 VREG 0.36 -3 -70 75 V V V V µA µA kΩ VIH (F/R) VIL (F/R) VIO (F/R) VIS (F/R) IIH (F/R) IIL (F/R) RU (F/R) VF/R = 5V VF/R = 0V 2.0 0 VREG-0.5 0.18 -22 -133 45 0.27 -10 -93 60 VREG 1.0 VREG 0.36 -3 -70 75 V V V V µA µA kΩ VIH (S/S) VIL (S/S) VIO (S/S) VIS (S/S) IIH (S/S) IIL (S/S) RU (S/S) VS/S = 5V VS/S = 0V 2.0 0 VREG-0.5 0.18 -22 -133 45 0.27 -10 -93 60 VREG 1.0 VREG 0.36 -3 -70 75 V V V V µA µA kΩ fI (CLK) VIH (CLK) VIL (CLK) VIO (CLK) VIS (CLK) IIH (CLK) IIL (CLK) RU (CLK) Design target value* VCLK = 5V VCLK = 0V 2.0 0 VREG-0.5 0.18 -22 -133 45 0.27 -10 -93 60 3 VREG 1.0 VREG 0.36 -3 -70 75 kHz V V V V µA µA kΩ Symbol Conditions min Ratings typ max Unit Note : * These items are design target values and are not tested. No.A1271-4/21 LV8105W Package Dimensions unit : mm (typ) 3163B 1.5 Pd max – Ta Specified board : 114.3 × 76.1 × 1.6mm3 glass epoxy Mounted on a board 36 37 25 24 0.5 9.0 7.0 Allowable power dissipation, Pd max – W 1.3 1.0 7.0 9.0 0.73 48 1 0.5 (0.75) 12 0.18 13 0.5 0.45 Independent IC 0.25 0.15 0 – 20 0 20 40 60 80 100 Ambient temperature, Ta – °C 1.7max (1.5) 0.1 SANYO : SQFP48(7X7) Pin Assignment RFGND 25 24 HB 23 IN3+ 22 IN321 IN2+ 20 IN219 IN1+ 18 IN117 FGIN+ 16 FGIN15 FGOUT 14 LD 13 FGS 1 2 3 4 5 6 7 8 9 10 11 12 WOUT UOUT VOUT WH WL UH NC 27 VH 36 NC 37 VCC 38 VG 39 CP2 40 CP1 41 NC 42 35 34 33 32 31 30 29 28 26 LV8105 VREG 43 GND2 44 GND1 45 C 46 R 47 FIL 48 INTOUT INTIN INTREF POUT DOUT S/S F/R RF UL VL CSD CLK NC RC BR No.A1271-5/21 LV8105W Three-phase logic truth table (A high level input is the state where IN+ > IN-.) F/R = “L” IN1 1 2 3 4 5 6 H H H L L L IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H F/R = “H” IN2 H H L L L H IN3 L H H H L L Drive output Upper gate VH WH WH UH UH VH Lower gate UL UL VL VL WL WL When F/R is “L”, the Hall input while the motor is rotating must be input in order from 1 to 6 of the above table. When the Hall input is performed by the reverse order, it will not become the soft current-carrying output. (The motor is driven by the 120 degrees current-carrying only.) Also, when F/R is “H”, the Hall input while the motor is rotating must be input in order from 6 to 1 of the above table. When the Hall input is performed by the reverse order, it will not become the soft current-carrying output. (The motor is driven by the 120 degrees current-carrying only.) S/S Input Input High or Open Low Mode Stop Start BR Input Input High or Open Low Mode Brake Release Current Control Characteristics RF – INTOUT (typical characteristics) 0.3 0.25 0.2 GAIN = 0.25 RF – V 0.1 0 1.5 2.0 2.2 2.5 3.0 3.2 3.5 4.0 INTOUT – V No.A1271-6/21 0.1µF 1µF 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ 110Ω 4700pF 4700pF 4700pF 4700pF IN1+ IN1- IN2+ IN2- IN3+ IN3HB VCC FREQUENCY MULTIPLY LVSD VREG VREG 0.1µF HALL FIL 0.1µF + 0.1µF 47µF 24V 51kΩ INT INT IN OUT VREG + CONTROL AMP HALL HYS COMP HB 0.047µF 1.8kΩ Block Diagram (Referance constants) 1MΩ POUT INT REF 33kΩ DOUT VREG POUT DOUT 3kΩ LD LD SPEED DISCRI VREG SPEED PLL EDGES DETECT 3-HALL MIX CHARGE PUMP 3kΩ FGS FGS FG FIL 150pF FW217 × 3 FGOUT 0.082µF 510kΩ FGIN- 0.01µF CP1 CP2 0.068µF VG 62Ω 62Ω 100Ω 100kΩ 0.1µF 180pF 680pF 8.2kΩ LV8105W 0.1µF RST DRIVE LOGIC FGIN+ + + VREG 51kΩ 100kΩ 0.1µF VH 62Ω VOUT 62Ω VL 100Ω PRE DRIVER 180pF 680pF UH UOUT UL ±5% 120pF BR F/R S/S ±5% 24kΩ R CSD OSC LATCH C RC COMP VCO 1/512 51kΩ 0.22µF 1/32 1/16 51kΩ 100kΩ CURR COMP INT OSC 0.1µF 180pF FIL 0.022µF CLK VCO PLL WH 62Ω WOUT 62Ω WL 100Ω CLK 680kΩ ±2% RC 0.047µF CSD 2000pF ±5% BR F/R VREG S/S RFGND RF GND2 GND1 680pF 51kΩ 0.1Ω No.A1271-7/21 LV8105W Relations Hall input with Drive output (1) When F/R = ”L” and the soft current-carrying output. IN1 IN2 IN3 (UH) (VH) (WH) 120 degrees Current-carrying (UL) (VL) (WL) UH VH WH Soft Current-carrying UL VL WL PWM control output Synchronous rectification output No.A1271-8/21 LV8105W (2) When F/R = ”H” and the soft current-carrying output. IN1 IN2 IN3 (UH) (VH) (WH) 120 degrees Current-carrying (UL) (VL) (WL) UH VH WH Soft Current-carrying UL VL WL PWM control output Synchronous rectification output No.A1271-9/21 LV8105W (3) When F/R = ”L” and the 120 degrees current-carrying only. IN1 IN2 IN3 UH VH WH UL VL WL PWM control output Synchronous rectification output (4) When F/R=”H” and the 120 degrees current-carrying only. IN1 IN2 IN3 UH VH WH UL VL WL PWM control output Synchronous rectification output No.A1271-10/21 LV8105W Pin Functions Pin No. 1 Pin name CSD protection. Connect a capacitor between this pin and GND. This pin combines also functions as the logic circuit block initial reset pin. Pin function Pin to set the operating time of the constraint Equivalent circuit VREG Reset circuit 500Ω 1 3 RC Pin to set the speed discriminator output amplitude switching circuit. Connect a capacitor between this pin and GND. And connect a resistor between VREG and this pin. VREG 1kΩ 3 4 INTOUT Integrating amplifier output pin. VREG 4 105kΩ 5 INTIN Integrating amplifier inverting input pin. 500Ω VREG 30kΩ INTOUT 6 INTREF Integrating amplifier non-inverting input pin. 1/2 VREG potential. Connect a capacitor between this pin and GND. 6 500Ω 30kΩ 500Ω 5 7 DOUT Speed discriminator output pin. Acceleration → high, deceleration → low. VREG 7 Continued on next page. No.A1271-11/21 LV8105W Continued from preceding page. Pin No. 8 Pin name POUT Pin function Speed control PLL output pin. Outputs the phase comparison result for CLK and FG. Equivalent circuit VREG 8 9 S/S Start / Stop control pin. Low : 0V to 1.0V High : 2.0V to VREG Goes high when left open. Low for start. The hysteresis width is about 0.27V. VREG 55kΩ 5kΩ 9 10 CLK External clock signal input pin. Low : 0V to 1.0V High : 2.0V to VREG Goes high when left open. The hysteresis width is about 0.27V. f = 3kHz, maximum. VREG 55kΩ 5kΩ 10 11 F/R Forward / reverse control pin. Low : 0V to 1.0V High : 2.0V to VREG Goes high when left open. Low for forward. The hysteresis width is about 0.27V. VREG 55kΩ 5kΩ 11 12 BR Brake pin (short braking operation). Low : 0V to 1.0V High : 2.0V to VREG Goes high when left open. High or open for brake mode operation. The hysteresis width is about 0.27V. VREG 55kΩ 5kΩ 12 Continued on next page. No.A1271-12/21 LV8105W Continued from preceding page. Pin No. 13 Pin name FGS Pin function FG amplifier Schmitt output pin. This is an open collector output. Equivalent circuit VREG 13 14 LD Lock detection output pin. This is an open collector output. Goes low when the motor speed is within the speed lock range (±6.25%). VREG 14 15 FGOUT FG amplifier output pin. This pin is connected to the FG Schmitt comparator circuit internally in the IC. VREG 15 105kΩ FG Schmitt comparator 16 FGINFG amplifier inverting input pin. 500Ω VREG 30kΩ FGOUT 17 FGIN+ FG amplifier non-inverting input pin. 1/2 VREG potential. Connect a capacitor between this pin and GND. 17 500Ω 30kΩ 500Ω 16 18 19 20 21 22 23 IN1IN1+ IN2IN2+ IN3IN3+ Hall input pins. The input is seen as a high level input when IN+ > IN-, and as a low level input for the opposite state. If noise on the Hall signals is a problem, insert capacitors between the corresponding IN+ and INinputs. VREG 18 20 22 19 21 23 Continued on next page. No.A1271-13/21 LV8105W Continued from preceding page. Pin No. 24 Pin name HB Pin function Hall bias switch pin. Goes off when the S/S pin is the stop state. Equivalent circuit VCC 24 25 RFGND Output current detection reference pin. Connect to GND side of the current detection resistor Rf. VREG 25 2kΩ 26 RF Output current detection pin. Connect to the current detection resistor Rf. Sets the the maximum output current IOUT to be 0.25/Rf. VREG 5kΩ 26 28 31 34 UL VL WL Output pins for gate drive of the lower side N channel power FET. VREG 28 31 34 Continued on next page. No.A1271-14/21 LV8105W Continued from preceding page. Pin No. 30 33 36 Pin name UH VH WH Pin function Output pins for gate drive of the upper side N channel power FET. Equivalent circuit VG 100Ω 30 33 36 29 32 35 UOUT VOUT WOUT Pins to detect the source voltage of the upper side N channel power FET. 100Ω 29 32 35 38 VCC Power supply pin. Connect a capacitor between this pin and GND for stabilization. 39 VG Charge pump output pin. Connect a capacitor between this pin and VCC. VCC 400Ω 100Ω 40 CP2 Pin to connect the capacitor for charge pump. Connect a capacitor between this pin and CP1. 39 40 41 CP1 Pin to connect the capacitor for charge pump. Connect a capacitor between this pin and CP2. VCC 41 43 VREG 5V constant voltage output pin (5.6V). Connect a capacitor between this pin and GND. VCC 43 Continued on next page. No.A1271-15/21 LV8105W Continued from preceding page. Pin No. 44 45 46 Pin name GND2 GND1 C GND pins. GND1 and GND2 are connected in the IC. VCO oscillation pin. Connect a capacitor between this pin and GND. Pin function Equivalent circuit VREG 500Ω 46 47 R Pin to set the charge/discharge current of the VCO circuit. Connect a resistor between this pin and GND. VREG 500Ω 47 48 FIL VCO PLL output filter pin. VREG 48 500Ω 2 27 37 42 NC No connection pins. No.A1271-16/21 LV8105W Description of LV8105W 1. Speed control circuit This IC controls the speed with a combination of the speed discriminator circuit and the PLL circuit. Therefore, when a motor that has large load variation is used, it is possible to prevent the rotation variation as compared with the speed control method only the speed discriminator. The speed discriminator circuit and the PLL circuit outputs an error signal once every one FG period. The FG servo frequency signal (fFG) is controlled to have the equal frequency with the clock signal (fCLK) which is input through the CLK pin. fFG = fCLK 2. VCO circuit This IC has the VCO circuit to generate the reference signal of the speed discriminator circuit. The reference signal frequency is calculated as follows. fVCO = fCLK × 512 fVCO : Reference signal frequency, fCLK : Clock signal frequency The components connected to the R, C and FIL pins must be connected to the GND1 pin (pin 45) with a line that is as short as possible to reduce influence of noise. 3. Output drive circuit This IC adopts a direct PWM drive method to reduce power loss in the output. An external output transistor is always saturated while the transistor is on and driving force of the motor is adjusted by changing the duty that the output transistor is on. The waveform of the coil current becomes trapezoidal with the current control and the overlap switching of about 15 degrees. Therefore, it is possible to reduce the motor noise and the torque ripple when switching the phase to which power is applied (Soft current-carrying). When the 120 degrees current-carrying, the PWM switching is performed on the UL, VL and WL pins only. Also, when the soft current-carrying, the PWM switching is performed on any the outputs (the UL, VL, WL, UH, VH and WH pins). The PWM frequency is determined with 64kHz (typical) in the IC. When the PWM switching of the upper side output is off, the lower side output is turned on. Also, when the PWM switching of the lower side output is off, the upper side output is turned on (Synchronous rectification). The off-time of the synchronous rectification is determined in the IC and varies from 1.2µs to 3.1µs. 4. Current limiter circuit The current limiter circuit limits the (peak) current at the value I = VRF/Rf (VRF = 0.25V (typical), Rf : current detection resistor). The current limitation operation consists of reducing the PWM output on-duty to suppress the current. High accuracy detection can be achieved by connecting the RF and RFGND pins lines near at the ends of the current detection resistor (Rf). 5. Speed lock range The speed lock range is less than ±6.25% of the fixes speed. When the motor speed is in the lock range, the LD pin (an open collector output) goes low. If the motor speed goes out of the lock range, the on-duty of the motor drive output is adjusted according to the speed error to control the motor speed to be within the lock range. As for the 120 degrees current-carrying and the soft current-carrying, when the motor speed goes out of the lock range, the current-carrying becomes the 120 degrees current-carrying. When the motor speed is within the lock range, the current-carrying becomes the soft current-carrying. No.A1271-17/21 LV8105W 6. Speed discriminator output amplitude switching circuit By the magnitude relation between the time t that is set by using the capacitor and resistor connected with the RC pin and the clock period which is input through the CLK pin, the output amplitude of the speed discriminator switches as follows. When the clock period is smaller than t VREG-1.0V 0.9V When the clock period is bigger than t VREG-1.7V 1.6V When connect a resistor R between the RC pin and VREG and a capacitor C between the RC pin and GND, the above time t is calculated as follows. t = 0.91 × R × C By the variance of the IC, “0.91” of the above formula has varied from 0.885 to 0.935. When switching the output amplitude of the speed discriminator by the input voltage to the RC pin is performed, input that voltage to the RC pin through the resistor of 20kΩ. The output amplitude of the speed discriminator is switched by the input voltage as follows. Low level input (0V to 2V), VREG-1.0V 0.9V High level input (4V to 6V), VREG-1.7V 1.6V When there is no need for the speed discriminator output amplitude switching, connect the RC pin with GND. In this instance, the high level output voltage of the speed discriminator becomes VREC-1.0V and the low level output voltage of the speed discriminator becomes 0.9V. 7. Hall input signal The input amplitude of 100mVp-p or more (differential) is desirable in the Hall sensor inputs. The closer the input wave-form is to a square wave, the lower the required input amplitude. Inversely, a higher input amplitude is required the closer the input waveform is to a triangular wave. Also, note that the input DC voltage must be set to be within the common-mode input voltage range. If a Hall sensor IC is used to provide the Hall inputs, those signals can be input to one side (either the + or - side) of the Hall sensor signal inputs as 0 to VREG level signals if the other side is held fixed at a voltage within the common-mode input voltage range that applies when the Hall sensors are used. If noise on the Hall inputs is a problem, that noise must be excluded by inserting capacitors across the inputs. Those capacitors must be located as close as possible to the input pins. When the Hall inputs for all three phases are in the same state, all the outputs will be in the off state. The bias of the Hall element can be cut by supplying the bias of the Hall element from the HB pin while the S/S pin is a stop mode(Hall bias switch). The Hall input frequency range possible for the soft current-carrying is determined from 30Hz to 500Hz (IN1 frequency). 8. S/S switching circuit When the S/S pin is set to the low level, S/S switching circuit is the start mode. Inversely, when the S/S pin is set to the high level or open, S/S switching circuit is the stop mode. At the stop mode, all the outputs will be in the off state. This IC will be in the power save state of decreasing the supply current at the stop mode. 9. Braking circuit When the BR pin is set to the high level or open, the brake is on. Inversely, when the BR pin is set to the low level, the brake is released. The brake becomes a short brake that turns on the lower side output transistors for all phases (the UL, VL and WL side) and turns off the upper side output transistors for all phases (the UH, VH and WH side). Note that the current limiter does not operate during braking. During braking, the duty is set to 100%, regardless of the motor speed. The current that flows in the output transistors during braking is determined by the motor back EMF voltage and the coil resistance. Applications must be designed so that this current does not exceed the ratings of the output transistors used. (The higher the motor speed at which braking is applied, the more severe this problem becomes). The braking function can be applied and released with the IC at the start mode. This means that motor startup and stop control can be performed using the BR pin with the S/S pin held at the low level (the start mode). If the startup time becomes excessive, it can be reduced by controlling the motor startup and stop with the BR pin rather than with the S/S pin (Since the IC will be in the power save state at the stop mode, enough time for the VCO circuit to stabilize will be required at the beginning of the motor start operation). No.A1271-18/21 LV8105W 10. Forward/Reverse switching circuit The motor rotation direction can be switched by using the F/R pin. However, the following notes must be observed if the motor direction is switched while the motor is turning. • This IC is designed to avoid through currents when switching directions. However, increases in the motor supply voltage (due to instantaneous return of the motor current to the power supply) during direction switching may cause problems. The values of the capacitors inserted between power and ground must be increased if this increase is excessive. • If the motor current after direction switching exceeds the current limit value, the PWM drive side outputs will be turned off, but the opposite side output will be in the short-circuit braking state, and a current determined by the motor back EMF voltage and the coil resistance will flow. Applications must be designed so that this current does not exceed the ratings of the output transistors used. (The higher the motor speed at which the direction is switched, the more severe this problem becomes.) 11. Constraint protection circuit The LV8105W includes an on-chip constraint protection circuit to protect the motor and the output transistors in motor constraint mode. If the LD output remains high (indicating the unlocked state) for a fixed period in the motor drive state (the S/S pin : start, the BR pin : brake release), the lower side output transistors (the UL, VL and WL side) are turned off. This time can be set by adjusting the oscillation frequency of the CSD pin by using a external capacitor. By the capacitance of the capacitor attached to the CSD pin, the set time is calculated as follows. The set time (sec) = 60.8 × C (µF) When a 0.047µF capacitor is connected with the CSD pin, the set time becomes about 2.9sec. By the variance of the IC, “60.8” of the above formula has varied from 40.8 to 80.8. To restart a motor by cancelling the constraint protection function, any of the following operation is necessary. • Put the S/S pin into the start state again after the stop state (about 1ms or more). • Put the BR pin into the brake release state again after the braking state (about 1ms or more). • Turn on the power supply again after the turn off state. When the clock disconnect protection function, the thermal shutdown function and the low-voltage protection function are operating, the constraint protection function does not operate even if the motor does not rotate. The oscillation waveform of the CSD pin is used as the reference signal for some circuits in addition to the motor constraint protection circuit. Therefore, it is desirable to oscillate the CSD pin even if the constraint protection function is unnecessary. If the constraint protection circuit is not used, the oscillation of the CSD pin must be stopped by connecting a 220kΩ resistor and a 0.01µF capacitor in parallel between the CSD pin and GND. However, in that case, the clock disconnection protection circuit will no longer function. Also, the synchronous rectification does not operate in any of the following cases. • When the motor does not rotate in the motor constrained state since the motor is started up by the S/S or the BR input, the PWM switching is performed by using the current limiter circuit. But, the synchronous rectification does not operate when the oscillation of the CSD pin is stopped. The CSD pin combines also functions as the initial reset pin. The time that the CSD pin voltage is charged to about 1.25V is determined as the initial reset. At the initial reset, all the outputs will be in the off state. 12. Clock disconnection protection circuit If the clock input through the CLK pin goes to the no input state in the motor drive state (the S/S pin : start, the BR pin : brake release), the lower side output transistors (the UL, VL and WL side) are turned off. If the clock is resupplied, the clock disconnection protection function is cancelled. When the clock period is longer than about thirty-fourth part of the constraint protection set time, the clock disconnection protection circuit judges the clock input to be the no input state and this protection function will operate. 13. Thermal shutdown circuit If the junction temperature rises to the specified temperature (TSD) in the motor drive state (the S/S pin : start, the BR pin : brake release), the lower side output transistors (the UL, VL and WL side) are turned off. If the junction temperature falls to more than the hysteresis width (∆TSD), the thermal shutdown function is cancelled. No.A1271-19/21 LV8105W 14. Low-voltage protection circuit The LV8105W includes a low-voltage protection circuit to protect against incorrect operation when the VCC power is applied or if the power supply voltage falls below its operating level. When the VCC voltage falls under the specified voltage (VLVSD), all the outputs will be in the off state. If the VCC voltage rises to more than the hysteresis width (∆VLVSD), the low-voltage protection function is cancelled. 15. Power supply stabilization Since this IC is used in applications that flow the large output current, the power supply line is subject to fluctuations. Therefore, capacitors with capacitance adequate to stabilize the power supply voltage must be connected between the VCC pin and GND. If diodes are inserted in the power supply line to prevent the IC destruction due to reverse power supply connection, since this makes the power supply voltage even more subject to fluctuations, even larger capacitance will be required. 16. Ground lines The signal system GND and the output system GND must be separated, and connected to one GND at the connector. As the large current flows to the output system GND, this GND line must be made as short as possible. Output system GND : GND for Rf and VCC line capacitors Signal system GND : GND for the IC and external components 17. Integrating amplifier The integrating amplifier integrates the speed error pulses and phase error pulses and converts them to the speed command voltage. At that time it also sets the control loop gain and the frequency characteristics. External components of the integrating amplifier must be placed as close to the IC as possible to reduce influence of noise. 18. FG amplifier The FG amplifier normally makes up a filter amplifier to reject noise. Since a clamp circuit has been added at the FG amplifier output, the output amplitude is clamped at about 3.2Vp-p, even if the amplifier gain is increased. After the FG amplifier, the Schmitt comparator on one side hysteresis(200mV (typical)) is inserted. The Schmitt comparator output (FGS output) becomes high level when the FG amplifier output is lower than the FGIN+ voltage, and becomes low level when the FG amplifier output is higher to more than Schmitt width as compared with the FGIN+ voltage. Therefore, it is desirable that the amplifier gain be set so that the output amplitude is over 1.0Vp-p at the lowest controlled speed to be used. The capacitor connected between the FGIN+ pin and GND is required for bias voltage stabilization. This capacitor must be connected to the GND1 pin (pin 45) with a line that is as short as possible to reduce influence of noise. As the FG amplifier and the FGS output are operating even if the S/S pin is the stop state, it is possible to monitor the motor rotation by the FGS output. No.A1271-20/21 LV8105W SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of August, 2008. Specifications and information herein are subject to change without notice. PS No.A1271-21/21