MC10EL52D

MC10EL52, MC100EL52 5V ECL Differential Data and Clock D Flip‐Flop Description http://onsemi.com MARKING DIAGRAMS* 8 1 SOIC−8 D SUFFIX CASE 751 1 1 1 > 100 V Machine Model • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V • • • • • • • with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input Pulldown Resistors on D and CLK Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen: Index 28 to 34 Transistor Count = 48 devices Pb−Free Packages are Available KEL52 ALYW G 1 8 HL52 ALYWG G 4Y M G G • 365 ps Propagation Delay • 2.0 GHz Toggle Frequency • ESD Protection: > 1 kV Human Body Model, 8 HEL52 ALYW G 8 8 TSSOP−8 DT SUFFIX CASE 948R Features 8 1 4 1 KL52 ALYWG G 2N M G G The MC10EL/100EL52 is a differential data, differential clock D flip-flop with reset. The device is functionally equivalent to the E452 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E452, the EL52 is ideally suited for those applications which require the ultimate in AC performance. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EL52 allow the device to also be used as a negative edge triggered device. The EL52 employs input clamping circuitry so that under open input conditions (pulled down to VEE) the outputs of the device will remain stable. The 100 Series contains temperature compensation. 1 4 DFN8 MN SUFFIX CASE 506AA H = MC10 K = MC100 4Y = MC10 2N = MC100 A = Assembly Location L Y W M G = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2008 August, 2008 − Rev. 6 1 Publication Order Number: MC10EL52/D MC10EL52, MC100EL52 Table 1. TRUTH TABLE D 1 D 8 D 2 7 VCC Q D* CLK* Q L H Z Z L H Z = LOW to HIGH Transition * Pin will default low when left open. CLK CLK 3 6 4 5 Table 2. PIN DESCRIPTION Q PIN VEE Figure 1. Logic Diagram and Pinout Assignment FUNCTION D, D CLK, CLK Q, Q VCC VEE ECL Data Input ECL Clock Input ECL Data Output Positive Supply Negative Supply EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 8 V VEE NECL Mode Power Supply VCC = 0 V −8 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 8 SOIC 8 SOIC 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board 8 SOIC 41 to 44 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 8 TSSOP 8 TSSOP 185 140 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board 8 TSSOP 41 to 44 ± 5% °C/W Tsol Wave Solder