MC10EP451MNG

3.3 V/5 V ECL 6-Bit Differential Register with Master Reset MC10EP451, MC100EP451 Description The MC10/100EP451 is a 6−bit fully differential register with common clock and single−ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75 kW pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < VEE + 1.2 V, the clamp will override and force the output to a default state. When in the default state, and since the flip−flop is edge triggered, the output reaches a determined, but not predicted, valid state. The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW. The 100 Series contains temperature compensation. Features • • • • • • • • • 450 ps Typical Propagation Delay Maximum Frequency > 3.0 GHz Typical Asynchronous Master Reset 20 ps Skew Within Device, 35 ps Skew Device−To−Device PECL Mode Operating Range: VCC = 3.0 V to 5.5 V With VEE = 0 V NECL Mode Operating Range: VCC = 0 V With VEE = −3.0 V to −5.5 V Open Input Default State Safety Clamp on Inputs These Devices are Pb−Free and are RoHS Compliant www.onsemi.com 32 1 LQFP−32 FA SUFFIX CASE 561AB QFN32 MN SUFFIX CASE 488AM MARKING DIAGRAMS* 1 MCxx EP451 AWLYYWWG G MCxxx EP451 AWLYYWWG xxx A WL YY WW G or G = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Package Shipping† LQFP−32 250 Units / Tube MC10EP451FAG (Pb−Free) LQFP−32 250 Units / Tube MC100EP451FAG (Pb−Free) 2000 / MC100EP451FAR2G LQFP−32 Tape & Reel (Pb−Free) Device MC100EP451MNG QFN−32 (Pb−Free) MC100EP451MNR4G QFN−32 (Pb−Free) 72 Units / Tube 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2014 April, 2021 − Rev. 11 1 Publication Order Number: MC10EP451/D MC10EP451, MC100EP451 D4 24 D5 23 D5 22 Q5 Q5 VEE Q4 Q4 21 20 19 18 17 D1 D2 32 31 D2 MR VEE D3 D3 D4 30 26 25 29 28 27 D4 25 16 VCC D1 1 24 D4 D3 26 15 Q3 D0 2 23 D5 D3 27 14 Q3 D0 3 22 D5 VEE 28 13 VCC CLK 4 MR 29 12 Q2 CLK 5 D2 30 11 Q2 VCC 6 19 VEE D2 31 10 Q1 Q0 7 18 Q4 D1 32 9 Q1 Q0 8 17 Q4 MC10EP451 MC100EP451 1 D1 2 D0 3 4 5 6 7 D0 CLK CLK VCC Q0 21 Q5 MC10EP451 MC100EP451 8 9 10 11 12 13 14 Q1 Q1 Q2 Q2 VCC Q3 20 Q5 15 16 Q3 VCC Figure 2. QFN−32 Pinout (Top View) Q0 Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. D0 D0 Figure 1. LQFP−32 Pinout (Top View) Q D Q0 Q0 R Table 1. PIN DESCRIPTION PIN D1 D1 FUNCTION D [0:5]*, D [0:5]* ECL Differential Data Inputs MR* ECL Master Reset Input CLK*, CLK* ECL Differential Clock Inputs Q [0:5], Q [0:5] ECL Differential Data Outputs VCC Positive Supply VEE Negative Supply EP for QFN−32, only The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat− sinking conduit. The pad is electrically connected to VEE. Q D Q1 Q1 R D2 D2 Q D Q2 Q2 R D3 D3 Q D Q3 Q3 R D4 D4 * Pins will default LOW when left open. Q D Q4 Q4 R D5 D5 CLK CLK Q D Q5 R MR VEE Figure 3. Logic Diagram www.onsemi.com 2 Q5 MC10EP451, MC100EP451 Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb−Free Pkg LQFP−32 QFN−32 Level 2 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 919 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm LQFP−32 LQFP−32 80 55 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board LQFP−32 12 to 17 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm QFN−32 QFN−32 31 27 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P QFN−32 12 °C/W Tsol Wave Solder 265 °C Pb−Free VI v VCC VI w VEE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 3 MC10EP451, MC100EP451 Table 4. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2) −40°C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 80 95 125 80 95 125 80 95 125 mA Output HIGH Voltage (Note 3) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV VOL Output LOW Voltage (Note 3) 1365 1490 1615 1430 1555 1680 1470 1615 1740 mV VIH Input HIGH Voltage (Single−Ended) 2090 2415 2155 2480 2215 2540 mV VIL Input LOW Voltage (Single−Ended) 1365 1690 1430 1755 1490 1815 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) 2.0 3.3 2.0 3.3 2.0 3.3 V 150 mA Symbol Characteristic IEE Power Supply Current VOH IIH Input HIGH Current IIL Input LOW Current 150 150 0.5 0.5 0.5 mA Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 80 95 125 80 95 125 80 95 125 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 3) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV VOL Output LOW Voltage (Note 3) 3065 3190 3315 3130 3255 3380 3170 3315 3440 mV VIH Input HIGH Voltage (Single−Ended) 3790 4115 3855 4180 3915 4240 mV VIL Input LOW Voltage (Single−Ended) 3065 3390 3130 3455 3190 3515 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) 2.0 5.0 2.0 5.0 2.0 5.0 V 150 mA IIH Input HIGH Current IIL Input LOW Current 150 150 0.5 0.5 0.5 mA Table 6. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 6) −40°C Symbol IEE Characteristic Power Supply Current 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 80 95 125 80 95 125 80 95 125 mA VOH Output HIGH Voltage (Note 3) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV VOL Output LOW Voltage (Note 3) −1935 −1810 −1685 −1870 −1745 −1620 −1830 −1685 −1560 mV VIH Input HIGH Voltage (Single−Ended) −1210 −885 −1145 −820 −1085 −760 mV VIL Input LOW Voltage (Single−Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) 0.0 V 150 mA IIH Input HIGH Current IIL Input LOW Current VEE+2.0 0.0 VEE+2.0 150 0.5 0.0 VEE+2.0 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 3. All loading with 50 W to VCC − 2.0 V. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 6. Input and output parameters vary 1:1 with VCC. www.onsemi.com 4 MC10EP451, MC100EP451 Table 7. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 7) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 85 105 135 85 105 135 85 105 135 mA VOH Output HIGH Voltage (Note 8) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 8) 1305 1480 1605 1305 1480 1605 1305 1480 1605 mV VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single−Ended) 1305 1675 1305 1675 1305 1675 mV Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) 2.0 3.3 2.0 3.3 2.0 3.3 V 150 mA VIHCMR IIH Input HIGH Current IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 8. All loading with 50 W to VCC − 2.0 V. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 10) −40°C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 85 105 135 85 105 135 85 105 135 mA Output HIGH Voltage (Note 11) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV Output LOW Voltage (Note 11) 3005 3180 3305 3005 3180 3305 3005 3180 3305 mV VIH Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single−Ended) 3005 3375 3005 3375 3005 3375 mV Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 12) 2.0 5.0 2.0 5.0 2.0 5.0 V 150 mA Symbol Characteristic IEE Power Supply Current VOH VOL VIHCMR IIH Input HIGH Current IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 10. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 11. All loading with 50 W to VCC − 2.0 V. 12. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 5 MC10EP451, MC100EP451 Table 9. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 13) −40°C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 85 105 135 85 105 135 85 105 135 mA Output HIGH Voltage (Note 14) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 14) −1995 −1820 −1695 −1995 −1820 −1695 −1995 −1820 −1695 mV VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL Input LOW Voltage (Single−Ended) −1995 −1625 −1995 −1625 −1995 −1625 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 15) 0.0 V 150 mA Symbol Characteristic IEE Power Supply Current VOH IIH Input HIGH Current IIL Input LOW Current VEE+2.0 0.0 VEE+2.0 0.0 150 0.5 VEE+2.0 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 13. Input and output parameters vary 1:1 with VCC. 14. All loading with 50 W to VCC − 2.0 V. 15. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 10. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 16) −40°C Min Typ Output Voltage Amplitude @ 3 GHz (Figure 4) (Note 17) 540 670 Propagation Delay to Output Differential CLK to Q, Q MR to Q, Q 330 430 430 530 MR to CLK 240 D to CLK CLK to D 80 80 MR 400 Characteristic Symbol VOUTpp tPLH, tPHL tRR Reset Recovery tS tH Setup Time Hold Time tPW Minimum Pulse Rate 25°C Max Min Typ 520 650 350 450 450 550 145 250 40 40 80 80 530 630 85°C Max Min Typ 450 580 390 490 490 590 150 260 160 ps 40 40 80 80 40 40 ps 550 650 400 Max Unit mV 590 690 400 ps ps tSKEW Within−Device Skew (Note 18) Device−To−Device Skew (Note 19) 20 35 40 100 20 35 40 100 20 35 40 100 tJITTER CLOCK Random Jitter (RMS) @ v3.0 GHz (Figure 4) 0.2 1 0.2 1 0.2 1 ps 150 150 250 250 160 160 260 260 180 180 280 280 ps tr tf Output Rise/Fall Times (20% − 80%) Q, Q 100 100 110 110 130 130 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 16. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. 17. VOL and VOH specifications not guaranteed for Fmax testing. 18. Skew is measured between outputs under identical transitions and conditions on any one device. 19. Device−To−Device skew for identical transitions at identical VCC levels. www.onsemi.com 6 MC10EP451, MC100EP451 900 5V VOUTpp (mV) 800 3.3 V 700 600 500 400 300 200 100 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FREQUENCY (GHz) Figure 4. Fmax Typical Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 5. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1642/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN32 5x5, 0.5P CASE 488AM ISSUE A 1 32 SCALE 2:1 A D PIN ONE LOCATION ÉÉ ÉÉ NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L B DATE 23 OCT 2013 L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E DIM A A1 A3 b D D2 E E2 e K L L1 0.15 C 0.15 C EXPOSED Cu A DETAIL B 0.10 C (A3) A1 0.08 C DETAIL A 9 32X L ALTERNATE CONSTRUCTION GENERIC MARKING DIAGRAM* K D2 1 XXXXXXXX XXXXXXXX AWLYYWWG G 17 8 MOLD CMPD DETAIL B SEATING PLANE C SIDE VIEW NOTE 4 ÉÉ ÉÉ ÇÇ TOP VIEW MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.18 0.30 5.00 BSC 2.95 3.25 5.00 BSC 2.95 3.25 0.50 BSC 0.20 −−− 0.30 0.50 −−− 0.15 E2 1 32 25 e e/2 32X b 0.10 M C A B 0.05 M C BOTTOM VIEW XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 5.30 32X 0.63 3.35 3.35 5.30 0.50 PITCH 32X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON20032D QFN32 5x5 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS LQFP−32, 7x7 CASE 561AB−01 ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON30893E 32 LEAD LQFP, 7X7 DATE 19 JUN 2008 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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