MC33272A, MC33274A,
NCV33272A, NCV33274A
Operational Amplifiers,
Single Supply,
High Slew Rate,
Low Input Offset Voltage
The MC33272/74 series of monolithic operational amplifiers are
quality fabricated with innovative Bipolar design concepts. This dual
and quad operational amplifier series incorporates Bipolar inputs
along with a patented Zip−R−Trim element for input offset voltage
reduction. The MC33272/74 series of operational amplifiers exhibits
low input offset voltage and high gain bandwidth product. Dual
−doublet frequency compensation is used to increase the slew rate
while maintaining low input noise characteristics. Its all NPN output
stage exhibits no deadband crossover distortion, large output voltage
swing, and an excellent phase and gain margin. It also provides a low
open loop high frequency output impedance with symmetrical source
and sink AC frequency performance.
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8
PDIP−8
P SUFFIX
CASE 626
8
•
•
•
Input Offset Voltage Trimmed to 100 mV (Typ)
Low Input Bias Current: 300 nA
Low Input Offset Current: 3.0 nA
High Input Resistance: 16 MW
Low Noise: 18 nV/ √ Hz @ 1.0 kHz
High Gain Bandwidth Product: 24 MHz @ 100 kHz
High Slew Rate: 10 V/ms
Power Bandwidth: 160 kHz
Excellent Frequency Stability
Unity Gain Stable: w/Capacitance Loads to 500 pF
Large Output Voltage Swing: +14.1 V/ −14.6 V
Low Total Harmonic Distortion: 0.003%
Power Supply Drain Current: 2.15 mA per Amplifier
Single or Split Supply Operation: +3.0 V to +36 V or
±1.5 V to ±18 V
ESD Diodes Provide Added Protection to the Inputs
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
Pb−Free Packages are Available
MC33272AP
AWL
YYWWG
1
1
8
SOIC−8
D SUFFIX
CASE 751
8
1
33272
ALYWx
G
1
x = A for MC33272AD/DR2
= N for NCV33272ADR2
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MARKING
DIAGRAMS
DUAL
QUAD
14
PDIP−14
P SUFFIX
CASE 646
MC33274AP
AWLYYWWG
1
14
1
SOIC−14
D SUFFIX
CASE 751A
14
1
14
14
MC33274ADG
AWLYWW
1
NCV33274AG
AWLYWW
1
TSSOP−14
DTB SUFFIX
CASE 948G
14
1
14
14
NCV3
3274
ALYWG
G
MC33
274A
ALYWG
G
1
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 14
1
Publication Order Number:
MC33272A/D
MC33272A, MC33274A, NCV33272A, NCV33274A
PIN CONNECTIONS
DUAL
QUAD
CASE 626/751
CASE 646/751A/948G
Output 1
1
2
Inputs 1
VEE
3
8
7
+
+
4
6
VCC
Output 2
Output 1
1
14
2
13
Inputs 1
Inputs 2
3
5
VCC
(Top View)
1
4
+
Inputs 4
12
4
11
5
10
Inputs 2
6
Output 2
+
+
-
2
3
7
+
-
Output 4
9
8
VEE
Inputs 3
Output 3
(Top View)
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC to VEE
+36
V
Input Differential Voltage Range
VIDR
Note 1
V
Input Voltage Range
VIR
Note 1
V
Output Short Circuit Duration (Note 2)
tSC
Indefinite
sec
Maximum Junction Temperature
TJ
+150
°C
Storage Temperature
Tstg
−60 to +150
°C
Supply Voltage
ESD Protection at Any Pin
− Human Body Model
− Machine Model
Maximum Power Dissipation
Operating Temperature Range
MC33272A, MC33274A
NCV33272A, NCV33274A
Vesd
2000
200
V
PD
Note 2
mW
TA
−40 to +85
−40 to +125
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Either or both input voltages should not exceed VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2).
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2
MC33272A, MC33274A, NCV33272A, NCV33274A
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Figure
Symbol
Input Offset Voltage (RS = 10 W, VCM = 0 V, VO = 0 V)
(VCC = +15 V, VEE = −15 V)
TA = +25°C
TA = −40° to +85°C
TA = −40° to +125°C (NCV33272A)
TA = −40° to +125°C (NCV33274A)
(VCC = 5.0 V, VEE = 0)
TA = +25°C
3
|VIO|
Average Temperature Coefficient of Input Offset Voltage
RS = 10 W, VCM = 0 V, VO = 0 V, TA = −40° to +125°C
3
Input Bias Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = Tlow to Thigh
4, 5
Input Offset Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = Tlow to Thigh
6
Large Signal Voltage Gain (VO = 0 V to 10 V, RL = 2.0 kW)
TA = +25°C
TA = Tlow to Thigh
7
Max
Unit
mV
−
−
−
−
0.1
−
−
−
1.0
1.8
2.5
3.5
−
−
2.0
−
2.0
−
−
−
300
−
650
800
−
−
3.0
−
65
80
DVIO/DT
mV/°C
IIB
nA
nA
VICR
V
VEE to (VCC −1.8)
AVOL
dB
90
86
Output Voltage Swing (VID = ±1.0 V)
(VCC = +15 V, VEE = −15 V)
RL = 2.0 kW
RL = 2.0 kW
RL = 10 kW
RL = 10 kW
(VCC = 5.0 V, VEE = 0 V)
RL = 2.0 kW
RL = 2.0 kW
100
−
−
−
8, 9, 12
Power Supply Rejection
VCC/VEE = +15 V/ −15 V, +5.0 V/ −15 V, +15 V/ −5.0 V
V
VO +
VO −
VO +
VO −
13.4
−
13.4
−
13.9
−13.9
14
−14.7
−
−13.5
−
−14.1
VOL
VOH
−
3.7
−
−
0.2
5.0
13
CMR
80
100
−
14, 15
PSR
80
105
−
+25
−25
+37
−37
−
−
10, 11
Common Mode Rejection (Vin = +13.2 V to −15 V)
Output Short Circuit Current (VID = 1.0 V, Output to Ground)
Source
Sink
16
ISC
Power Supply Current Per Amplifier (VO = 0 V)
(VCC = +15 V, VEE = −15 V)
TA = +25°C
TA = Tlow to Thigh
(VCC = 5.0 V, VEE = 0 V)
TA = +25°C
17
ICC
Tlow = −40°C
Tlow = −40°C
Typ
|IIO|
Common Mode Input Voltage Range (DVIO = 5.0 mV, VO = 0 V)
TA = +25°C
3. MC33272A, MC33274A
NCV33272A, NCV33274A
Min
Thigh = +85°C
Thigh = +125°C
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3
dB
dB
mA
mA
−
−
2.15
−
2.75
3.0
−
−
2.75
MC33272A, MC33274A, NCV33272A, NCV33274A
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Figure
Symbol
Slew Rate
(Vin = −10 V to +10 V, RL = 2.0 kW, CL = 100 pF, AV = +1.0 V)
18, 33
SR
19
20, 21, 22
Gain Bandwidth Product (f = 100 kHz)
AC Voltage Gain (RL = 2.0 kW, VO = 0 V, f = 20 kHz)
Min
Typ
Max
Unit
V/ms
8.0
10
−
GBW
17
24
−
MHz
AVO
−
65
−
dB
BW
−
5.5
−
MHz
Unity Gain Bandwidth (Open Loop)
Gain Margin (RL = 2.0 kW, CL = 0 pF)
23, 24, 26
Am
−
12
−
dB
Phase Margin (RL = 2.0 kW, CL = 0 pF)
23, 25, 26
fm
−
55
−
Deg
27
CS
−
−120
−
dB
BWP
−
160
−
kHz
−
0.003
−
Channel Separation (f = 20 Hz to 20 kHz)
Power Bandwidth (VO = 20 Vpp, RL = 2.0 kW, THD ≤ 1.0%)
Total Harmonic Distortion
(RL = 2.0 kW, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0)
28
THD
Open Loop Output Impedance (VO = 0 V, f = 6.0 MHz)
29
%
|ZO|
−
35
−
W
Differential Input Resistance (VCM = 0 V)
Rin
−
16
−
MW
Differential Input Capacitance (VCM = 0 V)
Cin
−
3.0
−
pF
Equivalent Input Noise Voltage (RS = 100 W, f = 1.0 kHz)
30
en
−
18
−
nV/ √ Hz
Equivalent Input Noise Current (f = 1.0 kHz)
31
in
−
0.5
−
pA/ √ Hz
VCC
Vin
+
-
Vin
+
Sections
B
C
D
VO
+
VEE
Figure 1. Equivalent Circuit Schematic
(Each Amplifier)
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4
2400
5.0
V,
IO INPUT OFFSET VOLTAGE (mV)
P(MAX),
MAXIMUM POWER DISSIPATION (mW)
D
MC33272A, MC33274A, NCV33272A, NCV33274A
2000
MC33272P & MC33274P
1600
MC33274D
1200
800
MC33272D
400
0
-60 -40 -20
0
20
40
60
1.0
2
50
75
100
125
600
I
IB, INPUT BIAS CURRENT (nA)
150
VCC = +15 V
VEE = -15 V
TA = 25°C
-12
-8.0
-4.0
0
4.0
8.0
12
500
VCC = +15 V
VEE = -15 V
VCM = 0 V
400
300
200
100
0
-55
16
-25
0
25
50
75
VCM, COMMON MODE VOLTAGE (V)
TA, AMBIENT TEMPERATURE (°C)
Figure 4. Input Bias Current versus
Common Mode Voltage
Figure 5. Input Bias Current
versus Temperature
VCC
VCC
VCC -0.5
VCC -1.0
VCC -1.5
VCC -2.0
VCC = +5.0 V to +18 V
VEE = -5.0 V to -18 V
DVIO = 5.0 mV
VO = 0 V
VEE +1.0
VEE
-25
0
25
50
75
100
125
A,
VOL OPEN LOOP VOLTAGE GAIN (X 1.0 kV/V)
I
IB, INPUT BIAS CURRENT (nA)
V,
ICR INPUT COMMON MODE VOLTAGE RANGE (V)
25
Figure 3. Input Offset Voltage versus
Temperature for Typical Units
200
VEE
-55
0
Figure 2. Maximum Power Dissipation
versus Temperature
250
VEE +0.5
-25
TA, AMBIENT TEMPERATURE (°C)
300
0
-16
1. VIO > 0 @ 25°C
2. VIO = 0 @ 25°C
3. VIO < 0 @ 25°C
TA, AMBIENT TEMPERATURE (°C)
350
50
2
1
3
-3.0
-5.0
-55
80 100 120 140 160 180
3
1
-1.0
400
100
VCC = +15 V
VEE = -15 V
VCM = 0 V
3.0
100
125
100
125
180
160
140
120
100
-55
VCC = +15 V
VEE = -15 V
RL = 2.0 kW
f = 10 Hz
DVO = -10 V to +10 V
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 6. Input Common Mode Voltage
Range versus Temperature
Figure 7. Open Loop Voltage Gain
versus Temperature
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V sat , OUTPUT SATURATION VOLTAGE (V)
MC33272A, MC33274A, NCV33272A, NCV33274A
TA = 25°C
30
RL = 10 kW
20
10
0
V sat , OUTPUT SATURATION VOLTAGE (V)
RL = 2.0 kW
0
5.0
10
15
Source
VCC -1.0
TA = -55°C
TA = 125°C
VCC -2.0
TA = 25°C
VEE +2.0
Sink
VEE +1.0
TA = 125°C
TA = 25°C
TA = -55°C
VCC = +5.0 V to +18 V
VEE = -5.0 V to -18 V
VEE
20
0
5.0
10
15
20
VCC, VEE SUPPLY VOLTAGE (V)
IL, LOAD CURRENT (±mA)
Figure 8. Split Supply Output Voltage Swing
versus Supply Voltage
Figure 9. Split Supply Output Saturation
Voltage versus Load Current
VCC
TA = 125°C
VCC
VCC -4.0
VCC = +5.0 V to +18 V
RL to Gnd
VEE = Gnd
TA = 55°C
VCC -8.0
VCC -12
+0.2
TA = 125°C
TA = +25°C
TA = -55°C
+0.1
Gnd
0
100
1.0 k
10 k
100 k
8.0
TA = 25°C
4.0
TA = -55°C
TA = 125°C
VCC = +15 V
RL to VCC
VEE = Gnd
RFdbk = 100 kW
0
10
100
1.0 k
10 k
100 k
Figure 11. Single Supply Output Saturation
Voltage versus Load Resistance to VCC
CMR, COMMON MODE REJECTION (dB)
VCC = +15 V
VEE = -15 V
RL = 2.0 kW
AV = +1.0
THD = ≤1.0%
TA = 25°C
0
1.0 k
TA = 55°C
Figure 10. Single Supply Output Saturation
Voltage versus Load Resistance to Ground
16
4
TA = 25°C
14.2
RL, LOAD RESISTANCE TO VCC (W)
20
8
TA = 125°C
14.6
RL , LOAD RESISTANCE TO GROUND (kW)
24
12
15
1.0 M
28
VO, OUTPUT VOLTAGE (Vpp )
VCC
V sat , OUTPUT SATURATION VOLTAGE (V)
VO, OUTPUT VOLTAGE (Vpp )
40
120
100
TA = -55°C
TA = 125°C
80
60
VCC = +15 V
VEE = -15 V
VCM = 0 V
DVCM = ±1.5 V
ADM
DVCM
40
DVO
+
20
CMR = 20Log
DVCM
DVO
X ADM
0
10 k
100 k
1.0 M
1 0M
10
100
1.0 k
10 k
100 k
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 12. Output Voltage versus Frequency
Figure 13. Common Mode Rejection
versus Frequency
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1.0 M
MC33272A, MC33274A, NCV33272A, NCV33274A
100
80
TA = -55°C
60
VCC
ADM
+
40
DVO
VEE
20
DVO/ADM
DVCC
+PSR = 20Log
|I|,
SC OUTPUT SHORT CIRCUIT CURRENT (mA)
0
-PSR, POWER SUPPLY REJECTION (dB)
VCC = +15 V
VEE = -15 V
DVCC = ±1.5 V
TA = 125°C
10
100
1.0 k
10 k
100 k
DVCC = ±1.5 V
VCC = +15 V
VEE = -15 V
100
TA = -55°C
80
60
VCC
ADM
+
40
DVO
TA = 125°C
VEE
20
-PSR = 20Log
10
DVO/ADM
DVEE
100
1.0 k
10 k
100 k
1.0 M
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 14. Positive Power Supply Rejection
versus Frequency
Figure 15. Negative Power Supply Rejection
versus Frequency
11
60
VCC = +15 V
VEE = -15 V
VID = ±1.0 V
RL < 100 W
50
Sink
40
Source
Sink
30
Source
20
10
0
-55
-25
0
25
50
75
100
9.0
TA = +25°C
8.0
TA = -55°C
7.0
6.0
5.0
3.0
125
0
2.0
4.0
6.0
8.0
10
12
14
16
18
VCC, |VEE| , SUPPLY VOLTAGE (V)
Figure 16. Output Short Circuit Current
versus Temperature
Figure 17. Supply Current versus
Supply Voltage
GBW, GAIN BANDWIDTH PRODUCT (MHz)
DVin
+
VO
2.0kW
100 pF
1.0
VCC = +15 V
VEE = -15 V
DVin = 20 V
0.95
0.9
0.85
-55
TA = +125°C
TA, AMBIENT TEMPERATURE (°C)
1.1
1.05
10
4.0
1.15
SR, SLEW RATE (NORMALIZED)
120
0
1 .0 M
I,
CC SUPPLY CURRENT (mA)
+PSR, POWER SUPPLY REJECTION (dB)
120
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
50
VCC = +15 V
VEE = -15 V
f = 100 kHz
RL = 2.0 kW
CL = 0 pF
40
30
20
10
0
-55
Figure 18. Normalized Slew Rate
versus Temperature
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
Figure 19. Gain Bandwidth Product
versus Temperature
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20
125
100
20
100
120
140
Phase
5.0
160
0
180
-5.0
200
-15
220
240
1.0 M
280
100 M
10 M
-10 1A - Phase V = 18 V, V = -18 V
CC
EE
-15 2A - Phase VCC = 1.5 V, VEE = -1.5 V
1B - Gain VCC = 18 V, VEE = -18 V
-20 2B - Gain V = 1.5 V, V = -1.5 V
CC
EE
-25
100 k
1.0 M
220
2B
240
10 M
100 M
Figure 21. Gain and Phase
versus Frequency
12
100
140
1A
160
2A
0
180
VCC = +15 V
VEE = -15 V
-10 Vout = 0 V
TA = 25°C
1A - Phase (RL = 2.0 kW)
-20 2A - Phase (RL = 2.0 kW, CL = 300 pF)
1B - Gain (RL = 2.0 kW)
2B - Gain (RL = 2.0 kW, CL = 300 pF)
-30
3.0
4.0
6.0
8.0 10
200
1B
220
2B
240
260
280
20
200
1B
Figure 20. Voltage Gain and Phase
versus Frequency
10
180
2A
f, FREQUENCY (Hz)
120
0
Gain Margin
10
10
VCC = +15 V
VEE = -15 V
VO = 0 V
8.0
6.0
20
30
-
Vin
VO
+
2.0 kW
4.0
CL
40
2.0
50
Phase Margin
0
1.0
30
10
100
1000
f, FREQUENCY (MHz)
CL, OUTPUT LOAD CAPACITANCE (pF)
Figure 22. Open Loop Voltage Gain and
Phase versus Frequency
Figure 23. Open Loop Gain Margin and Phase
Margin versus Output Load Capacitance
12
60
CL = 10 pF
10
8.0
CL = 100 pF
6.0
CL = 300 pF
CL = 500 pF
4.0
2.0
0
-55
160
0
f, FREQUENCY (Hz)
20
140
5.0
φ m, PHASE MARGIN (DEGREES)
A,
VOL OPEN LOOP VOLTAGE GAIN (dB)
-25
100 k
120
1A
TA = 25°C
CL = 0 pF
10
-5.0
260
-20
A,
m OPEN LOOP GAIN MARGIN (dB)
15
A,
m OPEN LOOP GAIN MARGIN (dB)
-10
VCC = +15 V
VEE = -15 V
RL = 2.0 kW
TA = 25°C
φ EXCESS PHASE (DEGREES)
A V, VOLTAGE GAIN (dB)
10
80
VCC = +15 V
VEE = -15 V
-25
0
25
50
75
100
CL = 10 pF
50
CL = 100 pF
CL = 300 pF
40
30
CL = 500 pF
20
VCC = +15 V
VEE = -15 V
10
0
-55
125
-25
0
25
50
75
100
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 24. Open Loop Gain Margin
versus Temperature
Figure 25. Phase Margin versus Temperature
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φ m, PHASE MARGIN (DEGREES)
Gain
15
25
A V, VOLTAGE GAIN (dB)
20
80
φ, EXCESS PHASE (DEGREES)
25
φ, PHASE (DEGREES)
MC33272A, MC33274A, NCV33272A, NCV33274A
125
MC33272A, MC33274A, NCV33272A, NCV33274A
40
VCC = +15 V
VEE = -15 V
RT = R1+R2
VO = 0 V
TA = 25°C
3.0
0
Vin
+
R2
10
10
VO
100
0
10 k
1.0 k
e,
nV/ √ Hz )
n INPUT REFERRED NOISE VOLTAGE (
1.0 k
10 k
100 k
1.0 M
50
AV = +1000
AV = +1.0
100
1.0 k
VCC = +15 V
VEE = -15 V
10 k
VCC = +15 V
VEE = -15 V
VO = 0 V
TA = 25°C
40
30
AV = 1000
20
AV = 100
10
AV = 1.0
AV = 10
0
10 k
100 k
100 k
1.0 M
10 M
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 28. Total Harmonic Distortion
versus Frequency
Figure 29. Output Impedance versus Frequency
50
+
40
-
30
VO
Input Noise Voltage
Test Circuit
20
VCC = +15 V
VEE = -15 V
TA = 25°C
10
110
Figure 27. Channel Separation
versus Frequency
VO = 2.0 Vpp
TA = 25°C
0
120
Figure 26. Phase Margin and Gain Margin
versus Differential Source Resistance
AV = +10
10
130
f, FREQUENCY (Hz)
0.1
0.001
10
140
RT, DIFFERENTIAL SOURCE RESISTANCE (W)
AV = +100
0.01
Driver Channel
VCC = +15 V
VEE = -15 V
RL = 2.0 kW
DVOD = 20 Vpp
TA = 25°C
150
100
100
pA/ √ Hz )
i,
n INPUT REFERRED NOISE CURRENT (
THD, TOTAL HARMONIC DISTORTION (%)
20
R1
1.0
1.0
30
|Z|,
Ω
O OUTPUT IMPEDANCE ()
A,
m GAIN MARGIN (dB)
Phase Margin
9.0
CS, CHANNEL SEPERATION (dB)
50
12
6.0
160
60
Gain Margin
φ m , PHASE MARGIN (DEGREES)
15
100
1.0 k
f, FREQUENCY (Hz)
10 k
100 k
2.0
Input Noise Current Circuit
1.8
+
1.6
RS
1.4
-
1.2
(RS = 10 kW)
1.0
0.8
0.6
0.4
0.2
0
10
Figure 30. Input Referred Noise Voltage
versus Frequency
VCC = +15 V
VEE = -15 V
TA = 25°C
100
1.0 k
f, FREQUENCY (Hz)
10 k
Figure 31. Input Referred Noise Current
versus Frequency
http://onsemi.com
9
VO
100 k
MC33272A, MC33274A, NCV33272A, NCV33274A
PERCENT OVERSHOOT (%)
60
VCC = +15 V
VEE = -15 V
RL = 2.0 kW
TA = 25°C
50
40
30
20
10
0
10
100
CL, LOAD CAPACITANCE (pF)
1000
V,
O OUTPUT VOLTAGE (5.0 V/DIV)
V,
O OUTPUT VOLTAGE (5.0 V/DIV)
Figure 32. Percent Overshoot versus
Load Capacitance
VCC = +15 V
VEE = -15 V
AV = +1.0
RL = 2.0 kW
CL = 100 pF
TA = 25°C
t, TIME (2.0 ms/DIV)
VCC = +15 V
VEE = -15 V
AV = +1.0
RL = 2.0 kW
TA = 25°C
CL = f
t, TIME (2.0 ns/DIV)
Figure 33. Non−inverting Amplifier Slew Rate
for the MC33274
Figure 34. Non−inverting Amplifier Overshoot
for the MC33274
VCC = +15 V
VEE = -15 V
AV = +1.0
RL = 2.0 kW
CL = 300 pF
TA = 25°C
VCC = +15 V
VEE = -15 V
AV = +1.0
RL = 2.0 kW
CL = 300 pF
TA = 25°C
V,
O OUTPUT VOLTAGE (5.0 V/DIV)
V,
O OUTPUT VOLTAGE (50 mV/DIV)
CL = 100 pF
t, TIME (2.0 ms/DIV)
t, TIME (1.0 ms/DIV)
Figure 35. Small Signal Transient Response
for MC33274
Figure 36. Large Signal Transient Response
for MC33274
http://onsemi.com
10
MC33272A, MC33274A, NCV33272A, NCV33274A
ORDERING INFORMATION
Device
MC33272AD
Package
SOIC−8
MC33272ADG
SOIC−8
(Pb−Free)
MC33272ADR2
SOIC−8
MC33272ADR2G
MC33272AP
MC33272APG
NCV33272ADR2*
SOIC−8
(Pb−Free)
98 Units / Rail
2500 / Tape & Reel
PDIP−8
PDIP−8
(Pb−Free)
50 Units / Rail
SOIC−8
NCV33272ADR2G*
SOIC−8
(Pb−Free)
MC33274AD
SOIC−14
MC33274ADG
SOIC−14
(Pb−Free)
MC33274ADR2
SOIC−14
MC33274ADR2G
SOIC−14
(Pb−Free)
MC33274ADTBR2G
Shipping†
2500 / Tape & Reel
55 Units / Rail
2500 / Tape & Reel
TSSOP−14
(Pb−Free)
MC33274AP
PDIP−14
MC33274APG
PDIP−14
(Pb−Free)
NCV33274AD*
SOIC−14
NCV33274ADG*
SOIC−14
(Pb−Free)
NCV33274ADR2*
SOIC−14
NCV33274ADR2G*
SOIC−14
(Pb−Free)
NCV33274ADTBR2G*
TSSOP−14
(Pb−Free)
25 Units / Rail
55 Units / Rail
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
http://onsemi.com
11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE S
1
SCALE 1:1
D
A
14
8
E
H
E1
1
NOTE 8
7
b2
c
B
TOP VIEW
END VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
NOTE 3
L
SEATING
PLANE
A1
C
D1
e
M
eB
END VIEW
14X b
SIDE VIEW
0.010
M
C A
M
B
M
NOTE 6
DATE 22 APR 2015
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.735 0.775
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
18.67 19.69
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
GENERIC
MARKING DIAGRAM*
14
XXXXXXXXXXXX
XXXXXXXXXXXX
AWLYYWWG
STYLES ON PAGE 2
1
XXXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42428B
PDIP−14
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
PDIP−14
CASE 646−06
ISSUE S
DATE 22 APR 2015
STYLE 1:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO
CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO
CONNECTION
12. EMITTER
13. BASE
14. COLLECTOR
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
PIN 1. DRAIN
2. SOURCE
3. GATE
4. NO
CONNECTION
5. GATE
6. SOURCE
7. DRAIN
8. DRAIN
9. SOURCE
10. GATE
11. NO
CONNECTION
12. GATE
13. SOURCE
14. DRAIN
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. NO CONNECTION
5. SOURCE
6. DRAIN
7. GATE
8. GATE
9. DRAIN
10. SOURCE
11. NO CONNECTION
12. SOURCE
13. DRAIN
14. GATE
STYLE 6:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 7:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON
CATHODE
STYLE 8:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 9:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
STYLE 10:
PIN 1. COMMON
CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON
CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 11:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 12:
PIN 1. COMMON CATHODE
2. COMMON ANODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. COMMON ANODE
7. COMMON CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. ANODE/CATHODE
14. ANODE/CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42428B
PDIP−14
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
G
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
98ASH70246A
DESCRIPTION:
TSSOP−14 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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