MC74VHCT139A
Dual 2-to-4 Decoder/
Demultiplexer
The MC74VHCT139A is an advanced high speed CMOS 2−to−4
decoder/demultiplexer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar
Schottky TTL devices while maintaining CMOS low power
dissipation.
When the device is enabled (E = low), it can be used for gating or as
a data input for demultiplexing operations. When the enable input is
held high, all four outputs are fixed high, independent of other inputs.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device output is compatible with TTL−type input thresholds
and the output has a full 5.0 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3.0 V CMOS logic to 5.0 V CMOS logic, or from 1.8 V CMOS logic
to 3.0 V CMOS logic while operating at the high−voltage power
supply
The MC74VHCT139A input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHCT139A to be used to interface 5.0 V circuits to
3.0 V circuits. The output structures also provide protection when
VCC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage−input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
•
•
•
•
•
•
•
•
•
•
•
•
High Speed: tPD = 5.0 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 4 mΑ (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 100 FETs or 25 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 6
1
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MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
1
VHCT139AG
AWLYWW
1
16
VHCT
139A
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
1
1
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Outputs
E
A1
A0
Y0
Y1 Y2
Y3
H
L
L
L
L
X
L
L
H
H
X
L
H
L
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
L
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
MC74VHCT139A/D
MC74VHCT139A
ADDRESS
INPUTS
A0a
A1a
2
4
3
5
6
Ea
1
16
VCC
A0a
2
15
Eb
A1a
3
14
A0b
Y0a
4
13
A1b
Y1a
5
12
Y0b
Y2a
6
11
Y1b
Y3a
7
10
Y2b
GND
8
9
Y3b
7
Y1a
Y2a
ACTIVE-LOW
OUTPUTS
Y3a
1
Ea
ADDRESS
INPUTS
Y0a
A0b
A1b
14
12
13
11
10
9
Figure 1. Pin Assignment
Eb
Y0b
Y1b
Y2b
ACTIVE-LOW
OUTPUTS
Y3b
15
Figure 2. Logic Diagram
En
Y0
Y1
A0
Y2
Y3
A1
Figure 3. Expanded Logic Diagram
(1/2 of Device)
X/Y
A1a
3
A0a
2
2
1
Ea
1
EN
2
1
0
3
INPUT
4 Y0a
5 Y1a
A1a
3
A0a
2
6 Y2a
7 Y3a
Ea
1
0
1
Eb 15
2
6 Y2a
7 Y3a
12 Y0b
10 Y2b
10 Y2b
9 Y3b
Eb 15
9 Y3b
Figure 5. IEC Logic Diagram
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2
A1b 13
A0b 14
11 Y1b
Figure 4. Input Equivalent Circuit
4 Y0a
5 Y1a
3
12 Y0b
A1b 13
A0b 14
DMUX
0
0
G
3
1
11 Y1b
MC74VHCT139A
MAXIMUM RATINGS
Symbol
Value
Unit
VCC
Positive DC Supply Voltage
−0.5 to +7.0
V
VIN
Digital Input Voltage
−0.5 to +7.0
V
VOUT
DC Output Voltage
−0.5 to +7.0
−0.5 to VCC +0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
$20
mA
IOUT
DC Output Current, per Pin
$25
mA
ICC
DC Supply Current, VCC and GND Pins
PD
Power Dissipation in Still Air
TSTG
Storage Temperature Range
VESD
ESD Withstand Voltage
ILATCHUP
qJA
Parameter
Output in 3−State
High or Low State
SOIC
TSSOP
Latchup Performance
$75
mA
200
180
mW
−65 to +150
°C
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
>2000
>200
>2000
V
Above VCC and Below GND at 125°C (Note 4)
$300
mA
143
164
°C/W
Thermal Resistance, Junction−to−Ambient
SOIC
TSSOP
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
Max
Unit
4.5
5.5
V
DC Input Voltage
0
5.5
V
DC Output Voltage Output in 3−State
High or Low State
0
0
5.5
VCC
V
−55
125
°C
0
20
ns/V
VCC
DC Supply Voltage
VIN
VOUT
TA
Operating Temperature Range, all Package Types
tr, tf
Input Rise or Fall Time
VCC = 5.0 V + 0.5 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80 ° C
117.8
TJ = 90 ° C
1,032,200
TJ = 100 ° C
80
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 110° C
Time, Years
TJ = 120° C
Time, Hours
TJ = 130 ° C
Junction
Temperature °C
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS TIME
TO 0.1% BOND FAILURES
1
1
10
100
1000
TIME, YEARS
Figure 6. Failure Rate vs. Time Junction Temperature
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3
MC74VHCT139A
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
(V)
Min
VIH
Minimum High−Level Input
Voltage
4.5 to 5.5
2
VIL
Maximum Low−Level Input
Voltage
4.5 to 5.5
VOH
Maximum High−Level
Output Voltage
VOL
Maximum Low−Level
Output Voltage
Condition
TA ≤ 85°C
TA = 25°C
Typ
Max
Min
Max
2
0.8
VIN = VIH or VIL
IOH = −50 mA
4.5
4.4
VIN = VIH or VIL
IOH = −8 mA
4.5
3.94
VIN = VIH or VIL
IOL = 50 mA
4.5
VIN = VIH or VIL
IOH = 8 mA
TA = − 55 to
125°C
Min
Max
2
0.8
Unit
V
0.8
V
V
4.5
4.4
4.4
3.8
3.66
V
0
0.1
0.1
0.1
4.5
0.36
0.44
0.52
IIN
Input Leakage Current
VIN = 5.5 V or GND
0 to 5.5
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
4.0
40.0
40.0
mA
ICCT
Additional Quiescent
Supply Current (per Pin)
Any one input:
VIN = 3.4 V
All other inputs:
VIN = VCC or GND
5.5
1.35
1.5
1.5
mA
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
IOPD
Output Leakage Current
VOUT = 5.5 V
0
0.5
5
5
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA ≤ 85°C
TA = 25°C
Symbol
tPLH,
tPHL
tPLH,
tPHL
CIN
Parameter
Maximum Propagation
Delay, A to Y
Maximum Propagation
Delay, E to Y
Test Conditions
Min
TA = − 55 to
125°C
Typ
Max
Min
Max
Min
Max
Unit
ns
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
7.2
9.7
11.0
14.5
1.0
1.0
13.0
16.5
1.0
1.0
13.0
16.5
VCC = 5.0 ± 0.5 V
CL = 15 pF
CL = 50 pF
5.0
6.5
7.2
9.2
1.0
1.0
8.5
10.5
1.0
1.0
8.5
10.5
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
6.4
8.9
9.2
12.7
1.0
1.0
11.0
14.5
1.0
1.0
11.0
14.5
VCC = 5.0 ± 0.5 V
CL = 15 pF
CL = 50 pF
4.4
5.9
6.3
8.3
1.0
1.0
7.5
9.5
1.0
1.0
7.5
9.5
4
10
Maximum Input
Capacitance
10
10
ns
pF
Typical @ 25°C, VCC = 5.0V
CPD
26
Power Dissipation Capacitance (Note 5)
pF
5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/2 (per decoder). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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4
MC74VHCT139A
3.0 V
A
3.0 V
E
1.5 V
GND
1.5 V
GND
tPHL
tPLH
tPHL
tPLH
VOH
Y
VOH
1.5 V
1.5 V
Y
VOL
VOL
Figure 7. Switching Waveform
Figure 8. Switching Waveform
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
Figure 9. Test Circuit
ORDERING INFORMATION
Package
Shipping†
MC74VHCT139ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74VHCT139ADR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74VHCT139ADTG
TSSOP−16
(Pb−Free)
96 Units / Rail
MC74VHCT139ADTRG
TSSOP−16
(Pb−Free)
2500 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR, DYE #1
BASE, #1
EMITTER, #1
COLLECTOR, #1
COLLECTOR, #2
BASE, #2
EMITTER, #2
COLLECTOR, #2
COLLECTOR, #3
BASE, #3
EMITTER, #3
COLLECTOR, #3
COLLECTOR, #4
BASE, #4
EMITTER, #4
COLLECTOR, #4
STYLE 4:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
STYLE 5:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
DRAIN, DYE #1
DRAIN, #1
DRAIN, #2
DRAIN, #2
DRAIN, #3
DRAIN, #3
DRAIN, #4
DRAIN, #4
GATE, #4
SOURCE, #4
GATE, #3
SOURCE, #3
GATE, #2
SOURCE, #2
GATE, #1
SOURCE, #1
STYLE 6:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
STYLE 7:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
SOURCE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE P‐CH
SOURCE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE N‐CH
COLLECTOR, DYE #1
COLLECTOR, #1
COLLECTOR, #2
COLLECTOR, #2
COLLECTOR, #3
COLLECTOR, #3
COLLECTOR, #4
COLLECTOR, #4
BASE, #4
EMITTER, #4
BASE, #3
EMITTER, #3
BASE, #2
EMITTER, #2
BASE, #1
EMITTER, #1
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
S
V
S
K
S
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
N
8
1
0.25 (0.010)
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
0.65
PITCH
16X
0.36
DOCUMENT NUMBER:
DESCRIPTION:
16X
1.26
98ASH70247A
TSSOP−16
DIMENSIONS: MILLIMETERS
XXXX
A
L
Y
W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
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