MJE13009G
Switch-mode Series
NPN Silicon Power
Transistors
The MJE13009G is designed for high−voltage, high−speed power
switching inductive circuits where fall time is critical. They are
particularly suited for 115 and 220 V switch-mode applications
such
as
Switching
Regulators,
Inverters,
Motor
Controls, Solenoid/Relay drivers and Deflection circuits.
Features
• VCEO(sus) 400 V and 300 V
• Reverse Bias SOA with Inductive Loads @ TC = 100_C
• Inductive Switching Matrix 3 to 12 Amp, 25 and 100_C tc @ 8 A,
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12 AMPERE
NPN SILICON
POWER TRANSISTOR
400 VOLTS − 100 WATTS
100_C is 120 ns (Typ)
• 700 V Blocking Capability
• SOA and Switching Applications Information
• These Devices are Pb−Free and are RoHS Compliant*
TO−220AB
CASE 221A−09
STYLE 1
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Collector−Emitter Voltage
VCEO(sus)
400
Vdc
Collector−Emitter Voltage
VCEV
700
Vdc
Emitter−Base Voltage
VEBO
9
Vdc
Collector Current
− Continuous
− Peak (Note 1)
IC
ICM
12
24
Adc
Base Current
− Continuous
− Peak (Note 1)
IB
IBM
6
12
Adc
Emitter Current
− Continuous
− Peak (Note 1)
IE
IEM
18
36
Adc
Total Device Dissipation @ TA = 25_C
Derate above 25°C
PD
2
0.016
W
W/_C
Total Device Dissipation @ TC = 25_C
Derate above 25°C
PD
100
0.8
W
W/_C
TJ, Tstg
−65 to
+150
_C
Symbol
Max
Unit
Thermal Resistance, Junction−to−Ambient
RqJA
62.5
_C/W
Thermal Resistance, Junction−to−Case
RqJC
1.25
_C/W
TL
275
_C
Operating and Storage Junction
Temperature Range
1
Maximum Lead Temperature for Soldering
Purposes 1/8″ from Case for 5 Seconds
3
MARKING DIAGRAM
MJE13009G
AY WW
A
Y
WW
G
THERMAL CHARACTERISTICS
Characteristics
2
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Pulse Test: Pulse Width = 5 ms, Duty Cycle ≤ 10%.
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
MJE13009G
Package
Shipping
TO−220
(Pb−Free)
50 Units / Rail
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 10
1
Publication Order Number:
MJE13009/D
MJE13009G
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ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
VCEO(sus)
400
−
−
Vdc
−
−
−
−
1
5
−
−
1
OFF CHARACTERISTICS (Note 2)
Collector−Emitter Sustaining Voltage
(IC = 10 mA, IB = 0)
Collector Cutoff Current
(VCEV = Rated Value, VBE(off) = 1.5 Vdc)
(VCEV = Rated Value, VBE(off) = 1.5 Vdc, TC = 100_C)
ICEV
Emitter Cutoff Current
(VEB = 9 Vdc, IC = 0)
IEBO
mAdc
mAdc
SECOND BREAKDOWN
Second Breakdown Collector Current with base forward biased
Clamped Inductive SOA with Base Reverse Biased
IS/b
−
See Figure 1
See Figure 2
ON CHARACTERISTICS (Note 2)
DC Current Gain
(IC = 5 Adc, VCE = 5 Vdc)
(IC = 8 Adc, VCE = 5 Vdc)
hFE
8
6
−
−
40
30
−
−
−
−
−
−
−
−
1
1.5
3
2
−
−
−
−
−
−
1.2
1.6
1.5
fT
4
−
−
MHz
Cob
−
180
−
pF
td
−
0.06
0.1
ms
tr
−
0.45
1
ms
ts
−
1.3
3
ms
tf
−
0.2
0.7
ms
tsv
−
0.92
2.3
ms
tc
−
0.12
0.7
ms
Collector−Emitter Saturation Voltage
(IC = 5 Adc, IB = 1 Adc)
(IC = 8 Adc, IB = 1.6 Adc)
(IC = 12 Adc, IB = 3 Adc)
(IC = 8 Adc, IB = 1.6 Adc, TC = 100_C)
VCE(sat)
Base−Emitter Saturation Voltage
(IC = 5 Adc, IB = 1 Adc)
(IC = 8 Adc, IB = 1.6 Adc)
(IC = 8 Adc, IB = 1.6 Adc, TC = 100_C)
VBE(sat)
Vdc
Vdc
DYNAMIC CHARACTERISTICS
Current−Gain − Bandwidth Product
(IC = 500 mAdc, VCE = 10 Vdc, f = 1 MHz)
Output Capacitance
(VCB = 10 Vdc, IE = 0, f = 0.1 MHz)
SWITCHING CHARACTERISTICS
Resistive Load (Table 1)
Delay Time
Rise Time
Storage Time
(VCC = 125 Vdc, IC = 8 A,
IB1 = IB2 = 1.6 A, tp = 25 ms,
Duty Cycle v 1%)
Fall Time
Inductive Load, Clamped (Table 1, Figure 13)
Voltage Storage Time
Crossover Time
(IC = 8 A, Vclamp = 300 Vdc,
IB1 = 1.6 A, VBE(off) = 5 Vdc, TC = 100_C)
2. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
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2
MJE13009G
14
10m
σ
20
10
5
2
1
0.5
TC = 25°C
100m
σ
1m
s
dc
12
IC, COLLECTOR (AMP)
IC, COLLECTOR CURRENT (AMP)
100
50
THERMAL LIMIT
BONDING WIRE LIMIT
SECOND BREAKDOWN LIM
CURVES
IT APPLY BELOW RATED
VCEO
0.2
0.1
0.05
0.02
0.01
10
TC ≤ 100°C
IB1 = 2.5 A
8
6
VBE(off) = 9 V
4
5V
2
3V
0
5
7
10
50 70 100
20 30
200 300
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
0
500
100
200
300
1.5
400 V 500
600
700
800
VCEV, COLLECTOR-EMITTER CLAMP VOLTAGE (VOLTS)
Figure 1. Forward Bias Safe Operating Area
Figure 2. Reverse Bias Switching Safe
Operating Area
The Safe Operating Area figures shown in Figures 1 and 2 are specified ratings for these devices under the test conditions shown.
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate IC − VCE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 1 is based on TC = 25_C; TJ(pk) is
variable depending on power level. Second breakdown
pulse limits are valid for duty cycles to 10% but must be
derated when TC ≥ 25_C. Second breakdown limitations do
not derate the same as thermal limitations. Allowable
current at the voltages shown on Figure 1 may be found at
any case temperature by using the appropriate curve on
Figure 3.
TJ(pk) may be calculated from the data in Figure 4. At high
case temperatures, thermal limitations will reduce the power
that can be handled to values less than the limitations
imposed by second breakdown. Use of reverse biased safe
operating area data (Figure 2) is discussed in the applications
information section.
POWER DERATING FACTOR
1
SECOND BREAK
DOWN DERATING
0.8
0.6
THERMAL
DERATING
0.4
0.2
0
20
40
60
80
100
140
120
160
TC, CASE TEMPERATURE (°C)
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
Figure 3. Forward Bias Power Derating
1
0.7
0.5
D = 0.5
0.3
0.2
0.2
0.1
0.1
0.07
0.05
0.02
0.03
0.02
0.01
SINGLE PULSE
0.01
0.01
0.02
0.05
0.1
P(pk)
ZqJC(t) = r(t) RqJC
RqJC = 1.25°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TC = P(pk) ZqJC(t)
0.05
0.2
0.5
1
2
5
10
20
t, TIME (ms)
Figure 4. Typical Thermal Response [ZqJC(t)]
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3
t1
t2
DUTY CYCLE, D = t1/t2
50
100
200
500
1.0 k
MJE13009G
30
VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS)
hFE , DC CURRENT GAIN
50
TJ = 150°C
20
25°C
55°C
10
7
VCE = 5 V
5
0.2
0.3
3
0.5 0.7 1
5
7
2
IC, COLLECTOR CURRENT (AMP)
10
20
2
1.6
5A
8A
12 A
0.8
0.4
TJ = 25°C
0
0.05 0.07 0.1
Figure 5. DC Current Gain
0.2 0.3
0.5 0.7 1
IB, BASE CURRENT (AMP)
2
3
5
Figure 6. Collector Saturation Region
0.7
1.4
0.6
IC/IB = 3
V, VOLTAGE (VOLTS)
IC/IB = 3
1.2
V, VOLTAGE (VOLTS)
3A
IC = 1 A
1.2
TJ = -55°C
1
0.8
25°C
150°C
TJ = 150°C
0.5
0.4
- 55°C
0.3
0.2
25°C
0.6
0.1
0.4
0
0.2 0.3
0.5 0.7
1
2
3
5
7
20
10
0.2 0.3
3
5
7
10
Figure 8. Collector−Emitter Saturation
Voltage
20
4K
Cib
2K
1K
C, CAPACITANCE (pF)
IC, COLLECTOR CURRENT (A)
μ
2
Figure 7. Base−Emitter Saturation Voltage
VCE = 250 V
TJ = 150°C
125°C
100°C
10
75°C
50°C
1
REVERSE
FORWARD
+0.2
+0.4
0
-0.2
VBE, BASE-EMITTER VOLTAGE (VOLTS)
+0.6
TJ = 25°C
1K
800
600
400
Cob
200
100
80
60
40
25°C
0.1
-0.4
1
IC, COLLECTOR CURRENT (AMP)
10K
100
0.5 0.7
IC, COLLECTOR CURRENT (AMP)
0.1
Figure 9. Collector Cutoff Region
100
0.2 0.5 1 2 5 10 20 50
VR, REVERSE VOLTAGE (VOLTS)
Figure 10. Capacitance
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4
200
500
MJE13009G
Table 1. Test Conditions for Dynamic Performance
RESISTIVE
SWITCHING
REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING
+5 V
VCC
33
1N4933
+125 V
MJE210
TEST CIRCUITS
0.001 mF
L
RC
5V
2N2222
PW
DUTY CYCLE ≤ 10%
tr, tf ≤ 10 ns
1
k
68
IC
RB
1
+5 Vk
1N4933
MR826*
33 1N4933
Vclamp
*SELECTED FOR ≥ 1 kV
5.1 k
VCE
51
IB
TEST WAVEFORMS
CIRCUIT
VALUES
NOTE
PW and VCC Adjusted for Desired IC
RB Adjusted for Desired IB1
Coil Data:
Ferroxcube Core #6656
Full Bobbin (~16 Turns) #16
IC
ICM
t1
VCE
TIME
Vclamp
D1
-4.0
V
MJE200
47 100
1/2 W
- VBE(off)
GAP for 200 mH/20 A
Lcoil = 200 mH
OUTPUT WAVEFORMS
tf CLAMPED
tf UNCLAMPED ≈ t2
t1 ADJUSTED TO
OBTAIN IC
t
Lcoil (ICM)
tf
t1 ≈
VCC
VCEM
SCOPE
RB
D.U.T.
1k
2N2905
0.02 mF 270
TUT
t2 ≈
Lcoil (ICM)
Vclamp
t2
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5
VCC = 20 V
Vclamp = 300 Vdc
VCC = 125 V
RC = 15 W
D1 = 1N5820 or Equiv.
RB = W
+10 V
Test Equipment
Scope−Tektronics
475 or Equivalent
25 ms
0
-8 V
tr, tf < 10 ns
Duty Cycle = 1.0%
RB and RC adjusted
for desired IB and IC
MJE13009G
APPLICATIONS INFORMATION FOR SWITCH-MODE SPECIFICATIONS
INTRODUCTION
the output rectifiers, however, the voltage induced in the
primary leakage inductance is not clamped by these diodes
and could be large enough to destroy the device. A snubber
network or an additional clamp may be required to keep the
turn−off load line within the Reverse Bias SOA curve.
Load lines that fall within the pulsed forward biased SOA
curve during turn−on and within the reverse bias SOA curve
during turn−off are considered safe, with the following
assumptions:
1. The device thermal limitations are not exceeded.
2. The turn−on time does not exceed 10 ms (see standard
pulsed forward SOA curves in Figure 1).
3. The base drive conditions are within the specified
limits shown on the Reverse Bias SOA curve
(Figure 2).
The primary considerations when selecting a power
transistor for switch-mode applications are voltage and
current ratings, switching speed, and energy handling
capability. In this section, these specifications will be
discussed and related to the circuit examples illustrated in
Table 2. (Note 3)
VOLTAGE REQUIREMENTS
Both blocking voltage and sustaining voltage are
important in switch-mode applications.
Circuits B and C in Table 2 illustrate applications that
require high blocking voltage capability. In both circuits the
switching transistor is subjected to voltages substantially
higher than VCC after the device is completely off (see load
line diagrams at IC = Ileakage ≈ 0 in Table 2). The blocking
capability at this point depends on the base to emitter
conditions and the device junction temperature. Since the
highest device capability occurs when the base to emitter
junction is reverse biased (VCEV), this is the recommended
and specified use condition. Maximum ICEV at rated VCEV
is specified at a relatively low reverse bias (1.5 V) both at
25°C and 100_C. Increasing the reverse bias will give some
improvement in device blocking capability.
The sustaining or active region voltage requirements in
switching applications occur during turn−on and turn−off. If
the load contains a significant capacitive component, high
current and voltage can exist simultaneously during turn−on
and the pulsed forward bias SOA curves (Figure 1) are the
proper design limits.
For inductive loads, high voltage and current must be
sustained simultaneously during turn−off, in most cases,
with the base to emitter junction reverse biased. Under these
conditions the collector voltage must be held to a safe level
at or below a specific value of collector current. This can be
accomplished by several means such as active clamping, RC
snubbing, load line shaping, etc. The safe level for these
devices is specified as a Reverse Bias Safe Operating Area
(Figure 2) which represents voltage−current conditions that
can be sustained during reverse biased turn−off. This rating
is verified under clamped conditions so that the device is
never subjected to an avalanche mode.
CURRENT REQUIREMENTS
An efficient switching transistor must operate at the
required current level with good fall time, high energy
handling capability and low saturation voltage. On this data
sheet, these parameters have been specified at 8 amperes
which represents typical design conditions for these devices.
The current drive requirements are usually dictated by the
VCE(sat) specification because the maximum saturation
voltage is specified at a forced gain condition which must be
duplicated or exceeded in the application to control the
saturation voltage.
SWITCHING REQUIREMENTS
In many switching applications, a major portion of the
transistor power dissipation occurs during the fall time (tfi ).
For this reason considerable effort is usually devoted to
reducing the fall time. The recommended way to accomplish
this is to reverse bias the base−emitter junction during
turn−off. The reverse biased switching characteristics for
inductive loads are discussed in Figure 11 and Table 3 and
resistive loads in Figures 13 and 14. Usually the inductive
load component will be the dominant factor in
switch-mode applications and the inductive switching
data will more closely represent the device performance in
actual application. The inductive switching characteristics
are derived from the same circuit used to specify the reverse
biased SOA curves, (See Table 1) providing correlation
between test procedures and actual use conditions.
In the four application examples (Table 2) load lines are
shown in relation to the pulsed forward and reverse biased
SOA curves.
In circuits A and D, inductive reactance is clamped by the
diodes shown. In circuits B and C the voltage is clamped by
3. For detailed information on specific switching applications, see
ON Semiconductor Application Notes AN−719, AN−767.
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6
MJE13009G
RESISTIVE SWITCHING PERFORMANCE
1K
2K
ts
VCC = 125 V
IC/IB = 5
TJ = 25°C
700
500
1K
t, TIME (ns)
200
tr
VCC = 125 V
IC/IB = 5
TJ = 25°C
500
300
200
100
td @ VBE(off) = 5 V
tf
50
0.2 0.3
2
3
5
7
0.5 0.7 1
IC, COLLECTOR CURRENT (AMP)
10
100
20
0.2
Figure 11. Turn−On Time
tsv
90% IB1
10%
VCEM
10
20
IC
Vclamp
tfi
VCE
tti
tc
Vclamp
IB
90% IC
trv
0.5 0.7 1
2
5
7
IC, COLLECTOR CURRENT (AMP)
Figure 12. Turn−Off Time
IC
90% VCEM
0.3
10%
ICM
VOLTAGE 50 V/DIV
70
CURRENT 2 A/DIV
t, TIME (ns)
700
300
2%
IC
IC
VCE
TIME
TIME 20 ns/DIV
Figure 13. Inductive Switching
Measurements
Figure 14. Typical Inductive Switching Waveforms
(at 300 V and 12 A with IB1 = 2.4 A and VBE(off) = 5 V)
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MJE13009G
Table 2. Applications Examples of Switching Circuits
CIRCUIT
LOAD LINE DIAGRAMS
SERIES SWITCHING
REGULATOR
Collector Current
A
VCC
TURN-ON (FORWARD BIAS) SOA
ton ≤ 10 ms
DUTY CYCLE ≤ 10%
24 A
VO
PD = 4000 W
TC = 100°C
TIME DIAGRAMS
IC
2
350 V
12 A
TURNON
TURN-OFF (REVERSE BIAS)
SOA
1.5 V ≤ VBE(off) ≤ 9.0 V
DUTY CYCLE ≤ 10%
TURNOFF
1
VCC 400 V
t
TIME
VCE
VCC
1
700 V
t
COLLECTOR VOLTAGE
RINGING CHOKE
INVERTER
B
TURN-ON (FORWARD BIAS) SOA
TURN-ON ton ≤ 10 ms
TURN-ON DUTY CYCLE ≤ 10%
PD = 4000 W 2
TC = 100°C
350 V
12 A
TURN-OFF (REVERSE BIAS) SOA
TURN-OFF 1.5 V ≤ VBE(off) ≤ 9.0 V
TURN-OFF
TURN-OFF DUTY CYCLE ≤ 10%
TURN-ON
24 A
Collector Current
VCC
TIME
VO
N
VCC
400 V
VCC + N(Vo)
PUSH−PULL
INVERTER/CONVERTER
700 V
1
VCC
Collector Current
VO
toff
ton
VCC+
N(Vo)
VCC
t
COLLECTOR VOLTAGE
TURN-ON (FORWARD BIAS) SOA
TURN-ON ton ≤ 10 ms
TURN-ON DUTY CYCLE ≤ 10%
PD = 4000 W 2
TC = 100°C
350 V
TURN-OFF (REVERSE BIAS) SOA
12 A
TURN-ON
TURN-OFF 1.5 V ≤ VBE(off) ≤ 9.0 V
TURN-OFF DUTY CYCLE ≤ 10%
TURN-OFF
IC
ton
400 V
t
2 VCC
VCC
700 V
1
toff
VCE
2 VCC
VCC
t
LEAKAGE
SPIKE
VCE
1
24 A
C
IC
1
t
COLLECTOR VOLTAGE
SOLENOID DRIVER
TURN-ON (FORWARD BIAS) SOA
TURN-ON ton ≤ 10 ms
TURN-ON DUTY CYCLE ≤ 10%
VCC
D
SOLENOID
Collector Current
24 A
PD = 4000 W 2
350 V
TURN-OFF (REVERSE BIAS) SOA
TURN-OFF 1.5 V ≤ VBE(off) ≤ 9.0 V
TURN-OFF DUTY CYCLE ≤ 10%
TURN-OFF
IC
TC = 100°C
12 A
ton
toff
t
VCE
VCC
TURN-ON
VCC
400 V
1
700 V
COLLECTOR VOLTAGE
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8
1
t
MJE13009G
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Table 3. Typical Inductive Switching Performance
IC
AMP
TC
_C
tsv
ns
trv
ns
tfi
ns
tti
ns
tc
ns
3
25
100
770
1000
100
230
150
160
200
200
240
320
5
25
100
630
820
72
100
26
55
10
30
100
180
8
25
100
720
920
55
70
27
50
2
8
77
120
12
25
100
640
800
20
32
17
24
2
4
41
54
NOTE: All Data recorded In the Inductive Switching Circuit In Table 1.
SWITCHING TIME NOTES
In resistive switching circuits, rise, fall, and storage times
have been defined and apply to both current and voltage
waveforms since they are in phase. However, for inductive
loads which are common switch-mode power
supplies and hammer drivers, current and voltage
waveforms are not in phase. Therefore, separate
measurements must be made on each waveform to
determine the total switching time. For this reason, the
following new terms have been defined.
tsv = Voltage Storage Time, 90% IB1 to 10% VCEM
trv = Voltage Rise Time, 10 −90% VCEM
tfi = Current Fall Time, 90−10% ICM
tti = Current Tail, 10−2% ICM
tc = Crossover Time, 10% VCEM to 10% ICM
An enlarged portion of the turn−off waveforms is shown
in Figure 13 to aid in the visual identity of these terms.
For the designer, there is minimal switching loss during
storage time and the predominant switching power losses
occur during the crossover interval and can be obtained
using the standard equation from AN222/D:
PSWT = 1/2 VCCIC(tc) f
Typical inductive switching waveforms are shown in
Figure 14. In general, trv + tfi ] tc. However, at lower test
currents this relationship may not be valid.
As is common with most switching transistors, resistive
switching is specified at 25_C and has become a benchmark
for designers. However, for designers of high frequency
converter circuits, the user oriented specifications which
make this a “switch-mode” transistor are the inductive
switching speeds (tc and tsv) which are guaranteed at 100_C.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−220
CASE 221A
ISSUE AK
DATE 13 JAN 2022
SCALE 1:1
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
BASE
EMITTER
COLLECTOR
EMITTER
STYLE 3:
PIN 1.
2.
3.
4.
CATHODE
ANODE
GATE
ANODE
STYLE 4:
PIN 1.
2.
3.
4.
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
MAIN TERMINAL 2
STYLE 5:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 6:
PIN 1.
2.
3.
4.
ANODE
CATHODE
ANODE
CATHODE
STYLE 7:
PIN 1.
2.
3.
4.
CATHODE
ANODE
CATHODE
ANODE
STYLE 8:
PIN 1.
2.
3.
4.
CATHODE
ANODE
EXTERNAL TRIP/DELAY
ANODE
STYLE 9:
PIN 1.
2.
3.
4.
GATE
COLLECTOR
EMITTER
COLLECTOR
STYLE 10:
PIN 1.
2.
3.
4.
GATE
SOURCE
DRAIN
SOURCE
STYLE 11:
PIN 1.
2.
3.
4.
DRAIN
SOURCE
GATE
SOURCE
STYLE 12:
PIN 1.
2.
3.
4.
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
NOT CONNECTED
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42148B
TO−220
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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