MT9V022IA7ATM

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Features 1/3-Inch Wide-VGA CMOS Digital Image Sensor MT9V022 For the latest data sheet revision, refer to Aptina’s Web site: www.aptina.com Features Table 1: • Aptina® DigitalClarity® CMOS imaging technology • Array format: Wide-VGA, active 752H x 480V (360,960 pixels) • Global shutter photodiode pixels; simultaneous integration and readout • Monochrome or color: Near_IR enhanced performance for use with non-visible NIR illumination • Readout modes: progressive or interlaced • Shutter efficiency: >99% • Simple two-wire serial interface • Register Lock capability • Window Size: User programmable to any smaller format (QVGA, CIF, QCIF, etc.). Data rate can be maintained independent of window size • Binning: 2 x 2 and 4 x 4 of the full resolution • ADC: On-chip, 10-bit column-parallel (option to operate in 12-bit to 10-bit companding mode) • Automatic Controls: Auto exposure control (AEC) and auto gain control (AGC); variable regional and variable weight AEC/AGC • Support for four unique serial control register IDs to control multiple imagers on the same bus • Data output formats: – Single sensor mode: 10-bit parallel/stand-alone 8-bit or 10-bit serial LVDS – Stereo sensor mode: Interspersed 8-bit serial LVDS Parameter 1/3-inch 4.51mm(H) x 2.88mm(V) 5.35mm diagonal 752H x 480V 6.0μm x 6.0μm Monochrome or color RGB Bayer pattern Global shutter—TrueSNAP™ 26.6 MPS/26.6 MHz Active pixels Pixel size Color filter array Shutter type Maximum data rate/ master clock Full resolution Frame rate ADC resolution Responsivity Dynamic range Supply voltage Power consumption Operating temperature Packaging 752 x 480 60 fps (at full resolution) 10-bit column-parallel 4.8 V/lux-sec (550nm) >55dB linear; >80dB−100dB in HiDy mode 3.3V +0.3V (all supplies) Exposure Time LED_OUT Exposure Time Vertical Blanking FRAME_VALID LINE_VALID DOUT(9:0) Figure 14: xxx xxx xxx Simultaneous Master Mode Synchronization Waveforms #2 Exposure Time > Readout Time LED_OUT Exposure Time Vertical Blanking FRAME_VALID LINE_VALID DOUT(9:0) PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN xxx xxx 20 xxx Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description When exposure time is greater than the sum of vertical blank and window height, the number of vertical blank rows is increased automatically to accommodate the exposure time. Sequential Master Mode In sequential master mode the exposure period is followed by readout. The frame synchronization waveforms for sequential master mode are shown in Figure 15. The frame rate changes as the integration time changes. Figure 15: Sequential Master Mode Synchronization Waveforms Exposure Time LED_OUT FRAME_VALID LINE_VALID DOUT(9:0) xxx xxx xxx Snapshot Mode In snapshot mode the sensor accepts an input trigger signal which initiates exposure, and is immediately followed by readout. Figure 16 shows the interface signals used in snapshot mode. In snapshot mode, the start of the integration period is determined by the externally applied EXPOSURE pulse that is input to the MT9V022. The integration time is preprogrammed via the two-wire serial interface on R0x0B. After the frame's integration period is complete the readout process commences and the syncs and data are output. Sensor in snapshot mode can capture a single image or a sequence of images. The frame rate may only be controlled by changing the period of the user supplied EXPOSURE pulse train. The frame synchronization waveforms for snapshot mode are shown in Figure 17. Figure 16: Snapshot Mode Interface Signals EXPOSURE SYSCLK PIXCLK CONTROLLER LINE_VALID FRAME_VALID MT9V022 DOUT(9:0) PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 21 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Figure 17: Snapshot Mode Frame Synchronization Waveforms EXPOSURE Exposure Time LED_OUT FRAME_VALID LINE_VALID DOUT(9:0) xxx xxx xxx Slave Mode In slave mode, the exposure and readout are controlled using the EXPOSURE, STFRM_OUT, and STLN_OUT pins. When the slave mode is enabled, STFRM_OUT and STLN_OUT become input pins. The start and end of integration are controlled by EXPOSURE and STFRM_OUT pulses, respectively. While a STFRM_OUT pulse is used to stop integration, it is also used to enable the readout process. After integration is stopped, the user provides STLN_OUT pulses to trigger row readout. A full row of data is read out with each STLN_OUT pulse. The user must provide enough time between successive STLN_OUT pulses to allow the complete readout of one row. It is also important to provide additional STLN_OUT pulses to allow the sensors to read the vertical blanking rows. It is recommended that the user program the vertical blank register (R0x06) with a value of 4, and achieve additional vertical blanking between frames by delaying the application of the STFRM_OUT pulse. The elapsed time between the rising edge of STLN_OUT and the first valid pixel data is [horizontal blanking register (R0x05) + 4] clock cycles. Figure 18: Slave Mode Operation 1-row time Exposure (input) STFRM_OUT 1-row time 2 master clocks (input) LED_OUT (output) STLN_OUT (input) LINE_V ALID (output) Integration T ime Vertical Blanking (def = 45 lines) PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 22 98 ma ster clocks Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Signal Path The MT9V022 signal path consists of a programmable gain, a programmable analog offset, and a 10-bit ADC. See “Black Level Calibration” on page 30 for the programmable offset operation description. Figure 19: Signal Path Gain Selection (R0x35 or result of AGC) VREF (R0x2C) Pixel Output (reset minus signal) Offset Correction Voltage (R0x48 or result of BLC) 10 (12) bit ADC ADC Data (9:0) C1 S C2 On-Chip Biases ADC Voltage Reference The ADC voltage reference is programmed through R0x2C, bits 2:0. The ADC reference ranges from 1.0V to 2.1V. The default value is 1.4V. The increment size of the voltage reference is 0.1V from 1.0V to 1.6V (R0x2C[2:0] values 0 to 6). At R0x2C[2:0] = 7, the reference voltage jumps to 2.1V. The effect of the ADC calibration does not scale with VREF. Instead it is a fixed value relative to the output of the analog gain stage. At default, one LSB of calibration equals two LSB in output data (1LSBOffset = 2mV, 1LSBADC = 1mV). It is very important to preserve the correct values of the other bits in R0x2C. The default register setting is 0x0004. V_Step Voltage Reference This voltage is used for pixel high dynamic range operations, programmable from R0x31 through R0x34. Chip Version Chip version registers R0x00 and R0xFF are read-only. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 23 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Window Control Registers R0x01 column start, R0x02 Row Start, R0x03 window height (row size), and R0x04 Window Width (column size) control the size and starting coordinates of the window. The values programmed in the window height and width registers are the exact window height and width out of the sensor. The window start value should never be set below four. To read out the dark rows set bit 6 of R0x0D. In addition, bit 7 of R0x0D can be used to display the dark columns in the image. Blanking Control Horizontal blanking and vertical blanking registers R0x05 and R0x06 respectively control the blanking time in a row (horizontal blanking) and between frames (vertical blanking). • Horizontal blanking is specified in terms of pixel clocks. • Vertical blanking is specified in terms of numbers of rows. The actual imager timing can be calculated using Table 4 on page 13 and Table 5 on page 14 which describe “Row Timing and FRAME_VALID/LINE_VALID signals.” The minimum number of vertical blank rows is 4. Pixel Integration Control Total Integration R0x0B Total Shutter Width (In Terms of Number of Rows) This register (along with the window width and horizontal blanking registers) controls the integration time for the pixels. The actual total integration time, tINT, is: tINT = (Number of rows of integration × row time) + Overhead, where: The number of rows integration is equal to the result of automatic exposure control (AEC) which may vary from frame to frame, or, if AEC is disabled, the value in R0x0B Row time = (R0x04 + R0x05) master clock periods Overhead = (R0x04 + R0x05 – 255) master clock periods Typically, the value of R0x0B (total shutter width) is limited to the number of rows per frame (which includes vertical blanking rows), such that the frame rate is not affected by the integration time. If R0x0B is increased beyond the total number of rows per frame, it is required to add additional blanking rows using R0x06 as needed. A second constraint is that tINT must be adjusted to avoid banding in the image from light flicker. Under 60Hz flicker, this means frame time must be a multiple of 1/120 of a second. Under 50Hz flicker, frame time must be a multiple of 1/100 of a second. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 24 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Changes to Integration Time With automatic exposure control disabled (R0xAF, bit 0 is cleared to LOW), and if the total integration time (R0x0B) is changed via the two-wire serial interface while FRAME_VALID is asserted for frame n, the first frame output using the new integration time is frame (n + 2). Similarly, when automatic exposure control is enabled, any change to the integration time for frame n first appears in frame (n + 2) output. The sequence is as follows: 1. During frame n, the new integration time is held in the R0x0B live register. 2. At the start of frame (n + 1), the new integration time is transferred to the exposure control module. Integration for each row of frame (n + 1) has been completed using the old integration time. The earliest time that a row can start integrating using the new integration time is immediately after that row has been read for frame (n + 1). The actual time that rows start integrating using the new integration time is dependent on the new value of the integration time. 3. When frame (n + 1) is read out, it is integrated using the new integration time. If the integration time is changed (R0x0B written) on successive frames, each value written is applied to a single frame; the latency between writing a value and it affecting the frame readout remains at two frames. However, when automatic exposure control is disabled, if the integration time is changed through the two-wire serial interface after the falling edge of FRAME_VALID for frame n, the first frame output using the new integration time becomes frame (n + 3). Figure 20: Latency When Changing Integration FRAME_VALID New Integration Programmed Actual Integration Int = 200 rows Int = 300 rows Int = 200 rows Int = 300 rows LED_OUT Output image with Int = 200 rows Image Data Output image with Int = 300 rows Frame Start PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 25 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Exposure Indicator The exposure indicator is controlled by: • R0x1B LED_OUT Control The MT9V022 provides an output pin, LED_OUT, to indicate when the exposure takes place. When R0x1B bit 0 is clear, LED_OUT is HIGH during exposure. By using R0x1B, bit 1, the polarity of the LED_OUT pin can be inverted. High Dynamic Range High dynamic range is controlled by: • R0x08 Shutter Width 1 • R0x09 Shutter Width 2 • R0x0A Shutter Width Control • R0x31–R0x34 V_Step Voltages In the MT9V022, high dynamic range (that is, R0x0F, bit 6 = 1) is achieved by controlling the saturation level of the pixel (HDR or high dynamic range gate) during the exposure period. The sequence of the control voltages at the HDR gate is shown in Figure 21. After the pixels are reset, the step voltage, V_Step, which is applied to HDR gate, is setup at V1 for integration time t1 then to V2 for time t2, then V3 for time t3, and finally it is parked at V4, which also serves as an antiblooming voltage for the photodetector. This sequence of voltages leads to a piecewise linear pixel response, illustrated (in approximates) in Figure 21 on page 26. Figure 21: Sequence of Control Voltages at the HDR Gate Exposure VAA (3.3V) V1~1.4V t1 HDR Voltage Figure 22: V2~1.2V V3~1.0V V4~0.8V t2 t3 Sequence of Voltages in a Piecewise Linear Pixel Response dV3 Output dV2 dV1 Light Intensity 1/t PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 1 1/t 1/t 2 26 3 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description The parameters of the step voltage V_Step which takes values V1, V2, and V3 directly affect the position of the knee points in Figure 22. Light intensities work approximately as a reciprocal of the partial exposure time. Typically, t1 is the longest exposure, t2 shorter, and so on. Thus the range of light intensities is shortest for the first slope, providing the highest sensitivity. The register settings for V_Step and partial exposures are: V1 = R0x31, bits 4:0 V2 = R0x32, bits 4:0 V3 = R0x33, bits 4:0 V4 = R0x34, bits 4:0 t INT = t1 + t2 + t3 There are two ways to specify the knee points timing, the first by manual setting (default) and the second by automatic knee point adjustment. When the auto adjust enabler is set to HIGH (LOW by default), the MT9V022 calculates the knee points automatically using the following equations: t t t1 =tINT - t2 - t3 (EQ 1) 2 = tINT x (½)R0x0A, bits 3:0 (EQ 2) t R0x0A, bits 7:4 3 = INT x (½) (EQ 3) As a default for auto exposure, t2 is 1/16 of tINT, t3 is 1/64 of tINT. When the auto adjust enabler is disabled (default), t1, t2, and t3 may be programmed through the two-wire serial interface: t 1 = R0x08, bits 14:0 (EQ 4) 2 = (R0x09, bits 14:0) - (R0x08, bits 14:0) (EQ 5) t t t t t 3 = INT - 1 - 2 (EQ 6) t INT may be based on the manual setting of R0x0B or the result of the AEC. If the AEC is enabled then the auto knee adjust must also be enabled. Variable ADC Resolution By default, ADC resolution of the sensor is 10-bit. Additionally, a companding scheme of 12-bit into 10-bit is enabled by the R0x1C (28). This mode allows higher ADC resolution which means less quantization noise at low-light, and lower resolution at high light, where good ADC quantization is not so critical because of the high level of the photon’s shot noise. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 27 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Figure 23: 12- to 10-Bit Companding Chart 10-bit Codes 1,024 768 8 to 1 Companding (2,048 4 to 1 Companding (1,536 512 2 to 1 Companding (256 256 No companding (256 256 512 1,024 256) 384) 128) 12-bit Codes 256) 2,048 4,096 Gain Settings Changes to Gain Settings When the digital gain settings (R0x80–R0x98) are changed, the gain is updated on the next frame start. However, the latency for an analog gain change to take effect depends on the automatic gain control. If automatic gain control is enabled (R0xAF, bit 1 is set to HIGH), the gain changed for frame n first appears in frame (n + 1); if the automatic gain control is disabled, the gain changed for frame n first appears in frame (n + 2). Both analog and digital gain change regardless of whether the integration time is also changed simultaneously. Figure 24: Latency of Analog Gain Change When AGC Is Disabled FRAME_VALID New Gain Programmed Gain = 3.0X Actual Gain Gain = 3.5X Gain = 3.0X Output image with Gain = 3.0X Image Data Gain = 3.5X Output image with Gain = 3.5X Frame Start PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 28 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Analog Gain Analog gain is controlled by: • R0x35 Global Gain The formula for gain setting is: Gain = Bits[6:0] x 0.0625 (EQ 7) The analog gain range supported in the MT9V022 is 1X–4X with a step size of 6.25 percent. To control gain manually with this register, the sensor must NOT be in AGC mode. When adjusting the luminosity of an image, it is recommended to alter exposure first and yield to gain increases only when the exposure value has reached a maximum limit. Analog gain = bits (6:0) x 0.0625 for values 16–31 Analog gain = bits (6:0)/2 x 0.125 for values 32–64 For values 16–31: each LSB increases analog gain 0.0625v/v. A value of 16 = 1X gain. Range: 1X to 1.9375X. For values 32–64: each 2 LSB increases analog gain 0.125v/v (that is, double the gain increase for 2 LSB). Range: 2X to 4X. Odd values do not result in gain increases; the gain increases by 0.125 for values 32, 34, 36, and so on. Digital Gain Digital gain is controlled by: • R0x99–R0xA4 Tile Coordinates • R0x80–R0x98 Tiled Digital Gain and Weight In the MT9V022, the image may be divided into 25 tiles, as shown in Figure 25, through the two-wire serial interface, and apply digital gain individually to each tile. Figure 25: Tiled Sample X0/5 X1/5 X2/5 X3/5 Y0/5 x0_y0 x1_y0 X5/5 X5/5 x4_y0 Y1/5 x0_y1 x1_y1 x4_y1 x0_y2 x1_y2 x4_y2 x0_y3 x1_y3 x4_y3 x0_y4 x1_y4 x4_y4 Y2/5 Y3/5 Y4/5 Y5/5 PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 29 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Registers 0x99–0x9E and 0x9F–0xA4 represent the coordinates X0/5-X5/5 and Y0/5-Y5/5 in Figure 25, respectively. Digital gains of registers 0x80–0x98 apply to their corresponding tiles. The MT9V022 supports a digital gain of 0.25-3.75X. The formula for digital gain setting is: Digital Gain = Bits[3:0] x 0.25 (EQ 8) Black Level Calibration Black level calibration is controlled by: • R0x4C • R0x42 • R0x46–R0x48 The MT9V022 has automatic black level calibration on-chip, and if enabled, its result may be used in the offset correction shown in Figure 26. Figure 26: Black Level Calibration Flow Chart Gain Selection (R0x35 or result of AGC) Pixel Output (reset minus signal) Offset Correction Voltage (R0x48 or result of BLC) VREF (R0x2C) 10 (12) bit ADC ADC Data (9:0) C1 S C2 The automatic black level calibration measures the average value of pixels from 2 dark rows (1 dark row if row bin 4 is enabled) of the chip. (The pixels are averaged as if they were light-sensitive and passed through the appropriate gain.) This row average is then digitally low-pass filtered over many frames (R0x47, bits 7:5) to remove temporal noise and random instabilities associated with this measurement. Then, the new filtered average is compared to a minimum acceptable level, low threshold, and a maximum acceptable level, high threshold. If the average is lower than the minimum acceptable level, the offset correction voltage is increased by a programmable offset LSB in R0x4C. (Default step size is 2 LSB Offset = 1 ADC LSB at analog gain = 1X.) If it is above the maximum level, the offset correction voltage is decreased by 2 LSB (default). To avoid oscillation of the black level from below to above, the region the thresholds should be programmed so the difference is at least two times the offset DAC step size. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 30 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description In normal operation, the black level calibration value/offset correction value is calculated at the beginning of each frame and can be read through the two-wire serial interface from R0x48. This register is an 8-bit signed two’s complement value. However, if R0x47, bit 0 is set to “1,” the calibration value in R0x48 may be manually set to override the automatic black level calculation result. This feature can be used in conjunction with the “show dark rows” feature (R0x0D, bit 6) if using an external black level calibration circuit. The offset correction voltage is generated according to the following formulas: Offset Correction Voltage = (8-bit signed two’s complement calibration value,-127 to 127) × 0.5mV (EQ 9) ADC input voltage = (Pixel Output Voltage + Offset Correction Voltage) × Analog Gain (EQ 10) Row-wise Noise Correction Row-wise noise correction is controlled by the following registers: • R0x70 Row Noise Control • R0x72 Row Noise Constant • R0x73 Dark Column Start When the row-wise noise cancellation algorithm is enabled, the average value of the dark columns read out is used as a correction for the whole row. The row-wise correction is in addition to the general black level correction applied to the whole sensor frame and cannot be used to replace the latter. The dark average is subtracted from each pixel belonging to the same row, and then a positive constant is added (R0x72, bits 7:0). This constant should be set to the dark level targeted by the black level algorithm plus the noise expected on the measurements of the averaged values from dark columns; it is meant to prevent clipping from negative noise fluctuations. Pixel value = ADC value - dark column average + row noise constant (EQ 11) On a per-row basis, the dark column average is calculated from a programmable number of dark columns (pixels) values (R0x70, bits 3:0). The default is 10 dark columns. Of these, the maximum and minimum values are removed and then the average is calculated. If R0x70, bits 3:0 are set to “0” (2 pixels), it is essentially equivalent to disabling the dark average calculation since the average is equal to “0” after the maximum and minimum values are removed. R0x73 is used to indicate the starting column address of dark pixels which row-noise correction algorithm uses for calculation. In the MT9V022, dark columns which may be used are 759–776. R0x73 is used to select the starting column for the calculation. One additional note in setting the row-noise correction register: 777 < (R0x73, bits 9:0) + number of dark pixels programmed in R0x70, bits 3:0 -1 (EQ 12) This is to ensure the column pointer does not go beyond the limit the MT9V022 can support. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 31 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Automatic Gain Control and Automatic Exposure Control The integrated AEC/AGC unit is responsible for ensuring that optimal auto settings of exposure and (analog) gain are computed and updated every frame. AEC and AGC can be individually enabled or disabled by R0xAF. When AEC is disabled (R0xAF[0] = 0), the sensor uses the manual exposure value in R0x0B. When AGC is disabled (R0xAF[1] = 0), the sensor uses the manual gain value in R0x35. See Aptina Technical Note TN-09-17, “MT9V022 AEC and AGC Functions,” for further details. Figure 27: Controllable and Observable AEC/AGC Registers EXP. LPF (R0xA8) MAX. EXPOSURE (R0xBD) DESIRED BIN (desired luminance) (R0xA5) MANUAL EXP. (R0x0B) AEC UNIT MIN EXP. CURRENT BIN (current luminance) (R0xBC) 1 EXP. SKIP (R0xA6) AEC OUTPUT To exposure timing control 1 HISTOGRAM GENERATOR UNIT AGC UNIT MIN GAIN 0 R0xBB AGC OUTPUT 16 AEC ENABLE (R0xAF[0]) 1 To analog gain control 0 MAX. GAIN (R0x36) R0xBA GAIN LPF (R0xAB) GAIN SKIP (R0xA9) MANUAL GAIN (R0x35) AGC ENABLE (R0xAF[1]) The exposure is measured in row-time by reading R0xBB. The exposure range is 1 to 2047. The gain is measured in gain-units by reading R0xBA. The gain range is 16 to 63 (unity gain = 16 gain-units; multiply by 1/16 to get the true gain). When AEC is enabled (R0xAF[0] = 1), the maximum auto exposure value is limited by R0xBD; minimum auto exposure is fixed at 1 row. When AGC is enabled (R0xAF[1] = 1), the maximum auto gain value is limited by R0x36; minimum auto gain is fixed to 16 gain-units. The exposure control measures current scene luminosity and desired output luminosity by accumulating a histogram of pixel values while reading out a frame. The desired exposure and gain are then calculated from this for subsequent frame. Pixel Clock Speed The pixel clock speed is same as the master clock (SYSCLK) at 26.66 MHz by default. However, when column binning 2 or 4 (R0x0D, bit 2 or 3) is enabled, the pixel clock speed is reduced by half and one-fourth of the master clock speed respectively. See “Read Mode Options” on page 34 and “Column Binning” on page 35 for additional information. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 32 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Hard Reset of Logic The RC circuit for the MT9V022 uses a 10kΩ resistor and a 0.1μF capacitor. The rise time for the RC circuit is 1μs maximum. Soft Reset of Logic Soft reset of logic is controlled by: • R0x0C Reset Bit 0 is used to reset the digital logic of the sensor while preserving the existing two-wire serial interface configuration. Furthermore, by asserting the soft reset, the sensor aborts the current frame it is processing and starts a new frame. Bit 1 is a shadowed reset control register bit to explicitly reset the automatic gain and exposure control feature. These two bits are self-resetting bits and also return to “0” during two-wire serial interface reads. STANDBY Control The sensor goes into standby mode by setting STANDBY to HIGH. Once the sensor detects that STANDBY is asserted, it completes the current frame before disabling the digital logic, internal clocks, and analog power enable signal. To release the sensor out from the standby mode, reset STANDBY back to LOW. The LVDS must be powered to ensure that the device is in standby mode. See "Appendix B – Power-On Reset and Standby Timing" on page 52 for more information on standby. Monitor Mode Control Monitor mode is controlled by: • R0x0E Monitor Mode Enable • R0xC0 Monitor Mode Image Capture Control The sensor goes into monitor mode when R0x0E bit 0 is set to HIGH. In this mode, the sensor first captures a programmable number of frames (R0xC0), then goes into a sleep period for five minutes. The cycle of sleeping for five minutes and waking up to capture a number of frames continues until R0x0E bit 0 is cleared to return to normal operation. In some applications when monitor mode is enabled, the purpose of capturing frames is to calibrate the gain and exposure of the scene using automatic gain and exposure control feature. This feature typically takes less than 10 frames to settle. In case a larger number of frames is needed, the value of R0xC0 may be increased to capture more frames. During the sleep period, none of the analog circuitry and a very small fraction of digital logic (including a five-minute timer) is powered. The master clock (SYSCLK) is therefore always required. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 33 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Read Mode Options (Also see “Output Data Format” on page 11 and “Output Data Timing” on page 13.) Column Flip By setting bit 5 of R0x0D the readout order of the columns is reversed, as shown in Figure 28 on page 34. Row Flip By setting bit 4 of R0x0D the readout order of the rows is reversed, as shown in Figure 29 on page 34. Figure 28: Readout of Six Pixels in Normal and Column Flip Output Mode LINE_VALID Normal readout DOUT(9:0) Reverse readout DOUT(9:0) Figure 29: P4,1 (9:0) P4,2 (9:0) P4,3 (9:0) P4,4 (9:0) P4,5 (9:0) P4,6 (9:0) P4,n (9:0) P4,n-1 (9:0) P4,n-2 (9:0) P4,n-3 (9:0) P4,n-4 (9:0) P4,n-5 (9:0) Readout of Six Rows in Normal and Row Flip Output Mode LINE_VALID Normal readout DOUT(9:0) Reverse readout DOUT(9:0) Row4 (9:0) Row5 (9:0) Row6 (9:0) Row7 (9:0) Row8 7(9:0) Row9 (9:0) Row484 (9:0) Row483 (9:0) Row482 (9:0) Row481 (9:0) Row480 7(9:0) Row479 (9:0) Pixel Binning In addition to windowing mode in which smaller resolution (CIF, QCIF) is obtained by selecting small window from the sensor array, the MT9V022 also provides the ability to show the entire image captured by pixel array with smaller resolution by pixel binning. Pixel binning is based on combining signals from adjacent pixels by averaging. There are two options: binning 2 and binning 4. When binning 2 is on, 4 pixel signals from 2 adjacent rows and columns are combined. In binning 4 mode, 16 pixels are combined from 4 adjacent rows and columns. The image mode may work in conjunction with image flip. The binning operation increases SNR but decreases resolution. Enabling row bin2 and row bin4 improves frame rate by 2x and 4x respectively. The feature of column binning does not increase the frame rate in less resolution modes. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 34 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Row Binning By setting bit 0 or 1 of R0x0D, only half or one-fourth of the row set is read out, as shown in figure below. The number of rows read out is half or one-fourth of what is set in R0x03. Column Binning In setting bit 2 or 3 of R0x0D, the pixel data rate is slowed down by a factor of either two or four, respectively. This is due to the overhead time in the digital pixel data processing chain. As a result, the pixel clock speed is also reduced accordingly. Figure 30: Readout of 8 Pixels in Normal and Row Bin Output Mode LINE_VALID Normal readout DOUT(9:0) Row4 (9:0) Row5 (9:0) Row6 (9:0) Row7 (9:0) Row4 (9:0) Row6 (9:0) Row8 (9:0) Row10 (9:0) Row4 (9:0) Row8 (9:0) Row8 (9:0) Row9 (9:0) Row10 (9:0) Row11 (9:0) LINE_VALID Row Bin 2 readout DOUT(9:0) LINE_VALID Row Bin 4 readout DOUT(9:0) Figure 31: Readout of 8 Pixels in Normal and Column Bin Output Mode LINE_VALID Normal readout DOUT(9:0) D1 (9:0) D2 (9:0) D3 (9:0) D4 (9:0) D5 (9:0) D6 (9:0) D7 (9:0) D8 (9:0) PIXCLK LINE_VALID Column Bin 2 readout DOUT(9:0) D12 (9:0) D34 (9:0) D56 (9:0) D78 (9:0) PIXCLK LINE_VALID Column Bin 4 readout d1234 (9:0) DOUT(9:0) d5678 (9:0) PIXCLK PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 35 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Interlaced Readout The MT9V022 has two interlaced readout options. By setting R0x07[2:0] = 1, all the evennumbered rows are read out first, followed by a number of programmable field blanking (R0xBF, bits 7:0), and then the odd-numbered rows and finally vertical blanking (minimum is 4 blanking rows). By setting R0x07[2:0] = 2, only one field is read out; consequently, the number of rows read out is half what is set in R0x03. The row start address (R0x02) determines which field gets read out; if the row start address is even, the even field is read out; if row start address is odd, the odd field is read out. Figure 32: Spatial Illustration of Interlaced Image Readout P4,1 P4,2 P4,3.....................................P4,n-1 P4,n P6,0 P6,1 P6,2.....................................P6,n-1 P6,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VALID IMAGE - Even Field Pm-2,0 Pm-2,2.....................................Pm-2,n-2 Pm-2,n Pm,2 Pm,2.....................................Pm,n-1 Pm,n 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 HORIZONTAL BLANKING FIELD BLANKING P5,1 P5,2 P5,3.....................................P5,n-1 P5,n P7,0 P7,1 P7,2.....................................P7,n-1 P7,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VALID IMAGE - Odd Field 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 Pm-3,1 Pm-3,2.....................................Pm-3,n-1 Pm-3,n Pm,1 Pm,1.....................................Pm,n-1 Pm,n VERTICAL BLANKING 00 00 00 ............................................................................................. 00 00 00 00 00 00 ............................................................................................. 00 00 00 When interlaced mode is enabled, the total number of blanking rows are determined by both field blanking register (R0xBF) and vertical blanking register (R0x06). The followings are their equations. Field Blanking = R0xBF, bits 7:0 (EQ 13) Vertical Blanking = R0x06, bits 8:0 -R0xBF, bits 7:0 (EQ 14) with minimum vertical blanking requirement = 4 (EQ 15) Similar to progressive scan, FRAME_VALID is logic LOW during the valid image row only. Binning should not be used in conjunction with interlaced mode. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 36 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description LINE_VALID By setting bit 2 and 3 of R0x74 the LINE_VALID signal can get three different output formats. The formats for reading out four rows and two vertical blanking rows are shown in Figure 33. In the last format, the LINE_VALID signal is the XOR between the continuous LINE_VALID signal and the FRAME_VALID signal. Figure 33: Different LINE_VALID Formats Default FRAME_VALID LINE_VALID Continuously FRAME_VALID LINE_VALID XOR FRAME_VALID LINE_VALID LVDS Serial (Stand-Alone/Stereo) Output The LVDS interface allows for the streaming of sensor data serially to a standard off-theshelf deserializer up to five meters away from the sensor. The pixels (and controls) are packeted—12-bit packets for stand-alone mode and 18-bit packets for stereoscopy mode. All serial signalling (CLK and data) is LVDS. The LVDS serial output could either be data from a single sensor (stand-alone) or stream-merged data from two sensors (self and its stereoscopic slave pair). The appendices describe in detail the topologies for both stand-alone and stereoscopic modes. There are two standard deserializers that can be used. One for a stand-alone sensor stream and the other from a stereoscopic stream. The deserializer attached to a standalone sensor is able to reproduce the standard parallel output (8-bit pixel data, LINE_VALID, FRAME_VALID and PIXCLK). The deserializer attached to a stereoscopic sensor is able to reproduce 8-bit pixel data from each sensor (with embedded LINE_VALID and FRAME_VALID) and pixel-clk. An additional (simple) piece of logic is required to extract LINE_VALID and FRAME_VALID from the 8-bit pixel data. Irrespective of the mode (stereoscopy/stand-alone), LINE_VALID and FRAME_VALID are always embedded in the pixel data. In stereoscopic mode, the two sensors run in lock-step, implying all state machines are in the same state at any given time. This is ensured by the sensor-pair getting their sysclks and sys-resets in the same instance. Configuration writes through the two-wire serial interface are done in such a way that both sensors can get their configuration updates at once. The inter-sensor serial link is designed in such a way that once the slave PLL locks and the data-dly, shft-clk-dly and stream-latency-sel are configured, the master sensor streams good stereo content irrespective of any variation voltage and/or temperature as long as it is within specification. The configuration values of data-dly, shft-clk-dly and stream-latency-sel are either predetermined from the board-layout or can be empirically determined by reading back the stereo-error flag. This flag gets asserted when the two sensor streams are not in sync when merged. The combo_reg is used for out-of-sync diagnosis. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 37 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Figure 34: Serial Output Format for a 6x2 Frame Internal PIXCLK Internal Parallel Data P41 P42 P43 P44 P45 P46 P51 P52 P53 P54 P55 P56 Internal Line_Valid Internal Frame_Valid External Serial Data Out Notes: 1023 0 1023 1 P41 P42 P43 P44 P45 P46 2 1 P51 P52 P53 P54 P55 P56 3 1. External pixel values of 0, 1, 2, 3, are reserved (they only convey control information). Any raw pixel of value 0, 1, 2 and 3 will be substituted with 4. 2. The external pixel sequence 1023, 0 1023 is a reserved sequence (conveys control information). Any raw pixel sequence of 1023, 0, 1023 will be substituted with 1023, 4, 1023. LVDS Output Format In stand-alone mode, the packet size is 12 bits (2 frame bits and 10 payload bits); 10-bit pixels or 8-bit pixels can be selected. In 8-bit pixel mode (R0xB6[0] = 0), the packet consists of a start bit, 8-bit pixel data (with sync codes), the line valid bit, the frame valid bit and the stop bit. For 10-bit pixel mode (R0xB6[0] = 1), the packet consists of a start bit, 10-bit pixel data, and the stop bit. Table 7: LVDS Packet Format in Stand-Alone Mode (Stereoscopy Mode Bit De-Asserted) 12-Bit Packet use_10-bit_pixels Bit De-Asserted (8-Bit Mode) use_10-bit_pixels Bit Asserted (10-Bit Mode) Bit[0] Bit[1] Bit2] Bit[3] Bit4] Bit[5] Bit[6] Bit[7] Bit[8] Bit[9] Bit[10] Bit[11] 1'b1 (Start bit) PixelData[2] PixelData[3] PixelData[4] PixelData[5] PixelData[6] PixelData[7] PixelData[8] PixelData[9] Line_Valid Frame_Valid 1'b0 (Stop bit) 1'b1 (Start bit) PixelData[0] PixelData[1] PixelData[2] PixelData[3] PixelData[4] PixelData[5] PixelData[6] PixelData[7] PixelData[8] PixelData[9] 1'b0 (Stop bit) In stereoscopic mode (see Figure 47 on page 50), the packet size is 18 bits (2 frame bits and 16 payload bits). The packet consists of a start bit, the master pixel byte (with sync codes), the slave byte (with sync codes), and the stop bit.) PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 38 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Table 8: LVDS Packet Format in Stereoscopy Mode (Stereoscopy Mode Bit Asserted) 18-bit Packet Function Bit[0] Bit[1] Bit[2] Bit[3] Bit[4] Bit[5] Bit[6] Bit[7] Bit[8] Bit[9] Bit[10] Bit[11] Bit[12] Bit[13] Bit[14] Bit[15] Bit[16] Bit[17] 1'b1 (Start bit) MasterSensorPixelData[2] MasterSensorPixelData[3] MasterSensorPixelData[4] MasterSensorPixelData[5] MasterSensorPixelData[6] MasterSensorPixelData[7] MasterSensorPixelData[8] MasterSensorPixelData[9] SlaveSensorPixelData[2] SlaveSensorPixelData[3] SlaveSensorPixelData[4] SlaveSensorPixelData[5] SlaveSensorPixelData[6] SlaveSensorPixelData[7] SlaveSensorPixelData[8] SlaveSensorPixelData[9] 1'b0 (Stop bit) Control signals LINE_VALID and FRAME_VALID can be reconstructed from their respective preceding and succeeding flags that are always embedded within the pixel data in the form of reserved words. Table 9: Reserved Words in the Pixel Data Stream Pixel Data Reserved Word Flag 0 1 2 3 Precedes frame valid assertion Precedes line valid assertion Succeeds line valid de-assertion Succeeds frame valid de-assertion When LVDS mode is enabled along with column binning (bin 2 or bin 4, R0x0D[3:2], the packet size remains the same but the serial pixel data stream repeats itself depending on whether 2X or 4X binning is set: • For bin 2, LVDS outputs double the expected data (pixel 0,0 is output twice in sequence, followed by pixel 0,1 twice, . . .). • For bin 4, LVDS outputs 4 times the expected data (pixel 0,0 is output 4 times in sequence followed by pixel 0,1 times 4, . . .). The receiving hardware will need to undersample the output stream getting data either every 2 clocks (bin 2) or every 4 (bin 4) clocks. If the sensor provides a pixel whose value is 0,1, 2, or 3 (that is, the same as a reserved word) then the outgoing serial pixel value is switched to 4. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 39 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Electrical Specifications Table 10: DC Electrical Characteristics VPWR = 3.3V ±0.3V; TA = Ambient = 25°C Symbol Definition VIH VIL IIN Input high voltage Input low voltage Input leakage current VOH VOL IOH IOL VAA IPWRA VDD IPWRD VAAPIX IPIX VLVDS ILVDS IPWRA Standby IPWRD Standby Clock Off IPWRD Standby Clock On Output high voltage Output low voltage Output high current Output low current Analog power supply Analog supply current Digital power supply Digital supply current Pixel array power supply Pixel supply current LVDS power supply LVDS supply current Analog standby supply current Condition Minimum Typical Maximum Unit VPWR - 0.5 –0.3 –15.0 – – – VPWR + 0.3 0.8 15.0 V V μA VPWR -0.7 – –9.0 – 3.0 – 3.0 – 3.0 0.5 3.0 11.0 2 – – – – 3.3 35.0 3.3 35.0 3.3 1.4 3.3 13.0 3 – 0.3 – 9.0 3.6 60.0 3.6 60 3.6 3.0 3.6 15.0 4 V V mA mA V mA V mA V mA V mA μA Digital standby supply current with STDBY = VDD, CLKIN = 0 MHz clock off 1 2 4 μA Digital standby supply current with STDBY= VDD, CLKIN = 27 MHz clock on – 1.05 – mA 250 – – – 400 50 mV mV 1.0 – 1.2 – 1.4 35 mV mV ±10 ±12 mA ±1 ±10 μA – – ±20 100 mV μA No pull-up resistor; VIN = VPWR or VGND IOH = –4.0mA IOL = 4.0mA VOH = VDD - 0.7 VOL = 0.7 Default settings Default settings Default settings Default settings, CLOAD = 10pF Default settings Default settings Default settings Default settings STDBY = VDD LVDS Driver DC Specifications |VOD| |DVOD| VOS DVOS Output differential voltage Change in VOD between complementary output states Output offset voltage Change in VOS between complementary output states RLOAD = 100 Ω ± 1% IOS IOZ Output current when driver shorted to ground Output current when driver is tristate LVDS Receiver DC Specifications VIDTH+ Iin Input differential Input current PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN | VGPD| < 925mV 40 –100 – Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Table 11: Absolute Maximum Ratings Caution Symbol Parameter Minimum Maximum Unit –0.3 – – –0.3 –0.3 –40 4.5 200 200 VDD + 0.3 VDD + 0.3 +125 V mA mA V V °C Power supply voltage (all supplies) Total power supply current Total ground current DC input voltage DC output voltage Storage temperature VSUPPLY ISUPPLY IGND VIN VOUT TSTG1 Notes: Table 12: Stresses greater than those listed may cause permanent damage to the device. 1. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. AC Electrical Characteristics VPWR = 3.3V ±0.3V; TA = Ambient = 25°C; Output Load = 10pF Symbol SYSCLK tR tF tPLHP tPD tSD tHD tPFLR tPFLF Definition Input clock frequency Clock duty cycle Input clock rise time Input clock fall time SYSCLK to PIXCLK propagation delay PIXCLK to valid DOUT(9:0) propagation delay Data setup time Data hold time PIXCLK to LINE_VALID propagation delay PIXCLK to FRAME_VALID propagation delay Notes: Condition Minimum Typical Maximum Unit Note 1 13.0 45.0 1 1 3 –2 14 14 –2 –2 26.6 50.0 2 2 7 0 16 16 0 0 27.0 55.0 5 5 11 2 – – 2 2 MHz % ns ns ns ns ns CLOAD = 10pF CLOAD = 10pF CLOAD = 10pF CLOAD = 10pF ns ns 1. The frequency range specified applies only to the parallel output mode of operation. Propagation Delays for PIXCLK and Data Out Signals The pixel clock is inverted and delayed relative to the master clock. The relative delay from the master clock (SYSCLK) rising edge to both the pixel clock (PIXCLK) falling edge and the data output transition is typically 7ns. Note that the falling edge of the pixel clock occurs at approximately the same time as the data output transitions. See Table 12 for data setup and hold times. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 41 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Propagation Delays for FRAME_VALID and LINE_VALID Signals The LINE_VALID and FRAME_VALID signals change on the same rising master clock edge as the data output. The LINE_VALID goes HIGH on the same rising master clock edge as the output of the first valid pixel's data and returns LOW on the same master clock rising edge as the end of the output of the last valid pixel's data. As shown in the “Output Data Timing” on page 13, FRAME_VALID goes HIGH 143 pixel clocks before the first LINE_VALID goes HIGH. It returns LOW 23 pixel clocks after the last LINE_VALID goes LOW. Figure 35: Propagation Delays for PIXCLK and Data Out Signals tF tR SYSCLK tPLHP PIXCLK tPD tSD tHD DOUT(9:0) Figure 36: Propagation Delays for FRAME_VALID and LINE_VALID Signals t PFLR PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN t PFLF PIXCLK PIXCLK FRAME_VALID LINE_VALID FRAME_VALID LINE_VALID 42 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Performance Specifications Table 13 summarizes the specification for each performance parameter. Table 13: Performance Specifications Parameter Sensitivity DSNU PRNU Dynamic Range SNR Notes: Unit Minimum Typical Maximum Test Number LSB LSB % dB dB 400 N/A N/A 52.0 33.0 572 2.3 1.3 54.4 37.3 745 7.0 4.0 N/A N/A 1 2 3 4 5 1. All specifications address operation is at TA = 25°C (±3°C) and supply voltage = 3.3V. Image sensor was tested without a lens. Multiple images were captured and analyzed. Setup: VDD = VAA = VAAPIX = LVDSVDD = 3.3V. Testing was done with default frame timing and default register settings, with the exception of AEC/AGC, row noise correction, and auto black level, which were disabled. Performance definitions are detailed in the following sections. Test 1: Sensitivity A flat-field light source (90 lux, color temperature 4400K, broadband, w/ IR cut filter) is used as an illumination source. Signals are measured in LSB on the sensor output. A series of four frames are captured and averaged to obtain a scalar sensitivity output code. Test 2: Dark Signal Non-Uniformity (DSNU) The image sensor is held in the dark. Analog gain is changed to the maximum setting of 4X. Signals are measured in LSB on the sensor output. A series of four frames are captured and averaged (pixel-by-pixel) into one average frame. DSNU is calculated as the standard deviation of this average frame. Test 3: Photo Response Non-Uniformity (PRNU) A flat-field light source (90 lux, color temperature 4400K, broadband, with IR cut filter) is used as an illumination source. Signals are measured in LSB on the sensor output. Two series of four frames are captured and averaged (pixel-by-pixel) into one average frame, one series is captured under illuminated conditions, and one is captured in the dark. PRNU is expressed as a percentage relating the standard deviation of the average frames difference (illuminated frame - dark frame) to the average illumination level: Np 12 ----(S ( i ) – S dark ( i ) ) N p ∑ illumination i=1 PRNU = 100 × --------------------------------------------------------------------------------------N (EQ 16) p 1----(S (i)) N p ∑ illumination i=1 where Sillumination(i) is the signal measured for the i-th pixel from the average illuminated frame, Sdark(i) is the signal measured for the i-th pixel from the average dark frame, and Np is the total number of pixels contained in the array. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 43 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Test 4: Dynamic Range A temporal noise measurement is made with the image sensor in the dark and analog gain changed to the maximum setting of 4X. Signals are measured in LSB on the sensor output. Two consecutive dark frames are captured. Temporal noise is calculated as the average pixel value of the difference frame: Np ∑ ( S1i – S2i ) σi = 2 i-----------------------------------=1 (EQ 17) 2 ⋅ Np Where S1i is the signal measured for the i-th pixel from the first frame, S2i is the signal measured for the i-th pixel from the second frame, and Np is the total number of pixels contained in the array. The dynamic range is calculated according to the following formula: 4 × 1022 DynamicRange = 20 ⋅ log --------------------σt (EQ 18) Where σt is the temporal noise measured in the dark at 4X gain. Test 5: Signal-to-Noise Ratio A flat-field light source (90 lux, color temperature 4400K, broadband, with IR cut filter) is used as an illumination source. Signals are measured in LSB on the sensor output. Two consecutive illuminated frames are captured. Temporal noise is calculated as the average pixel value of the difference frame (according to the formula shown in Test 4). The signal-to-noise ratio is calculated as the ratio of the average signal level to the temporal noise according to the following formula: ⎛ ⎛ Np ⎞ ⎞ ⎜⎜ ⎟ ⁄N ⎟ S ⎜ ⎜ ∑ 1i⎟ p⎟ ⎝⎝i = 1 ⎠ ⎠ Signal – to – Noise – Ratio = 20 ⋅ log -------------------------------------σt (EQ 19) Where σt is the temporal noise measured from the illuminated frames, S1i is the signal measured for the i-th pixel from the first frame, and Np is the total number of pixels contained in the array. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 44 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Two-Wire Serial Bus Timing The two-wire serial bus operation requires certain minimum master clock cycles between transitions. These are specified in the following diagrams in master clock cycles. Figure 37: Serial Host Interface Start Condition Timing 4 4 SCLK SDATA Figure 38: Serial Host Interface Stop Condition Timing 4 4 SCLK SDATA Notes: Figure 39: 1. All timing are in units of master clock cycle. Serial Host Interface Data Timing for Write 4 4 SCLK SDATA Notes: Figure 40: 1. SDATA is driven by an off-chip transmitter. Serial Host Interface Data Timing for Read 5 SCLK SDATA Notes: PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 1. SDATA is pulled LOW by the sensor, or allowed to be pulled HIGH by a pull-up resistor off-chip. 45 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Figure 41: Acknowledge Signal Timing After an 8-Bit WRITE to the Sensor 3 6 SCLK Sensor pulls down SDATA pin SDATA Figure 42: Acknowledge Signal Timing After an 8-Bit READ from the Sensor 6 7 SCLK SDATA Note: Sensor tri-states SDATA pin (turns off pull down) After a READ, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read sequence is complete, the master must generate a “No Acknowledge” by leaving SDATA to float HIGH. On the following cycle, a start or stop bit may be used. Temperature Reference The MT9V022 contains a temperature reference circuit that can be used to measure relative temperatures. Contact your Aptina field applications engineer (FAE) for more information on using this circuit. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 46 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Figure 43: Typical Quantum Efficiency—Color Blue Green (B) Green (R) Red 40 35 Q u a n tu m E ffic ie n c y ( % ) 30 25 20 15 10 5 0 350 450 550 650 750 850 950 1050 Wavelength (nm) Figure 44: Typical Quantum Efficiency—Monochrome 60 Q u a n tu m E ffic ie n c y ( % ) 50 40 30 20 10 0 350 450 550 650 750 850 950 1050 Wavelength (nm) PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 47 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Package Dimensions Package Dimensions Figure 45: 52-Ball IBGA 0.90 (for reference only) D Seating plane A 0.10 A 0.40 (for reference only) 0.375 ±0.050 0.525 ±0.050 0.125 (for reference only) 52X Ø0.55 Dimensions apply to solder balls post reflow. The prereflow ball is Ø0.50 on a Ø0.4 NSMD ball pad. 7.00 1.00 TYP Fuses Ball A1 5.50 Ball A1 ID Ball A8 1.849 CL First clear pixel 1.999 3.50 7.00 CL 4.90 9.000 ±0.075 2.88 CTR CL Ø0.15 A C B 1.00 TYP 9.000 ±0.075 B 4.512 CTR C Ø0.15 A B C Solder ball material: 96.5% Sn, 3% Ag, 0.5% Cu Substrate material: plastic laminate Encapsulant: epoxy Notes: PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN Optical center Optical area CL Maximum rotation of optical area relative to package edges: 1º Maximum tilt of optical area relative to package edge : 50Dmicrons. Maximum tilt of optical area relative to top of cover glass: 50 microns. Lid material: borosilicate glass 0.40 thickness Image sensor die 1. All dimensions in millimeters. 48 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Appendix A – Serial Configurations Appendix A – Serial Configurations With the LVDS serial video output, the deserializer can be up to 8 meters from the sensor. The serial link can save on the cabling cost of 14 wires (DOUT[9:0], LINE_VALID, FRAME_VALID, PIXCLK, GND). Instead, just 3 wires (2 serial LVDS, 1 GND) are sufficient to carry the video signal. Configuration of Sensor for Stand-Alone Serial Output with Internal PLL In this configuration, the internal PLL generates the shift-clk (x12). The LVDS pins SER_DATAOUT_P and SER_DATAOUT_N must be connected to a deserializer (clocked at approximately the same system clock frequency). Figure 46 shows how a standard off-the-shelf deserializer (National Semiconductor DS92LV1212A) can be used to retrieve the standard parallel video signals of DOUT(9:0), LINE_VALID and FRAME_VALID. Figure 46: Stand-Alone Topology CLK 26.6 MHz Osc. LVDS SER_DATAIN Sensor LVDS BYPASS_CLKIN LVDS SER_DATAOUT LVDS SHIFT_CLKOUT DS92LV1212A 8 PIXEL 8 meters (maximum) 26.6 MHz Osc. 2 LINE_VALID FRAME_VALID 8-bit configuration shown Typical configuration of the sensor: 1. Power-up sensor. 2. Enable LVDS driver (set R0xB3[4]= 0). 3. De-assert LVDS power-down (set R0xB1[1] = 0. 4. Issue a soft reset (set R0x0C[0] = 1 followed by R0x0C[0] = 0. If necessary: 5. Force sync patterns for the deserializer to lock (set R0xB5[0] = 1). 6. Stop applying sync patterns (set R0xB5[0] = 0). PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 49 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Appendix A – Serial Configurations Configuration of Sensor for Stereoscopic Serial Output with Internal PLL In this configuration the internal PLL generates the shift-clk (x18) in phase with the system-clock. The LVDS pins SER_DATAOUT_P and SER_DATAOUT_N must be connected to a deserializer (clocked at approximately the same system clock frequency). Figure 47 shows how a standard off-the-shelf deserializer can be used to retrieve back DOUT(9:2) for both the master and slave sensors. Additional logic is required to extract out LINE_VALID and FRAME_VALID embedded within the pixel data stream. Figure 47: Stereoscopic Topology SLAVE MASTER 26.6 MHz Osc. LVDS SER_DATAIN LVDS SER_DATAIN SENSOR SENSOR SENSOR LVDS BYPASS_CLKIN LVDS BYPASS_CLKIN X 1 8/X 1 2 PL L LVDS SER_DATAOUT LVDS SHIFT_CLKOUT LVDS SER_DATAOUT LVDS SHIFT_CLKOUT 5 meters (maximum) 1. PLL in non-bypass mode 2. PLL in x 18 mode (stereoscopy) 1. PLL in bypass mode DS92LV16 8 PIXEL FROM SLAVE 26.6 MHz Osc. 8 PIXEL FROM MASTER LV and FV are embedded in the data stream Typical configuration of the master and slave sensors: 1. Power up the sensors. 2. Broadcast WRITE to de-assert LVDS power-down (set R0xB1[1] = 0). 3. Individual WRITE to master sensor putting its internal PLL into bypass mode (set R0xB1[0] = 1). 4. Broadcast WRITE to both sensors to set the stereoscopy bit (set R0x07[5] = 1). 5. Make sure all resolution, vertical blanking, horizontal blanking, window size, and AEC/AGC configurations are done through broadcast WRITE to maintain lockstep. 6. Broadcast WRITE to enable LVDS driver (set R0xB3[4] = 0). 7. Broadcast WRITE to enable LVDS receiver (set R0xB2[4] = 0). 8. Individual WRITE to master sensor, putting its internal PLL into bypass mode (set R0xB1[0] = 1). 9. Individual WRITE to slave sensor, enabling its internal PLL (set R0xB1[0] = 0). 10. Individual WRITE to slave sensor, setting it as a stereo slave (set R0x07[6] = 1). 11. Individual WRITEs to master sensor to minimize the inter-sensor skew (set R0xB2[2:0], R0xB3[2:0], and R0xB4[1:0] appropriately). Use R0xB7 and R0xB8 to get lockstep feedback from stereo_error_flag. 12. Broadcast WRITE to issue a soft reset (set R0x0C[0] = 1 followed by R0x0C[0] = 0). Note: PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN The stereo_error_flag is set if a mismatch has occurred at a reserved byte (slave and master sensor’s codes at this reserved byte must match). If the flag is set, steps 11 and 12 are repeated until the stereo_error_flag remains cleared. 50 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Appendix A – Serial Configurations Broadcast and Individual Writes for Stereoscopic Topology In stereoscopic mode, the two sensors are required to run in lockstep. This implies that control logic in each sensor is in exactly the same state as its pair on every clock. To ensure this, all inputs that affect control logic must be identical and arrive at the same time at each sensor. These inputs include: • system clock • system reset • two-wire serial interface clk - SCL • two-wire serial interface data - SDA Figure 48: Two-Wire Serial Interface Configuration in Stereoscopic Mode L 26.6 MHz Osc. L L S_CTRL_ADR[0] CLK S_CTRL_ADR[0] MASTER SENSOR SLAVE SENSOR CLK SCL HOST CLK SDA SCL SDA SCL SDA Host launches SCL and SDA on positive edge of SYSCLK. All system clock lengths (L) must be equal. SCL and SDA lengths to each sensor (from the host) must also be equal. The setup in Figure 48 shows how the two sensors can maintain lockstep when their configuration registers are written through the two-wire serial interface. A WRITE to configuration registers would either be broadcast (simultaneous WRITES to both sensors) or individual (WRITE to just one sensor at a time). READs from configuration registers would be individual (READs from just one sensor at a time). One of the two serial interface slave address bits of the sensor is hardwired. The other is controlled by the host. This allows the host to perform either a broadcast or a one-toone access. Broadcast WRITES are performed by setting the same S_CTRL_ADR input bit for both slave and master sensor. Individual WRITES are performed by setting opposite S_CTRL_ADR input bit for both slave and master sensor. Similarly, individual READs are performed by setting opposite S_CTRL_ADR input bit for both slave and master sensor. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 51 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Appendix B – Power-On Reset and Standby Timing Appendix B – Power-On Reset and Standby Timing Reset, Clocks, and Standby There are no constraints concerning the order in which the various power supplies are applied; however, the MT9V022 requires reset in order operate properly at power-up. Refer to Figure 49 for the power-up, reset, and standby sequences. Figure 49: Power-up, Reset, Clock and Standby Sequence Power up Active VDD, VDDLVDS, VAA, VAAPIX non-Low-Power Low-Power non-Low-Power Pre-Standby Wake up Standby Active Power down MIN 20 SYSCLK cycles RESET # Note 3 STANDBY MIN 10 SYSCLK cycles SYSCLK MIN 10 SYSCLK cycles MIN 10 SYSCLK cycles SCLK, SDATA Does not respond to serial interface when STANDBY = 1 Two-Wire Serial I/F DOUT[9:0] Driven = 0 DOUT[9:0] DATA OUTPUT Notes: PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 1. All output signals are defined during initial power-up with RESET# held LOW without SYSCLK being active. To properly reset the rest of the sensor, during initial power-up, assert RESET# (set to LOW state) for at least 750ns after all power supplies have stabilized and SYSCLK is active (being clocked). Driving RESET# to LOW state does not put the part in a low power state. 2. Before using two-wire serial interface, wait for 10 SYSCLK rising edges after RESET# is de-asserted. 3. Once the sensor detects that STANDBY has been asserted, it completes the current frame readout before entering standby mode. The user must supply enough SYSCLKs to allow a complete frame readout. See Table 4, “Frame Time,” on page 13 for more information. 4. In standby, all video data and synchronization output signals are High-Z. 5. In standby, the two-wire serial interface is not active. 52 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Appendix B – Power-On Reset and Standby Timing Standby Assertion Restrictions STANDBY cannot be asserted at any time. If STANDBY is asserted during a specific window within the vertical blanking period, the MT9V022 may enter a permanent standby state. This window (that is, dead zone) occurs prior to the beginning of the new frame readout. The permanent standby state is identified by the absence of the FRAME_VALID signal on frame readouts. Issuing a hardware reset (RESET# set to LOW state) will return the image sensor to default startup conditions. This dead zone can be avoided by: 1. Asserting STANDBY during the valid frame readout time (FRAME_VALID is HIGH) and maintaining STANDBY assertion for a minimum of one frame period. 2. Asserting STANDBY at the end of valid frame readout (falling edge of FRAME_VALID) and maintaining STANDBY assertion for a minimum of [5 + R0x06] row-times. When STANDBY is asserted during the vertical blanking period (FRAME_VALID is LOW), the STANDBY signal must not change state between [Vertical Blanking Register (R0x06) 5] row-times and [Vertical Blanking Register + 5] row-times after the falling edge of FRAME_VALID. Figure 50: STANDBY Restricted Location Dead Zone 10 row-times 5 row-times 5 row-times FRAME _VALID Vertical Blanking Period (R0x06) row-times PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 53 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Revision History Revision History Rev. H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/10 • Updated to non-confidential Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/10 • Updated to Aptina template Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12/06 • Changed description text in Table 3 on page 8, row H5, to "Error detected. Directly connected to STEREO ERROR FLAG." • Changed text in “Automatic Black Level Calibration” on page 11 • Changed “writing (or reading) the least significant 8 bits to R0x80 (128)” on page 15 to “writing (or reading) the least significant 8 bits to R0xF0 (240)” • Changed “the special register address (R0xF1)” on page 18 to “the special register address (R0xF0)” • Changed wording in Table 7 on page 15 row 0x00, on page 23 row 0xFF, and in Table 8 on page 19 row 0x00/0xFF from “Rev1,” etc. to “Iter1”, etc. • Updated legal values for R0x08, R0x09, R0x0B in Table 8 on page 19 • Updated Figure 24: “Latency of Analog Gain Change When AGC Is Disabled,” on page 28 • Changed signal name in Table 11 on page 41 in Maximum column, VIN and VOUT rows, from VDDQ to VDD • Moved “Propagation Delays for PIXCLK and Data Out Signals” up to follow Table 12 on page 41 • Added section on “Performance Specifications” on page 43 • Updated Figure 45 “52-Ball IBGA” on page 48 • Updated Figure 46: “Stand-Alone Topology,” on page 49 Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/06 • Added "Automatic Black Level Calibration" on page 11 • Updated Table 8, “Register Descriptions,” on page 19 (R0x73[9:0]) • Updated "Automatic Gain Control and Automatic Exposure Control" on page 32 • Updated "Row-wise Noise Correction" on page 31 • Updated Table 12, “AC Electrical Characteristics,” on page 41 • Updated "Appendix A – Serial Configurations" on page 49 • Updated "Configuration of Sensor for Stand-Alone Serial Output with Internal PLL" on page 49 • Updated Figure 46, Stand-Alone Topology, on page 49 • Updated "Configuration of Sensor for Stereoscopic Serial Output with Internal PLL" on page 50 • Updated Figure 47, Stereoscopic Topology, on page 50 Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12/05 • Added lead-free part numbers, page 1 • Added three notes to Table 3, “Ball Descriptions,” on page 8 • Updated Figure 3, Typical Configuration (Connection)—Parallel Output Mode, on page 9 PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 54 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Revision History • Updated Table 7, “Default Register Descriptions,” on page 15. Updated Registers 0x00, 0x0D, 0xF0, 0xF1 and 0xFF. Updated Registers 0x10, 0x15, 0x20 and 0xC2 with Rev 3 default values. • Updated Table 8, “Register Descriptions,” on page 19 0x00, 0xFF – Chip Version: added Rev 1, 2, and 3 values 0x06 – Vertical Blank: minimum number is 4 0x07 – Chip Control bit 5 - PLL generates 480 MHz clock 0x0D – Added reserve bits [9:8] 0x35 – Added calculation for lower and upper register ranges 0xF0 – Bytewise Address register corrected • Added "Simultaneous Master Mode" on page 20 • Added "Sequential Master Mode" on page 21 • Updated "Snapshot Mode" on page 21 • Updated "Slave Mode" on page 22 • Updated "Pixel Clock Speed" on page 32 • Added "Hard Reset of Logic" on page 33 • Updated Table 10, “DC Electrical Characteristics,” on page 40 • Added Table 11, “Absolute Maximum Ratings,” on page 41 • Updated Figure 35, Propagation Delays for PIXCLK and Data Out Signals, on page 42 • Updated "Appendix A – Serial Configurations" on page 49 • Updated Figure 46, Stand-Alone Topology, on page 49 • Updated Figure 47, Stereoscopic Topology, on page 50 • Added "Appendix B – Power-On Reset and Standby Timing" on page 52 Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/05 • Several text changes • Corrected steps in “Configuration of Sensor for Stereoscopic Serial Output with Internal PLL” on page 50 Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/05 • Updated part number and header on each page • Updated Table 1, “Key Performance Parameters,” on page 1 (Power Consumption). • Updated Figure 1, Block Diagram, on page 6; Update “General Description” on page 6 • Updated Table 3, “Ball Descriptions,” on page 8 • Updated Table 7, “Default Register Descriptions,” on page 15 (0xBE - Reserved) • Updated Table 8, “Register Descriptions,” on page 19 (R0x7F, R0x07[1:0], R0xB2[4], 0xB3[4], 0xBA, remove 0xBE) • Updated “Pixel Integration Control” on page 24 • Updated Table 10, “DC Electrical Characteristics,” on page 40 • Updated Table 12, “AC Electrical Characteristics,” on page 41 • Replaced “Thermometer” section and figure with section titled “Temperature Reference” on page 46 • Added Figure 45, 52-Ball IBGA, on page 48 10 Eunos Road 8 13-40, Singapore Post Center, Singapore 408600 prodmktg@aptina.com www.aptina.com Aptina, Aptina Imaging, DigitalClarity, and the Aptina logo are the property of Aptina Imaging Corporation All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 55 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation All rights reserved. MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor Revision History Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/05 • Initial release PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN 56 Aptina reserves the right to change products or specifications without notice. ©2005 Aptina Imaging Corporation. All rights reserved.