NB4N121KMN

NB4N121K 3.3V Differential In 1:21 Differential Fanout Clock Driver with HCSL level Output http://onsemi.com Description The NB4N121K is a Clock differential input fanout distribution 1 to 21 HCSL level differential outputs, optimized for ultra low propagation delay variation. The NB4N121K is designed with HCSL clock distribution for FBDIMM applications in mind. Inputs can accept differential LVPECL, CML, or LVDS levels. Single-ended LVPECL, CML, LVCMOS or LVTTL levels are accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12, and 13). Clock input pins incorporate an internal 50 W on die termination resistors. Output drive current at IREF (Pin 1) for 1X load is selected by connecting to GND. To drive a 2X load, connect IREF to VCC. See Figure 9. The NB4N121K specifically guarantees low output–to–output skews. Optimal design, layout, and processing minimize skew within a device and from device to device. System designers can take advantage of the NB4N121K's performance to distribute low skew clocks across the backplane or the motherboard. Features QFN-52 MN SUFFIX CASE 485M 1 52 MARKING DIAGRAM* 52 1 NB4N 121K AWLYYWWG • Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and • 340 ps Typical Rise and Fall Times • 800 ps Typical Propagation Delay • Dtpd 100 ps Maximum Propagation Delay Variation Per Each • • • • Differential Pair 2 kV Level 3 UL 94 V-0 @ 0.125 in 622 Table 3. MAXIMUM RATINGS (Note 3) Symbol VCC VI VINPP IOUT TA Tstg qJA qJC Tsol Parameter Positive Power Supply Positive Input Differential Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 3) Thermal Resistance (Junction-to-Case) Wave Solder Pb-Free 0 lfpm 500 lfpm 2S2P (Note 4) QFN-52 QFN-52 QFN-52 |CLK - CLKb| Continuous Surge QFN-52 Condition 1 GND = 0 V GND = 0 V Condition 2 Rating 6 GND - 0.3 v VI v VCC 1.2 50 100 -40 to +70 -65 to +150 25 19.6 21 265 Unit V V V mA mA °C °C °C/W °C/W °C/W °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard 51-6, multilayer board - 2S2P (2 signal, 2 power). 4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB4N121K Table 4. DC CHARACTERISTICS (VCC = 3.0 V to 3.6 V, TA = -40°C to +70°C Note 5) Symbol IGND ICC IIH IIL Characteristic GND Supply Current (All Outputs Loaded) Power Supply Current (All Outputs Loaded) Input HIGH Current CLKx, CLKx Input LOW Current CLKx, CLKx -150 1X 2X Min 70 Typ 98 420 780 2.0 -2.0 150 Max 120 Unit mA mA mA mA DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 5 and 7) Vth VIH VIL Input Threshold Reference Voltage Range (Note 6) Single-Ended Input HIGH Voltage Single-Ended Input LOW Voltage 1050 Vth + 150 GND VCC - 150 VCC Vth - 150 mV mV mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 8) VIHD VILD VID VCMR Differential Input HIGH Voltage Differential Input LOW Voltage Differential Input Voltage (VIHD - VILD) Input Common Mode Range 1200 GND 75 1163 VCC VCC - 75 2400 VCC - 75 mV mV mV HCSL OUTPUTS (Figure 4) VOH VOL Output HIGH Voltage Output LOW Voltage 600 -150 740 0 900 150 mV mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input parameters vary 1:1 with VCC. Measurements taken with outputs in either 1X (all outputs loaded 50 W to GND) or 2X (all outputs loaded 25 W to GND) configuration, see Figure 9. For 1X configuration, connect IREF to GND, or for 2X configuration, connect IREF to VCC. 6. Vth is applied to the complementary input when operating in single ended mode. http://onsemi.com 4 NB4N121K Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; -40°C to +70°C (Note 7) Symbol VOUTPP Characteristic Output Voltage Amplitude (@ VINPPmin) fin = 133 MHz fin = 166 MHz fin = 200 MHz CLK/CLK to Qx/Qx 550 Min Typ 725 725 725 800 Max 900 900 900 950 100 20 50 80 150 fin =133 MHz fin = 166 MHz fin = 200 MHz 150 250 1 Unit mV tPLH, tPHL DtPLH, DtPHL tSKEW Propagation Delay to (See Figure 3) ps ps ps ps ps ps ps Propagation Delay Variations Variation Per Each Diff Pair CLK/CLK to Qx/Qx (Note 8) (See Figure 3) Duty Cycle Skew (Note 9) Within-Device Skew, 1X Mode Only (Note 10) Within-Device Skew, 2X Mode (Note 10) Device-to-Device Skew (Note 10) RMS Random Clock Jitter (Note 11) tJITTER VINPP Vcross DVcross tr, tf Dtr, Dtf Input Voltage Swing/Sensitivity (Differential Configuration) Absolute Crossing Magnitude Voltage Variation in Magnitude of Vcross Absolute Magnitude in Output Risetime and Falltime (From 175 mV to 525 mV) Variation in Magnitude of Risetime and Falltime (Single-Ended) (See Figure 4) Qx, Qx Qx, Qx 1X 2X 1200 550 150 mV mV mV ps ps 175 340 700 125 150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. Measurements taken with outputs in either 1X (all outputs loaded 50 W to GND) or 2X (all outputs loaded 25 W to GND) configuration, see Figure 9. For 1X configuration, connect IREF to GND, or for 2X configuration, connect IREF to VCC. Typical gain is 20 dB. 8. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges. 9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+. 10. Skew is measured between outputs under identical transition @ 133 MHz. 11. Additive RMS jitter with 50% duty cycle clock signal using phase noise integrated from 12 KHz to 33 MHz CLK VINPP = VIH(CLK) - VIL(CLK) = VIH(CLK) - VIL(CLK) CLK tPLH Q VOUTPP = VOH(Q) - VOL(Q) = VOH(Q) - VOL(Q) Q tPHL DtPLH DtPHL Figure 3. AC Reference Measurement http://onsemi.com 5 NB4N121K 525 mV VCROSS 175 mV DVCROSS tr tf Figure 4. HCSL Output Parameter Characteristics CLK Vth CLK CLK Vth CLK Figure 5. Differential Input Driven Single-Ended (Vth = VREFAC) Figure 6. Differential Inputs Driven Differentially VCC Vthmax VIHmax VILmax VIH Vth VIL VIHmin VILmin VCC VCMmax VIHDmax VILDmax VID = VIHD - VILD VIHDtyp VILDtyp Vth VCMR Vthmin GND VCMmin GND VIHDmin VILDmin Figure 7. Vth Diagram Figure 8. VCMR Diagram http://onsemi.com 6 NB4N121K Qx RS1C Z 0 = 50 W 1X Load HCSL Driver RS2C Qx RREFA 2X Load Option A. For 1X configuration, connect IREF pin to GND or for 2X configuration, connect IREF pin to VCC. To adjust load drive for 1X configuration, use RREF from 0 W to 1 kW, to adjust 2X load, use 20 kW to 50 kW. B. RL1, RL2: 50 W for 1X Load 25 W for 2X Load C. RS1, RS2: 0 W for Test and Evaluation. Select to Minimizing Ringing. D. CL1, CL2, CL3, CL4: Receiver Input Simulation Load Capacitance Only Z 0 = 50 W RL1B 50 RL2B 50 CL1D 2 pF CL2D 2 pF Receiver Receiver 2 CL3D 2 pF CL4D 2 pF Figure 9. Typical Termination Configuration for Output Driver and Device Evaluation CLx for Test Only (Representing Receiver Input Loading); Not Added to Application VCC = 3.3 V VCC = 3.3 V VCC = 3.3 V VCC = 3.3 V Z 0 = 50 W NB4N121K D 50 W* LVDS Driver 50 W* D Z 0 = 50 W NB4N121K D 50 W* LVPECL Driver VTD VTD Z 0 = 50 W VTD VTD Z 0 = 50 W 50 W* D VTD = VTD = VCC - 2.0 V GND GND GND VTD = VTD GND *RTIN, Internal Input Termination Resistor *RTIN, Internal Input Termination Resistor Figure 10. LVPECL Interface Figure 11. LVDS Interface http://onsemi.com 7 NB4N121K VCC VCC VCC VCC Z 0 = 50 W VCC CML Driver VTD VTD Z 0 = 50 W NB4N121K D 50 W* LVCMOS/‐ LVTTL Driver Z 0 = 50 W NB4N121K D 50 W* VTD VTD 50 W* D 1.5 kW** 50 W* D VTD = VTD = VCC GND GND GND GND VTD = OPEN D = GND *RTIN, Internal Input Termination Resistor *RTIN, Internal Input Termination Resistor **or VREFAC GND Figure 12. Standard 50 W Load CML Interface Figure 13. LVCMOS/LVTTL Interface VCC VDR INTQ INTQb Q Qb Figure 14. HCSL Output Structure http://onsemi.com 8 NB4N121K ORDERING INFORMATION Device NB4N121KMN NB4N121KMNG NB4N121KMNR2 NB4N121KMNR2G Package QFN-52 QFN-52 (Pb-Free) QFN-52 QFN-52 (Pb-Free) Shipping† 260 Units / Tray 260 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 NB4N121K PACKAGE DIMENSIONS 52 PIN QFN 8x8 CASE 485M-01 ISSUE A D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.18 0.30 8.00 BSC 6.50 6.80 8.00 BSC 6.50 6.80 0.50 BSC 0.20 --0.30 0.50 E 2X 0.15 C 2X 0.15 C A2 0.10 C A 0.08 C SEATING PLANE DIM A A1 A2 A3 b D D2 E E2 e K L A1 D2 14 13 A3 REF C 26 27 52 X L E2 1 52 X 39 52 40 K e 52 X b NOTE 3 0.10 C A B 0.05 C ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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