NB3N121KMNR2G

NB3N121K 3.3V Differential 1:21 Fanout Clock and Data Driver with HCSL Outputs Description http://onsemi.com The NB3N121K is a differential 1:21 Clock and Data fanout buffer with High−speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N121K is designed with HCSL PCI Express clock distribution and FBDIMM applications in mind. Inputs can directly accept differential LVPECL, HCSL, and LVDS signals per Figures 7, 8, and 9. Single ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference supply per Figures 4 and 10. Input pins incorporate separate internal 50 W termination resistors allowing additional single ended system interconnect flexibility. Output drive current is set by connecting a 475 W resistor from IREF (Pin 1) to GND per Figure 6. Outputs can also interface to LVDS receivers when terminated per Figure 11. The NB3N121K specifically guarantees low output–to–output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. System designers can take advantage of the NB3N121K’s performance to distribute low skew clocks across the backplane or the motherboard. QFN−52 MN SUFFIX CASE 485M 1 MARKING DIAGRAM* 52 1 NB3N 121K AWLYYWWG A WL YY WW G Features • Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and • • • • • • • • • • 400 MHz 340 ps Typical Rise and Fall Times 800 ps Typical Propagation Delay 100 ps Max Within Device Skew 150 ps Max Device−to−Device Skew Dtpd 100 ps Maximum Propagation Delay Variation Per Each Differential Pair 0.1 ps Typical RMS Additive Phase Jitter LVDS Output Levels Optional with Interface Termination Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V Typical HCSL Output Level (700 mV Peak−to−Peak) These are Pb−Free Devices Applications • • • • • 52 = Assembly Site = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. Q0 Q0 VTCLK Q1 Q1 CLK CLK Q19 Q19 VTCLK Clock Distribution PCIe I, II, III Networking High End Computing Routers VCC GND Q20 IREF Q20 RREF Figure 1. Simplified Logic Diagram End Products • Servers • FBDIMM Memory Card © Semiconductor Components Industries, LLC, 2012 March, 2012 − Rev. 1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. 1 Publication Order Number: NB3N121K/D VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 52 51 50 49 48 47 46 45 44 43 42 41 40 NB3N121K Exposed Pad (EP) IREF 1 39 VCC GND 2 38 Q6 VTCLK 3 37 Q6 CLK 4 36 Q7 CLK 5 35 Q7 VTCLK 6 34 Q8 VCC 7 33 Q8 Q20 8 32 Q9 Q20 9 31 Q9 Q19 10 30 Q10 Q19 11 29 Q10 Q18 12 28 Q11 Q18 13 27 Q11 23 24 25 26 Q13 Q12 Q12 VCC 20 Q14 22 19 Q15 Q13 18 Q15 21 17 Q16 Q14 16 15 Q17 Q16 14 Q17 NB3N121K Figure 2. Pinout Configuration (Top View) http://onsemi.com 2 NB3N121K Table 1. PIN DESCRIPTION Pin Name 1 IREF Output I/O Use the IREF pin to set the output drive. Connect a 475 W RREF resistor from the IREF pin to GND to produce 2.63 mA of IREF current. A current mirror multiplies IREF by a factor of 5.4 to force 14.2 mA through a 50 W output load. See Figures 6 and 12. Minimize capacitance. 2 GND − Supply Ground. GND pin must be externally connected to power supply to guarantee proper operation. 3, 6 VTCLK, VTCLK − Internal 50 W Termination Resistor connection Pins. In the differential configuration when the input termination pins are connected to the common termination voltage, and if no signal is applied then the device may be susceptible to self−oscillation. 4 CLK LVPECL, HCSL, LVCMOS or LVTTL Input Clock (TRUE) Input 5 CLK LVPECL, HCSL, LVCMOS or LVTTL Input Clock (INVERT) Input 7, 26, 39, 52 VCC − 8, 10, 12, 14, 16, 18, 20, 22, 24, 27, 29, 31, 33, 35, 37, 40,42, 44, 46, 48, 50 Q[20−0] HCSL or LVDS Output (INVERT) (Note 1) (Note 1) Output 9, 11, 13, 15, 17, 19, 21, 23, 25, 28, 30, 32, 34, 36, 38, 41, 43, 45, 47, 49, 51 Q[20−0] HCSL or LVDS Output (TRUE) (Note 1) (Note 1) Output Exposed Pad EP GND Description Positive Supply pins. VCC pins must be externally connected to a power supply to guarantee proper operation. Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a sufficient heat−sinking conduit for proper thermal operation. The pad is electrically connected ot GND and must be connected to GND on the PC board. 1. Outputs can also interface to LVDS receiver when terminated per Figure 11. http://onsemi.com 3 NB3N121K Table 2. ATTRIBUTES Characteristic ESD Protection Value Human Body Model Machine Model Moisture Sensitivity (Note 2) Flammability Rating >2 kV 200 V QFN−52 Oxygen Index: 28 to 34 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 409 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS (Note 3) Symbol Rating Unit VCC Positive Power Supply Parameter GND = 0 V Condition 1 4.6 V VI Positive Input GND = 0 V GND − 0.3 ≤ VI ≤ VCC V IOUT Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range QFN−52 −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm 500 lfpm QFN−52 QFN−52 25 19.6 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P (Note 4) QFN−52 21 °C/W Tsol Wave Solder 265 °C Pb−Free Condition 2 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power). 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 4 NB3N121K Table 4. DC CHARACTERISTICS (VCC = 3.0 V to 3.6 V, TA = −40°C to +85°C Note 5) Symbol Typ Max Unit GND Supply Current (All Outputs Loaded) 120 150 mA ICC Power Supply Current (All Outputs Loaded) 440 500 mA IIH Input HIGH Current 2.0 150 mA IIL Input LOW Current IGND RTIN Characteristic Min Internal Input Termination Resistor −150 −2.0 45 50 mA 55 W DIFFERENTIAL INPUT DRIVEN SINGLE*ENDED (See Figures 4 and 5) Vth Input Threshold Reference Voltage Range (Note 6) 350 VCC − 1000 mV VIH Single−Ended Input HIGH Voltage Vth + 150 VCC mV VIL Single−Ended Input LOW Voltage GND Vth − 150 mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8 and 9) VIHD Differential Input HIGH Voltage 425 VCC − 850 mV VILD Differential Input LOW Voltage GND VCC − 1000 mV VID Differential Input Voltage (VIHD − VILD) 150 VCC − 850 mV Input Common Mode Range 350 VCC − 1000 mV VCMR HCSL OUTPUTS (Figure 4) VOH Output HIGH Voltage 600 740 900 mV VOL Output LOW Voltage −150 0 150 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Measurements taken with with outputs loaded 50 W to GND. Connect a 475 W resister from IREF (Pin 1) to GND. See Figure 6. 6. Vth is applied to the complementary input when operating in single ended mode per Figure 4. http://onsemi.com 5 NB3N121K Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; −40°C to +85°C (Note 7) Symbol VOUTPP tPLH, tPHL Characteristic Min Output Voltage Amplitude (@ VINPPmin) fin ≤ 400 MHz Propagation Delay (See Figure 3a) CLK/CLK to Qx/Qx DtPLH, DtPHL Propagation Delay Variations Per Each Diff Pair (Note 8) (See Figure 3a) CLK/CLK to Qx/Qx tSKEW Duty Cycle Skew (Note 9) Within -Device Skew Device to Device Skew (Note 10) tJIT VINPP VCROSS DVCROSS 550 Typ Max Unit 725 1000 mV 800 950 ps 100 20 100 150 Additive RMS Phase Jitter (Note 11) Fin = 100 MHz 0.1 ps ps ps Input Voltage Swing/Sensitivity (Differential Configuration) 150 VCC − 850 mV Absolute Crossing Magnitude Voltage (See Figure 3c) 250 550 mV 150 mV Variation in Magnitude of VCROSS (See Figure 3c) tr , tf Absolute Magnitude in Output Risetime and Falltime (from 175 mV to 525 mV) (See Figure 3b) Qx, Qx Dtr, Dtf Variation in Magnitude of Risetime and Falltime (Single−Ended) (See Figure 3b) Qx, Qx 100 340 700 125 ps ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. Connect a 475 W resister from IREF (Pin 1) to GND. All outputs loaded 50 W to GND per Figure 6. 8. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges per Figure 3. 9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+. 10. Skew is measured between outputs under identical conditions @ 50 MHz. 11. Phase noise integrated from 12 kHz to 20 MHz http://onsemi.com 6 NB3N121K QX CLK 525 mV VINPP = VIH(CLK) − VIL(CLK) = VIH(CLK) − VIL(CLK) 175 mV CLK tPLH tr Qx tPHL tf QX Qx 525 mV VOUTPP = VOH(Qx) − VOL(Q)x = VOH(Qx) − VOL(Qx) trMAX 175 mV Qx DtPLH Qx DtPHL tfMAX trMIN trMAX − trMIN = Dtr (a) Propagation Delay and Propagation Delay Variation tfMIN tfMAX − tfMIN = Dtf (b) tr, tf and Dtr, Dtf DVCROSS VCROSS (c) VCROSS and DVCROSS Figure 3. AC Reference Measurement VCC VIHDmax VILDmax VCMRmax CLK IN Vth VCMR IN CLK VCMRmin Vth VIHDtyp VILDtyp VIHDmin VILDmin VEE Figure 4. Single−Ended Interconnect Vth Reference Voltage Figure 5. Vth Diagram http://onsemi.com 7 VID = VIHD − VILD NB3N121K Qx RS1B Z0 = 50 W Receiver NB3N121K Driver RS2B Qx Z0 = 50 W CL1C 2 pF RL1D 50 W CL2C 2 pF RL2D 50 W RREFA A. Connect 475 W resistor RREF from IREF pin to GND. B. RS1, RS2: 0 W for Test and Evaluation. Select to Minimizing Ringing. C. CL1, CL2: Receiver Input Simulation (for test only not added to application circuit. D. RL1, RL2 Termination and Load Resistors Located at Receiver Inputs. Figure 6. Typical Termination Configuration for Output Driver and Device Evaluation VCC = 3.3 V / 2.5 V VCC = 3.3 V Z0 = 50 W CLK VCC = 3.3 V / 2.5 V / 1.8 V VCC = 3.3 V Z0 = 50 W CLK NB3N121K NB3N121K 50 W* LVPECL Driver 50 W* VTCLK LVDS Driver VTCLK Z0 = 50 W 50 W* CLK VTCLK Z0 = 50 W CLK 50 W* VTCLK = VTCLK VTCLK = VTCLK = VCC − 2.0 V GND VTCLK GND GND GND *RTIN, Internal Input Termination Resistor *RTIN, Internal Input Termination Resistor Figure 7. LVPECL Interface Figure 8. LVDS Interface http://onsemi.com 8 NB3N121K VCC = 3.3 V / 2.5 V / 1.8 V VCC = 3.3 V Z0 = 50 W CLK NB3N121K GND HCSL Driver VCC = 3.3 V / 2.5 V / 1.8 V VCC = 3.3 V Z0 = 50 W CLK 50 W* 50 W* VTCLK VTCLK LVCMOS/ LVTTL Driver VTCLK 50 W* Z0 = 50 W CLK VTCLK Vth VTCLK = VTCLK = GND GND GND GND *RTIN, Internal Input Termination Resistor VTCLK = OPEN VTCLK = OPEN CLK = Vth 100 W LVDS Device 100 W Zo = 50 W RL = 150 W IREF RL = 150 W RREF Figure 11. HCSL Interface Termination to LVDS 2.63 mA 14.2 mA IREF RREF 50 W* GND Figure 10. LVCMOS/LVTTL Interface Zo = 50 W NB3N121K Device Qx CLK *RTIN, Internal Input Termination Resistor Figure 9. Standard 50 W Load HCSL Interface Qx NB3N121K Qx 475 W RL1 Qx 50 W RL2 Figure 12. Simplified HCSL Output Structure http://onsemi.com 9 50 W NB3N121K ORDERING INFORMATION Package Shipping† NB3N121KMNG QFN−52 (Pb−Free) 260 Units / Tray NB3N121KMNR2G QFN−52 (Pb−Free) 2000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN52 8x8, 0.5P CASE 485M−01 ISSUE C 1 52 D SCALE 2:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ PIN ONE REFERENCE DATE 16 FEB 2010 B DIM A A1 A2 A3 b D D2 E E2 e K L E 2X 0.15 C 2X 0.15 C A2 0.10 C GENERIC MARKING DIAGRAM A 0.08 C SEATING PLANE A3 A1 1 REF C XXXXXXXXX XXXXXXXXX AWLYYWWG D2 14 52 X L 26 27 13 XXXXXXXXX A WL YY WW G E2 39 1 52 X K MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.18 0.30 8.00 BSC 6.50 6.80 8.00 BSC 6.50 6.80 0.50 BSC 0.20 --0.30 0.50 52 40 e 52 X b = Device Code = Assembly Site = Wafer Lot = Year = Work Week = Pb−Free Package RECOMMENDED SOLDERING FOOTPRINT NOTE 3 0.10 C A B 8.30 0.05 C 52X 0.62 6.75 6.75 PKG OUTLINE DOCUMENT NUMBER: DESCRIPTION: 98AON12057D 52 PIN QFN, 8X8, 0.5P 0.50 PITCH 8.30 52X 0.30 DIMENSIONS: MILLIMETERS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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