NB4N111KMNR4G

NB4N111K Clock Fanout Buffer, 1:10 Differential, 3.3 V, with HCSL Level Output Description http://onsemi.com The NB4N111K is a differential input clock 1 to 10 HCSL fanout buffer, optimized for ultra low propagation delay variation. The NB4N111K is designed with HCSL clock distribution for FBDIMM applications in mind. Inputs can accept differential VPECL, L CML, or VDS L levels. Single −ended LVPECL, CML, VCMOS L or VTTL L levels are accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12, and 13). Clock input pins incorporate an internal 50 W on die termination resistors. Outputs can interface with LVDS with proper termination (See Figure 15). The NB4N111K specifically guarantees low output–to–output skews. Optimal design, layout, and processing minimize skew within a device and from device to device. System designers can take advantage of the NB4N111K’s performance to distribute low skew clocks across the backplane or the motherboard. 1 QFN32 MN SUFFIX CASE 488AM 32 MARKING DIAGRAM* 32 1 NB4N 111K AWLYYWWG Features • Typical Input Clock Frequencies: 100, 133, 166, 200, 266, 333, and • • • • • • • 400 MHz 340 ps Typical Rise and Fall Times 800 ps Typical Propagation Delay Dtpd 100 ps Maximum Propagation Delay Variation Per Each Differential Pair 2 kV QFN32 Flammability Rating Oxygen Index: 28 to 34 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 622 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS (Note 3) Parameter Symbol Condition 1 Condition 2 Rating Unit VCC Positive Power Supply GND = 0 V 4.6 V VI Positive Input GND = 0 V GND − 0.3 v VI v VCC V VINPP Differential Input Voltage IOUT Output Current Continuous Surge TA Operating Temperature Range QFN32 Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm 500 lfpm QFN32 QFN32 qJC Thermal Resistance (Junction−to−Case) 2S2P (Note 4) QFN32 Tsol Wave Solder |CLK − CLK| Pb−Free VCC V 50 100 mA mA −40 to +70 °C −65 to +150 °C 31 27 °C/W °C/W 12 °C/W 265 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power). 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB4N111K Table 4. DC CHARACTERISTICS (VCC = 3.0 V to 3.6 V, TA = −40°C to +70°C Note 5) Symbol Characteristic IGND GND Supply Current (All Outputs Loaded) ICC Power Supply Current (All Outputs Loaded) IIH Input HIGH Current CLKx, CLKx IIL Input LOW Current CLKx, CLKx Min Typ Max Unit 70 98 120 mA 300 mA 150 mA 2.0 −150 −2.0 mA DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 5 and 7) Vth Input Threshold Reference Voltage Range (Note 6) 1050 VCC − 150 mV VIH Single−Ended Input HIGH Voltage Vth + 150 VCC mV VIL Single−Ended Input LOW Voltage GND Vth − 150 mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 8) VIHD Differential Input HIGH Voltage 1200 VCC mV VILD Differential Input LOW Voltage GND VCC − 75 mV VID Differential Input Voltage (VIHD − VILD) 75 2400 mV VCMR Input Common Mode Range 1163 VCC − 75 HCSL OUTPUTS (Figure 4) VOH Output HIGH Voltage 600 740 900 mV VOL Output LOW Voltage −150 0 150 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input parameters vary 1:1 with VCC. Measurements taken with all outputs loaded 50 W to GND, see Figure 9. 6. Vth is applied to the complementary input when operating in single ended mode. http://onsemi.com 4 NB4N111K Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; −40°C to +70°C (Note 7) Symbol Characteristic Typ Max Unit 725 1000 mV 800 1100 ps Propagation Delay Variations Variation Per Each Diff Pair CLK/CLK to Qx/Qx (Note 8) (See Figure 3) 100 ps tSKEW Duty Cycle Skew (Note 9) Within−Device Skew Device−to−Device Skew (Note 10) 20 100 150 ps ps ps tJITTER RMS Random Clock Jitter (Note 11) 1 ps Vcross Absolute Crossing Magnitude Voltage 550 mV DVcross Variation in Magnitude of Vcross 150 mV tr, tf Absolute Magnitude in Output Risetime and Falltime (From 175 mV to 525 mV) Qx, Qx 700 ps Dtr, Dtf Variation in Magnitude of Risetime and Falltime (Single−Ended) (See Figure 4) Qx, Qx 125 ps VOUTPP Output Voltage Amplitude (@ VINPPmin) tPLH, tPHL Propagation Delay to (See Figure 3) DtPLH, DtPHL Min fin = 400 MHz CLK/CLK to Qx/Qx 550 fin = 400 MHz 250 175 340 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. Measurements taken with all outputs loaded 50 W to GND, see Figure 9. Typical gain is 20 dB. 8. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges. 9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+. 10. Skew is measured between outputs under identical transition @ 400 MHz. 11. Additive RMS jitter with 50% duty cycle clock signal using phase noise integrated from 12 KHz to 33 MHz CLK VINPP = VIH(CLK) − VIL(CLK) = VIH(CLK) − VIL(CLK) CLK tPLH tPHL Q VOUTPP = VOH(Q) − VOL(Q) = VOH(Q) − VOL(Q) Q DtPHL DtPLH Figure 3. AC Reference Measurement http://onsemi.com 5 NB4N111K 525 mV DVCROSS VCROSS 175 mV tr tf Figure 4. HCSL Output Parameter Characteristics CLK CLK CLK CLK Vth Vth Figure 5. Differential Input Driven Single−Ended (Vth = VREFAC) VCC Vthmax Figure 6. Differential Inputs Driven Differentially VCC VCMmax VIHmax VILmax Vth Vthmin GND VIH Vth VIL VCMR VIHDmax VILDmax VID = VIHD − VILD VIHDtyp VILDtyp VIHmin VCMmin VILmin GND Figure 7. Vth Diagram VIHDmin VILDmin Figure 8. VCMR Diagram http://onsemi.com 6 NB4N111K Qx Z0 = 50 W RS1B Receiver HCSL Driver RS2B Z0 = 50 W Qx CL1C 2 pF IREFA CL2C 2 pF RL1 50 RL2 50 A. Connect IREF pin to GND. B. RS1, RS2: 0 W for Test and Evaluation. Select to Minimizing Ringing. C. CL1, CL2: Receiver Input Simulation Load Capacitance Only. Figure 9. Typical Termination Configuration for Output Driver and Device Evaluation CLx for Test Only (Representing Receiver Input Loading); Not Added to Application VCC = 3.3 V VCC = 3.3 V Z0 = 50 W LVPECL Driver VCC = 3.3 V Z0 = 50 W NB4N111K D 50 W* VTCLK LVDS Driver VTCLK Z0 = 50 W 50 W* D NB4N111K D 50 W* VTCLK VTCLK Z0 = 50 W VTCLK = VTCLK = VCC − 2.0 V GND VCC = 3.3 V 50 W* D VTCLK = VTCLK GND GND GND *RTIN, Internal Input Termination Resistor *RTIN, Internal Input Termination Resistor Figure 10. LVPECL Interface Figure 11. LVDS Interface http://onsemi.com 7 NB4N111K VCC VCC Z0 = 50 W VCC VCC NB4N111K D 50 W* Z0 = 50 W VTCLK CML Driver LVCMOS/ LVTTL Driver VTCLK Z0 = 50 W VCC 50 W* D VTCLK VTCLK 50 W* D Vth VTCLK = OPEN VTCLK = OPEN D = Vth VTCLK = VTCLK = VCC GND NB4N111K D 50 W* GND GND *RTIN, Internal Input Termination Resistor *RTIN, Internal Input Termination Resistor Figure 12. Standard 50 W Load CML Interface Figure 13. LVCMOS/LVTTL Interface VCC VDR INTQb INTQ Q Qb Figure 14. HCSL Output Structure HCSL Driver Qx Zo = 50 W 100 W Qx GND 100 W Zo = 50 W RL = 150 W RL = 150 W Figure 15. HCSL Interface Termination to LVDS http://onsemi.com 8 LVDS Receive NB4N111K ORDERING INFORMATION Package Shipping† NB4N111KMNG QFN32 (Pb−Free) 79 Units / Rail NB4N111KMNR4G QFN32 (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN32 5x5, 0.5P CASE 488AM ISSUE A 1 32 SCALE 2:1 A D PIN ONE LOCATION ÉÉ ÉÉ NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L B DATE 23 OCT 2013 L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E DIM A A1 A3 b D D2 E E2 e K L L1 0.15 C 0.15 C EXPOSED Cu A DETAIL B 0.10 C (A3) A1 0.08 C DETAIL A 9 32X L ALTERNATE CONSTRUCTION GENERIC MARKING DIAGRAM* K D2 1 XXXXXXXX XXXXXXXX AWLYYWWG G 17 8 MOLD CMPD DETAIL B SEATING PLANE C SIDE VIEW NOTE 4 ÉÉ ÉÉ ÇÇ TOP VIEW MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.18 0.30 5.00 BSC 2.95 3.25 5.00 BSC 2.95 3.25 0.50 BSC 0.20 −−− 0.30 0.50 −−− 0.15 E2 1 32 25 e e/2 32X b 0.10 M C A B 0.05 M C BOTTOM VIEW XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 5.30 32X 0.63 3.35 3.35 5.30 0.50 PITCH 32X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON20032D QFN32 5x5 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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