NB7L14MNGEVB

NB7L14MNGEVB NB7L14MNG Evaluation Board User's Manual http://onsemi.com Introduction ON Semiconductor has developed the QFN16EVB evaluation board for its high-performance devices packaged in the 16-pin QFN. This evaluation board was designed to provide a flexible and convenient platform to quickly evaluate, characterize and verify the operation of various ON Semiconductor products. Many QFN16EVBs are dedicated with a device already installed, and can be ordered from www.onsemi.com at the specific device web page. This evaluation board manual contains: • Information on 16-lead QFN Evaluation Board • Assembly Instructions • Appropriate Lab Setup • Bill of Materials EVAL BOARD USER’S MANUAL Board Layout The QFN16 Evaluation Board provides a high bandwidth, 50 W controlled impedance environment and is implemented in four layers. The first layer or primary trace layer is 0.008″ thick Rogers RO4003 material, and is designed to have equal electrical length on all signal traces from the device under test (DUT) pins to the SMA connectors. The second layer is the 1.0 oz copper ground plane and is primarily dedicated for the SMA connector ground plane. FR4 dielectric material is placed between the second and third layers and between third and fourth layers. The third layer is also 1.0 oz copper plane. A portion of this layer is designated for the device VCC and DUTGND power planes. The fourth layer is the secondary trace layer. This user’s manual provides detailed information on board contents, layout and its use. It should be used in conjunction with an appropriate ON Semiconductor device datasheet located at www.onsemi.com. The datasheet contains the technical device specifications. Top View Bottom View Figure 1. Top and Bottom View of the 16 QFN Evaluation Board © Semiconductor Components Industries, LLC, 2013 May, 2013 − Rev. 0 1 Publication Order Number: EVBUM2184/D NB7L14MNGEVB Pin 16 Pin 15 Pin 14 Pin 13 Figure 2. Enlarged Bottom View VEE/DUTGND VCC SMA_GND Pin 11 Pin 10 Pin 1 DUT_GND Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 SMA_GND Pin 12 Figure 3. Enlarged Bottom View of the Evaluation Board SILKSCREEN (TOP SIDE) LAYER 1 (TOP SIDE) 1 OZ ROGERS 4003 0.008 in LAYER 2 (GROUND PLANE P1) 1 OZ FR−4 0.020 in LAYER 3 (GROUND, VCC & VEE, PLANE P2) 1 OZ FR−4 0.025 in LAYER 4 (BOTTOM SIDE) 1 OZ Figure 4. Evaluation Board Layout, 4 Layer http://onsemi.com 2 0.062 ± 0.007 NB7L14MNGEVB Top View Bottom View Figure 5. Evaluation Board Layout Evaluation Board Assembly Instructions confusion with the use of this board, the negative supply connector is labeled VEE/DUTGND. SMAGND is the ground for the SMA connectors and is not to be confused with the device ground, VEE/DUTGND. SMAGND and DUTGND can be connected in single-supply applications. The power pin layout and typical connection of the evaluation board is shown in Figure 6. It is recommended to add bypass capacitors to reduce unwanted noise from the power supplies. Connect 0.1 mF capacitors from VCC and VEE/DUTGND to SMA_GND. The QFN−16 evaluation board is designed for characterizing devices in a 50 W laboratory environment using high bandwidth equipment. Each signal trace on the board has a via at the DUT pin, which provides an option of placing a termination resistor on the board bottom, depending on the input/output configuration (see Table 1, Configuration for Device: NB7L14). Table 4 contains the Bill of Materials for this evaluation board. The QFN16EVB was designed to accommodate a custom QFN−16 socket. Therefore, some external components are installed on the bottom side of the board. Output Loading/Termination ECL/PECL/LVPECL Outputs Solder the Device on the Evaluation Board Most ECL outputs are open emitter and need to be DC loaded and AC terminated to VCC − 2.0 V via a 50 W resistor. If no internal resistors are provided on the device, 0402 chip resistor pads are provided on the bottom side of the evaluation board to terminate the ECL driver. Solder the chip resistors to the bottom side of the board between the appropriate input device pads and the ground pads. If internal resistors are provided, the VT pins should be wired to SMAGND. (More information on termination is provided in AND8020). For standard ECL lab setup and test, a split (dual) power supply is recommended enabling the 50 W internal impedance in the oscilloscope, or other measuring instrument, to be used as an ECL output load/termination. By offsetting VCC = +2.0 V, SMAGND = VCC − 2.0 V, (SMAGND is the system ground, 0V); VCC is 2.0 V, and VEE/DUTGND is −3.0 V, −1.3 V or −0.5 V; see Table 2, Power Supply Levels). The soldering of a device to the evaluation board can be accomplished by hand soldering or solder reflow techniques using solder paste. Make sure pin 1 of the device is located properly and all the pins are aligned to the footprint pads. Solder the QFN−16 device to the evaluation board. As mentioned earlier, many QFN16EVBs are dedicated with a device already installed, and can be ordered from onsemi.com at the specific device web page. Connecting Power and Ground On the top side of the evaluation board, solder the four surface mount test point clips (anvils) to the pads labeled VCC, VEE/DUTGND, SMAGND, and ExPad. ExPad is connected to the exposed flag of the QFN package. For proper operation, the exposed flag is typically recommended to be tied to VEE/DUTGND, the negative supply of the device. The positive power supply connector is labeled VCC. Depending on the device, the negative power supply nomenclature is labeled either GND or VEE. To help avoid http://onsemi.com 3 NB7L14MNGEVB CML Outputs Installing the SMA Connectors Likewise, CML outputs need to be terminated to VCC via a 50 W resistor. If no internal resistors are provided on the device, 0402 chip resistor pads are provided on the bottom side of the evaluation board to terminate the CML driver. If internal resistors are provided, the VT pins should be wired to VCC. For CML lab setup and test, operation with negative supply voltages is recommended to enable the 50 W internal impedance in the oscilloscope, or other measuring instrument, to be used as a CML output termination; (VCC = 0 V, SMAGND = 0 V, and VEE/DUTGND = −5.0 V, −3.3 V, −2.5 V, or −1.8 V). Each configuration indicates the number of SMA connectors needed to populate an evaluation board for a given device. Each input and output requires one SMA connector. Install all the required SMA connectors onto the board and solder the center signal conductor pin to the board on J1 through J16. Please note that the alignment of the signal connector pin of the SMA connector to the metal trace on the board can influence lab results. The launch and reflection of the signals are largely influenced by imperfect alignment and soldering of the SMA connector. Validating the Assembled Board After assembling the evaluation board, it is recommended to perform continuity checks on all soldered areas before commencing with the evaluation process. Time Domain Reflectometry (TDR) is another highly recommended validation test. LVDS Outputs LVDS outputs are typically terminated with 100 W across the Q/Q output pair. The 100 W can be added on the QFN16EVB, but it is not provided on the board, since there are several user dependent LVDS output measurement techniques. For LVDS lab setup and test, a single supply is typically used, ie. VCC = 3.3 V and DUTGND = 0 V. http://onsemi.com 4 NB7L14MNGEVB NB7L14MNGEVB ASSEMBLY Table 1. CONFIGURATION FOR DEVICE: NB7L14 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SMA Connector Yes Yes Yes Yes No Yes Yes No Yes Yes Yes Yes No Yes Yes No Wire No No No No GND No No VCC No No No No VCC No No GND Device Pin # DUTGND/VEE = Exposed Pad and must be tied to DUTGND/VEE. CONFIGURATIONS J15 J14 J13 J16 J1 J12 VCC DUTGND/VEE J2 J11 DUT J10 J3 Exposed Pad SMAGND J4 J9 J5 J8 J6 Polarity of 22 mF: VCC + C4 − SMAGND 13 14 15 16 12 1 11 2 ExPad 10 3 9 4 8 7 J7 Top View VEE/DUTGND 6 SMAGND NOTE: 5 Bottom View Install 0.1 mF Decoupling Capacitors here and at package pins Figure 6. Power Supply Configuration for Device NB7L14 http://onsemi.com 5 + C2 − NB7L14MNGEVB NB7L14MNGEVB TEST Power Supply VCC VEE/DUTGND Test Measuring Equipment Differential Signal Generator VCC Out DUTGND/ VEE DUT Channel 1 Out Channel 2 ExPad SMAGND Trigger Trigger VEE/ GND (0 V) DUTGND Power Supply 1. Connect appropriate power supplies to VCC, VEE/DUTGND, SMAGND, and ExPad (see Table 2). 2. Connect a signal generator to the input SMA connectors. Setup input signal according to the device data sheet. 3. Connect a test measurement device to the device’s output SMA connectors. NOTE: The test measurement device must contain 50 W termination. Figure 7. Basic Lab Setup (Typical) Table 2. POWER SUPPLY LEVELS Outputs Power Supply VCC VEE/DUTGND SMAGND ExPad (typ) ECL/LVPECL 2.5 V +2.0 V −0.5 V 0V VEE/DUTGND ECL/LVPECL 3.3 V +2.0 V −1.3 V 0V VEE/DUTGND Table 3. NB7xxx, LVPECL OUTPUTS “SPLIT” POWER SUPPLY CONFIGURATION Dual Power Supplies Device Pin Power Supply Convertor “Spilt” Power Supply VCC VCC = +2.0 V SMAGND VTT = 0 V DUTGND DUTGND = −0.5 V or −1.3 V +2.0 V + VCC +1.3 V − + − DUTGND SMAGND +3.3 V Offset / “Split” Power Supply Configuration Figure 8. “Split” or Dual Power Supply Connections http://onsemi.com 6 NB7L14MNGEVB Table 4. BILL OF MATERIALS Manufacturer Description Part Number Qty Web Site SMA Connector Components Rosenberger SMA Connector, Side Launch, Gold Plated 32K243−40ME3 12 http://www.rosenberger.de http://www.rosenbergerna.com Surface Mount Test Points Keystone* SMT Miniature Test Point 5015 4 http://www.keyelco.com Chip Capacitor AVC Corporation* 0603 0.01 mF ±10% 06035C103KAT2A na http://www.avxcorp.com 0603 0.1 mF ±10% 0603C104KAT2A 8 Panasonic* 0402 50 W ±1% Precision Thick Film Chip Resistor ERJ−2RKF49R9X na http://www.panasonic.com Evaluation Board ON Semiconductor QFN 16 Evaluation Board QFN16EVB 1 http://www.onsemi.com Device Samples ON Semiconductor QFN 16 Package Device NB7L14MNG 1 http://www.onsemi.com Chip Resistor *Components are available through most distributors, i.e. www.newark.com, www.digikey.com http://onsemi.com 7 NB7L14MNGEVB Top Layer Second Layer (SMA_GND Plane) Figure 9. Gerber Files http://onsemi.com 8 NB7L14MNGEVB Third Layer (DUT_GND Trace) Bottom Layer Figure 10. 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