NB7VQ1006MMNHTBG

NB7VQ1006M 1.8V / 2.5V 10Gbps Equalizer Receiver with 1:6 Differential CML Outputs Multi−Level Inputs w/ Internal Termination Description http://onsemi.com MARKING DIAGRAM* 24 QFN−24 MN SUFFIX CASE 485L 1 NB7V Q1006M ALYWG G The NB7VQ1006M is a high performance differential 1:6 CML fanout buffer with a selectable Equalizer receiver. When placed in series with a Data path operating up to 10 Gb/s, the NB7VQ1006M will compensate the degraded data signal transmitted across a FR4 PCB backplane or cable interconnect and output six identical CML copies of the input signal. Therefore, the serial data rate is increased by reducing Inter−Symbol Interference (ISI) caused by losses in copper interconnect or long cables. The EQualizer ENable pin (EQEN) allows the IN/IN inputs to either flow through or bypass the Equalizer section. Control of the Equalizer function is realized by setting EQEN; When EQEN is set Low, the IN/IN inputs bypass the Equalizer. When EQEN is set High, the IN/IN inputs flow through the Equalizer. The default state at startup is LOW. As such, the NB7VQ1006M is ideal for SONET, GigE, Fiber Channel, Backplane and other Data distribution applications. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. This feature allows the NB7VQ1006M to accept various logic level standards, such as LVPECL, CML or LVDS. This feature provides transmission line termination at the receiver, eliminating external components. The outputs have the flexibility of being powered by either a 1.8 V or 2.5 V supply. The NB7VQ1006M is a member of the GigaComm™ family of high performance Clock/Data products. Features A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. EQ • • • • • • • • • • • Maximum Input Data Rate > 10 Gbps Maximum Input Clock Frequency > 7.5 GHz Backplane and Cable Interconnect Compensation 225 ps Typical Propagation Delay 30 ps Typical Rise and Fall Times Differential CML Outputs, 400 mV Peak−to−Peak, Typical Operating Range: VCC = 1.71 V to 2.625 V, GND = 0 V Internal Input Termination Resistors, 50 W QFN−24 Package, 4 mm x 4 mm −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices* SIMPLIFIED BLOCK DIAGRAM ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2010 June, 2010 − Rev. 2 1 Publication Order Number: NB7VQ1006M/D NB7VQ1006M CML Outputs Multi−Level Inputs LVPECL, LVDS, CML IN VT IN 50 W Q0 Q0 Q1 50 W 0 Q1 Q2 Q2 EQ Q3 1 Q3 Q4 EQEN (Equalizer Enable) Q4 75 kW Q5 Q5 Figure 1. Detailed Block Diagram of NB7VQ1006M Table 1. EQUALIZER ENABLE FUNCTION EQEN 0 1 Function IN/IN Inputs Bypass the EQualizer Section IN/IN Inputs Flow through the EQualizer Section GND 24 VCC IN IN VT EQEN VCC 1 2 3 4 5 6 7 GND 23 22 21 20 GND Q0 Q0 Q1 Q1 Exposed Pad (EP) 19 18 17 VCCO Q2 Q2 Q3 Q3 VCCO NB7VQ1006M 16 15 14 13 8 Q5 9 Q5 10 Q4 11 Q4 12 GND Figure 2. QFN−24 Lead Pinout (Top View) http://onsemi.com 2 NB7VQ1006M Table 2. PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 − Name VCC IN IN VT EQEN VCC GND Q5 Q5 Q4 Q4 GND VCCO Q3 Q3 Q2 Q2 VCCO GND Q1 Q1 Q0 Q0 GND EP − CML CML CML CML CML CML CML CML CML CML CML CML LVCMOS Input LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input I/O Positive Supply Voltage for the Core Logic Non−inverted Differential Clock/Data Input. (Note 1) Inverted Differential Clock/Data Input. (Note 1) Internal 50 W Termination Pin for IN and IN Equalizer Enable Input; pin will default LOW when left open (has internal pull−down resistor) Positive Supply Voltage for the Core Logic Negative Supply Voltage Inverted Differential Output. Typically terminated with 50 W resistor to VCC. Non−inverted Differential Output. Typically terminated with 50 W resistor to VCC. Inverted Differential Output. Typically terminated with 50 W resistor to VCC. Non−inverted Differential Output. Typically terminated with 50 W resistor to VCC. Negative Supply Voltage Positive Supply Voltage for the pre−amplifier and output buffer Inverted Differential Output. Typically terminated with 50 W resistor to VCC. Non−inverted Differential Output. Typically terminated with 50 W resistor to VCC. Inverted Differential Output. Typically terminated with 50 W resistor to VCC. Non−inverted Differential Output. Typically terminated with 50 W resistor to VCC. Positive Supply Voltage for the pre−amplifier and output buffer Negative Supply Voltage Inverted Differential Output. Typically terminated with 50 W resistor to VCC. Non−inverted Differential Output. Typically terminated with 50 W resistor to VCC. Inverted Differential Output. Typically terminated with 50 W resistor to VCC. Non−inverted Differential Output. Typically terminated with 50 W resistor to VCC. Negative Supply Voltage The Exposed Pad (EP) on the QFN−24 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to GND and is recommended to be electrically connected to GND on the PC board. Description 1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal is applied on IN/IN, then the device will be susceptible to self−oscillation. 2. All VCC, VCCO and GND pins must be externally connected to the same power supply voltage to guarantee proper device operation. http://onsemi.com 3 NB7VQ1006M Table 3. ATTRIBUTES Characteristics ESD Protection Moisture Sensitivity (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 Human Body Model Machine Model Value > 4 kV > 200 V Level 1 UL 94 V−0 @ 0.125 in 244 Table 4. MAXIMUM RATINGS Symbol VCC, VCCO VI VINPP IIN IOUT TA Tstg qJA Positive Power Supply Input Voltage Differential Input Voltage |IN − IN| Input Current Through RT (50 W Resistor) Output Current Through RT (50 W Resistor) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 4) TGSD 51−6 (2S2P Multilayer Test Board) with Filled Thermal Vias Thermal Resistance (Junction−to−Case) Wave Solder Pb−Free 0 lfpm 500 lfpm Standard Board QFN−24 QFN−24 QFN−24 Parameter Condition 1 GND = 0 V GND = 0 V Condition 2 Rating 3.0 −0.5 to VCC + 0.5 1.89 $40 $40 −40 to +85 −65 to +150 37 32 11 265 Unit V V V mA mA °C °C °C/W °C/W °C/W °C qJC Tsol Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 4 NB7VQ1006M Table 5. DC CHARACTERISTICS − CML OUTPUT VCC = VCCO = 1.71 V to 2.625 V; GND = 0 V TA = −40°C to 85°C Symbol Characteristic Min Typ Max Unit POWER SUPPLY CURRENT (Inputs and Outputs open) ICC ICCO Power Supply Current, Core Logic Power Supply Current, Outputs VCC = 2.5V VCC = 1.8V VCCO = 2.5V VCCO = 1.8V VCCO – 40 2460 1760 VCCO – 600 1900 VCCO – 525 1275 100 85 180 150 115 95 200 175 mA CML OUTPUTS (Notes 5 and 6) (Figure 10) VOH Output HIGH Voltage VCCO = 2.5 V VCCO = 1.8 V VCCO = 2.5V VCCO = 2.5V VCCO = 1.8V VCCO = 1.8V VCCO – 10 2490 1790 VCCO – 500 2000 VCCO – 425 1375 VCCO 2500 1800 VCCO – 400 2100 VCCO – 300 1500 mV VOL Output LOW Voltage mV DATA/CLOCK INPUTS (IN, IN) (Note 7) (Figures 6 & 7) VIHD VILD VID IIH IIL VIH VIL IIH IIL RTIN RTOUT Differential Input HIGH Voltage Differential Input LOW Voltage Differential Input Voltage (VIHD − VILD) Input HIGH Current Input LOW Current 1100 GND 100 −150 −150 30 −40 VCC VCC − 100 1200 +150 +150 mV mV mV mA mA CONTROL INPUTS (EQEN) Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current VCC x 0.65 GND −150 −150 25 10 VCC VCC x 0.35 +150 +150 mV mV mA mA TERMINATION RESISTORS Internal Input Termination Resistor Internal Output Termination Resistor 45 45 50 50 55 55 W W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. CML outputs loaded with 50 W to VCC for proper operation. 6. Input and output parameters vary 1:1 with VCC/VCCO. 7. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. http://onsemi.com 5 NB7VQ1006M Table 6. AC CHARACTERISTICS VCC = VCCO = 1.71 V to 2.625 V; GND = 0 V TA = −40°C to 85°C (Note 8) Symbol fDATA fMAX VOUTPP Characteristic Maximum Operating Input Data Rate Maximum Input Clock Frequency Output Voltage Amplitude EQEN = 0 or 1 (See Figures 4, Note 9) VCC = 2.5V VCC = 1.8V fin v 5.0 GHz VCC = 2.5V fin v 7.5 GHz VCC = 2.5V fin v 5 GHz VCC = 1.8V fin v 6.5 GHz VCC = 1.8V VCMR tPLH, tPHL tPLH TC tDC tSKEW Input Common Mode Range (Differential Configuration, Note 10) (Figure 8) Propagation Delay to Output Differential, IN/IN to Qn/Qn Propagation Delay Temperature Coefficient −40°C to +85°C Output Clock Duty Cycle Duty Cycle Skew (Note 11) Within Device Skew (Note 12) Device to Device Skew (Note 13) Random Clock Jitter RJ(RMS), 1000 cycles (Note 14) EQEN = 1fin v 5.0 GHz 5 GHz v fin v 7.5 GHz Deterministic Jitter (DJ) (Note 15) EQEN = 1, FR4 = 12”, v10 Gbps VCC = 2.5 V VCC = 1.8 V VINPP tr, tf Input Voltage Swing (Differential Configuration) (Note 16) (Figure 6) Output Rise/Fall Times Qn/Qn, (20% − 80%) 100 30 48 Min 10 7.5 6.5 275 225 225 200 1050 170 225 30 50 0.15 10 20 0.2 0.2 3 3 52 1 25 40 0.7 1.2 40 20 1200 65 mV ps 440 360 360 315 VCC − 50 315 mV ps fs/°C % ps Typ Max Unit Gbps GHz mV tJITTER ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Measured using a 400 mV source, 50% duty cycle 1GHz clock source. All outputs must be loaded with external 50 W to VCCO. Input edge rates 40 ps (20% − 80%). 9. Output voltage swing is a single−ended measurement operating in differential mode. 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. 11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 5 GHz. 12. Within device skew compares coincident edges. 13. Device to device skew is measured between outputs under identical transition 14. Additive CLOCK jitter with 50% duty cycle clock signal. 15. Additive Peak−to−Peak jitter with input NRZ data at PRBS23. 16. Input voltage swing is a single−ended measurement operating in differential mode, with minimum propagation change of 25 ps. 500 OUTPUT VOLTAGE AMPLITUDE (mV) 450 400 350 300 250 Q Output Amplitude (mV) VCC = 2.5 V VCC Q Output Amplitude (mV) VCC = 1.8 V IN 50 W VT 50 W IN 0 1 2 3 4 5 6 7 fIN, CLOCK INPUT FREQUENCY (GHz) 8 Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typ), (EQEN = 0) http://onsemi.com 6 Figure 4. Input Structure NB7VQ1006M IN IN Q Q tPLH VOUTPP = VOH(Q) − VOL(Q) tPHL VINPP = VIH(IN) − VIL(IN) IN IN VID = |VIHD(IN) − VILD(IN)| VIHD VILD Figure 5. Differential Inputs Driven Differentially Figure 6. AC Reference Measurement VCC VCM(MAX) VIHD(MAX) VILD(MAX) IN VIHD(TYP) VID = VIHD − VILD VILD(TYP) VIHD(MIN) VCMR IN VCM(MIN) GND VILD(MIN) Figure 7. VCMR Diagram VCCO 50 W Z = 50 W DUT Driver Device Q Z = 50 W Q 50 W D Receiver Device D Figure 8. Typical Termination for CML Output Driver and Device Evaluation http://onsemi.com 7 NB7VQ1006M VCCO VCC (Receiver) 50 W VCCO 50 W 100 W 50 W 50 W 50 W 50 W 16 mA GND 16 mA GND Figure 9. Typical CML Output Structure and Termination Figure 10. Alternative Output Termination APPLICATION INFORMATION VCC VT FR4 − 12 Inch Backplane NB7VQ1006M EQualizer Driver Q IN IN Q DJ1 DJ2 DJ3 Figure 11. Typical NB7VQ1006 Equalizer Application and Interconnect with PRBS23 pattern at 7.0 Gbps http://onsemi.com 8 NB7VQ1006M VCCx VCC VCC VCC ZO = 50 W LVPECL Driver VT NB7VQ1006M IN 50 W 50 W IN LVDS Driver ZO = 50 W VT = Open ZO = 50 W NB7VQ1006M IN 50 W 50 W IN ZO = 50 W GND VCCX = 2.5 V, VT = GND VCCX= 3.3 V, VT = 70 W to GND GND GND GND Figure 12. LVPECL Interface Figure 13. LVDS Interface VCC VCC VCC VCC ZO = 50 W CML Driver VT = VCC ZO = 50 W NB7VQ1006M IN 50 W 50 W IN Differential Driver ZO = 50 W VT = VREFAC* ZO = 50 W NB7VQ1006M IN 50 W 50 W IN GND GND GND Figure 14. Standard 50 W Load CML Interface Figure 15. Capacitor−Coupled Differential Interface (VT Connected to External VREFAC) GND *VREFAC bypassed to ground with a 0.01 mF capacitor ORDERING INFORMATION Device NB7VQ1006MMNG NB7VQ1006MMNHTBG NB7VQ1006MMNTXG Package QFN−24 (Pb−Free) QFN−24 (Pb−Free) QFN−24 (Pb−Free) Shipping† 92 Units / Rail 100 / Tape & Reel 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 NB7VQ1006M PACKAGE DIMENSIONS QFN24, 4x4, 0.5P CASE 485L−01 ISSUE A D PIN 1 IDENTIFICATION A B E 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.20 0.30 4.00 BSC 2.70 2.90 4.00 BSC 2.70 2.90 0.50 BSC 0.30 0.50 0.15 C 2X 0.15 C A2 0.10 C A 0.08 C SEATING PLANE A1 D2 L 7 6 A3 REF C DIM A A1 A2 A3 b D D2 E E2 e L e 12 13 E2 24X b 1 24 19 18 0.10 C A B 0.05 C e GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 10 NB7VQ1006M/D