NB7VQ1006MMNG

NB7VQ1006M 1.8 V / 2.5 V 10 Gbps Equalizer Receiver with 1:6 Differential CML Outputs Multi-Level Inputs W / Internal Termination www.onsemi.com Description The NB7VQ1006M is a high performance differential 1:6 CML fanout buffer with a selectable Equalizer receiver. When placed in series with a Data path operating up to 10 Gb/s, the NB7VQ1006M will compensate the degraded data signal transmitted across a FR4 PCB backplane or cable interconnect and output six identical CML copies of the input signal. Therefore, the serial data rate is increased by reducing Inter-Symbol Interference (ISI) caused by losses in copper interconnect or long cables. The EQualizer ENable pin (EQEN) allows the IN/IN inputs to either flow through or bypass the Equalizer section. Control of the Equalizer function is realized by setting EQEN; When EQEN is set Low, the IN/IN inputs bypass the Equalizer. When EQEN is set High, the IN/IN inputs flow through the Equalizer. The default state at startup is LOW. As such, the NB7VQ1006M is ideal for SONET, GigE, Fiber Channel, Backplane and other Data distribution applications. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. This feature allows the NB7VQ1006M to accept various logic level standards, such as LVPECL, CML or LVDS. This feature provides transmission line termination at the receiver, eliminating external components. The outputs have the flexibility of being powered by either a 1.8 V or 2.5 V supply. The NB7VQ1006M is a member of the GigaComm™ family of high performance Clock/Data products. QFN−24 MN SUFFIX CASE 485L MARKING DIAGRAM* 24 1 NB7V Q1006M ALYWG G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. SIMPLIFIED BLOCK DIAGRAM Features • • • • • • • • • • • Maximum Input Data Rate > 10 Gbps Maximum Input Clock Frequency > 7.5 GHz Backplane and Cable Interconnect Compensation 225 ps Typical Propagation Delay 30 ps Typical Rise and Fall Times Differential CML Outputs, 400 mV Peak-to-Peak, Typical Operating Range: VCC = 1.71 V to 2.625 V, GND = 0 V Internal Input Termination Resistors, 50 W QFN−24 Package, 4 mm x 4 mm −40°C to +85°C Ambient Operating Temperature This Device is Pb-Free, Halogen Free and is RoHS Compliant EQ ORDERING INFORMATION Device Package Shipping† NB7VQ1006MMNG QFN−24 (Pb-Free) 92 Units / Tube NB7VQ1006MMNTXG QFN−24 3000 Tape & Reel (Pb-Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 August, 2016 − Rev. 3 1 Publication Order Number: NB7VQ1006M/D NB7VQ1006M CML Outputs Q0 Multi−Level Inputs LVPECL, LVDS, CML IN Q0 Q1 Q1 50 W VT IN 0 50 W Q2 Q2 Q3 EQ 1 Q3 Q4 Q4 75 kW Q5 Q5 Figure 1. Detailed Block Diagram of NB7VQ1006M Table 1. EQUALIZER ENABLE FUNCTION EQEN Function Q1 Q1 GND IN/IN Inputs Flow through the EQualizer Section Q0 1 Q0 IN/IN Inputs Bypass the EQualizer Section GND 0 24 23 22 21 20 19 Exposed Pad (EP) VCC 1 18 VCCO IN 2 17 Q2 IN 3 16 Q2 VT 4 15 Q3 EQEN 5 14 Q3 VCC 6 13 VCCO Q5 10 11 12 GND 9 Q4 8 Q4 7 Q5 NB7VQ1006M GND EQEN (Equalizer Enable) Figure 2. QFN−24 Lead Pinout (Top View) www.onsemi.com 2 NB7VQ1006M Table 2. PIN DESCRIPTION Pin Name 1 VCC I/O Description 2 IN LVPECL, CML, LVDS Input Non-inverted Differential Clock/Data Input. (Note 1) 3 IN LVPECL, CML, LVDS Input Inverted Differential Clock/Data Input. (Note 1) Positive Supply Voltage for the Core Logic 4 VT 5 EQEN 6 VCC Positive Supply Voltage for the Core Logic 7 GND Negative Supply Voltage 8 Q5 CML Inverted Differential Output. Typically terminated with 50 W resistor to VCC. 9 Q5 CML Non-inverted Differential Output. Typically terminated with 50 W resistor to VCC. 10 Q4 CML Inverted Differential Output. Typically terminated with 50 W resistor to VCC. CML Non-inverted Differential Output. Typically terminated with 50 W resistor to VCC. Internal 50 W Termination Pin for IN and IN LVCMOS Input Equalizer Enable Input; pin will default LOW when left open (has internal pull-down resistor) 11 Q4 12 GND 13 VCCO 14 Q3 CML Inverted Differential Output. Typically terminated with 50 W resistor to VCC. 15 Q3 CML Non-inverted Differential Output. Typically terminated with 50 W resistor to VCC. 16 Q2 CML Inverted Differential Output. Typically terminated with 50 W resistor to VCC. 17 Q2 CML Non-inverted Differential Output. Typically terminated with 50 W resistor to VCC. 18 VCCO 19 GND 20 Q1 CML Inverted Differential Output. Typically terminated with 50 W resistor to VCC. 21 Q1 CML Non-inverted Differential Output. Typically terminated with 50 W resistor to VCC. 22 Q0 CML Inverted Differential Output. Typically terminated with 50 W resistor to VCC. 23 Q0 CML Non-inverted Differential Output. Typically terminated with 50 W resistor to VCC. 24 GND − EP Negative Supply Voltage Positive Supply Voltage for the pre-amplifier and output buffer Positive Supply Voltage for the pre-amplifier and output buffer Negative Supply Voltage Negative Supply Voltage − The Exposed Pad (EP) on the QFN−24 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is electrically connected to GND and is recommended to be electrically connected to GND on the PC board. 1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal is applied on IN/IN, then the device will be susceptible to self-oscillation. 2. All VCC, VCCO and GND pins must be externally connected to the same power supply voltage to guarantee proper device operation. www.onsemi.com 3 NB7VQ1006M Table 3. ATTRIBUTES Characteristics Value ESD Protection Human Body Model Machine Model > 4 kV > 200 V Moisture Sensitivity (Note 1) Level 1 Flammability Rating Oxygen Index: 28 to 34 Transistor Count UL 94 V−0 @ 0.125 in 244 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol VCC, VCCO VI VINPP IIN IOUT Parameter Condition 1 Condition 2 Rating Unit Positive Power Supply GND = 0 V 3.0 V Input Voltage GND = 0 V −0.5 to VCC + 0.5 V Differential Input Voltage |IN−IN| 1.89 V Input Current Through RT (50 W Resistor) $40 mA Output Current Through RT (50 W Resistor) $40 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) (Note 1) TGSD 51−6 (2S2P Multilayer Test Board) with Filled Thermal Vias qJC Thermal Resistance (Junction-to-Case) Tsol Wave Solder (Pb-Free) 0 lfpm 500 lfpm QFN−24 QFN−24 37 32 °C/W Standard Board QFN−24 11 °C/W 265 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. www.onsemi.com 4 NB7VQ1006M Table 5. DC CHARACTERISTICS − CML OUTPUT (VCC = VCCO = 1.71 V to 2.625 V; GND = 0 V TA = −40°C to 85°C) Symbol Characteristic Min Typ Max Unit 115 95 mA POWER SUPPLY CURRENT (Inputs and Outputs open) ICC ICCO Power Supply Current, Core Logic VCC = 2.5V VCC = 1.8V Power Supply Current, Outputs VCCO = 2.5V VCCO = 1.8V 100 85 180 150 200 175 CML OUTPUTS (Notes 1 and 2) (Figure 10) VOH Output HIGH Voltage VCCO = 2.5 V VCCO = 1.8 V VCCO – 40 2460 1760 VCCO – 10 2490 1790 VCCO 2500 1800 VOL Output LOW Voltage VCCO = 2.5V VCCO = 2.5V VCCO = 1.8V VCCO = 1.8V VCCO – 600 1900 VCCO – 525 1275 VCCO – 500 2000 VCCO – 425 1375 VCCO – 400 2100 VCCO – 300 1500 mV mV DATA/CLOCK INPUTS (IN, IN) (Note 3) (Figures 6 & 7) VIHD Differential Input HIGH Voltage 1100 VCC mV VILD Differential Input LOW Voltage GND VCC − 100 mV VID Differential Input Voltage (VIHD − VILD) 100 1200 mV IIH Input HIGH Current −150 30 +150 mA IIL Input LOW Current −150 −40 +150 mA CONTROL INPUTS (EQEN) VIH Input HIGH Voltage VCC x 0.65 VCC mV VIL Input LOW Voltage GND VCC x 0.35 mV IIH Input HIGH Current −150 25 +150 mA IIL Input LOW Current −150 10 +150 mA Internal Input Termination Resistor 45 50 55 W Internal Output Termination Resistor 45 50 55 W TERMINATION RESISTORS RTIN RTOUT NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. CML outputs loaded with 50 W to VCC for proper operation. 2. Input and output parameters vary 1:1 with VCC/VCCO. 3. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. www.onsemi.com 5 NB7VQ1006M Table 6. AC CHARACTERISTICS (VCC = VCCO = 1.71 V to 2.625 V; GND = 0 V TA = −40°C to 85°C (Note 1)) Symbol Characteristic Min fDATA Maximum Operating Input Data Rate 10 fMAX Maximum Input Clock Frequency VCC = 2.5V VCC = 1.8V 7.5 6.5 Output Voltage Amplitude EQEN = 0 or 1 fin v 5.0 GHz VCC = 2.5V fin v 7.5 GHz VCC = 2.5V (See Figures 4, Note 2) fin v 5 GHz VCC = 1.8V fin v 6.5 GHz VCC = 1.8V 275 225 225 200 VCMR Input Common Mode Range (Differential Configuration, Note 3) (Figure 8) 1050 tPLH, tPHL Propagation Delay to Output Differential, IN/IN to Qn/Qn 170 VOUTPP tPLH TC tDC Propagation Delay Temperature Coefficient −40°C to +85°C Output Clock Duty Cycle Typ Max GHz mV 440 360 360 315 225 VCC − 50 mV 315 ps 30 48 fs/°C 50 52 % ps tSKEW Duty Cycle Skew (Note 4) Within Device Skew (Note 5) Device to Device Skew (Note 6) 0.15 10 20 1 25 40 tJITTER Random Clock Jitter RJ(RMS), 1000 cycles (Note 7) EQEN = 1fin v 5.0 GHz 5 GHz v fin v 7.5 GHz 0.2 0.2 0.7 1.2 3 3 40 20 Deterministic Jitter (DJ) (Note 8) EQEN = 1, FR4 = 12”, v10 Gbps VCC = 2.5 V VCC = 1.8 V VINPP tr, tf Input Voltage Swing (Differential Configuration) (Note 9) (Figure 6) Output Rise/Fall Times Qn/Qn, (20%−80%) Unit Gbps 100 30 ps 1200 mV 65 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Measured using a 400 mV source, 50% duty cycle 1GHz clock source. All outputs must be loaded with external 50 W to VCCO. Input edge rates 40 ps (20% − 80%). 2. Output voltage swing is a single ended measurement operating in differential mode. 3. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. 4. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 5 GHz. 5. Within device skew compares coincident edges. 6. Device to device skew is measured between outputs under identical transition 7. Additive CLOCK jitter with 50% duty cycle clock signal. 8. Additive Peak-to-Peak jitter with input NRZ data at PRBS23. 9. Input voltage swing is a single-ended measurement operating in differential mode, with minimum propagation change of 25 ps. www.onsemi.com 6 NB7VQ1006M OUTPUT VOLTAGE AMPLITUDE (mV) 500 Q Output Amplitude (mV) VCC = 2.5 V 450 400 VCC Q Output Amplitude (mV) VCC = 1.8 V IN 350 50 W VT 300 50 W 250 IN 0 1 2 3 4 5 6 7 fIN, CLOCK INPUT FREQUENCY (GHz) 8 Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typ), (EQEN = 0) Figure 4. Input Structure IN IN IN VINPP = VIH(IN) − VIL(IN) IN VID = |VIHD(IN) − VILD(IN)| Q VIHD VILD VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 5. Differential Inputs Driven Differentially Figure 6. AC Reference Measurement VCC VIHD(MAX) VCM(MAX) VILD(MAX) IN VIHD(TYP) VID = VIHD − VILD VCMR IN VILD(TYP) VIHD(MIN) VCM(MIN) GND VILD(MIN) Figure 7. VCMR Diagram www.onsemi.com 7 NB7VQ1006M VCCO 50 W Z = 50 W DUT Driver Device 50 W Q D Receiver Device Z = 50 W Q D Figure 8. Typical Termination for CML Output Driver and Device Evaluation VCCO 50 W VCCO VCC (Receiver) 50 W 50 W 50 W 50 W 50 W 100 W 16 mA 16 mA GND GND Figure 9. Typical CML Output Structure and Termination Figure 10. Alternative Output Termination www.onsemi.com 8 NB7VQ1006M APPLICATION INFORMATION VCC VT Driver FR4 − 12 Inch Backplane Q NB7VQ1006M EQualizer IN IN Q DJ1 DJ2 DJ3 Figure 11. Typical NB7VQ1006 Equalizer Application and Interconnect with PRBS23 pattern at 7.0 Gbps www.onsemi.com 9 NB7VQ1006M VCCx NB7VQ1006M ZO = 50 W LVPECL Driver VCC VCC ZO = 50 W ZO = 50 W IN 50 W VT VCC LVDS Driver 50 W VCC GND Figure 13. LVDS Interface VCC VCC VCC NB7VQ1006M ZO = 50 W IN 50 W VT = VCC ZO = 50 W Differential Driver 50 W IN GND 50 W GND GND Figure 12. LVPECL Interface CML Driver 50 W IN VCCX = 2.5 V, VT = GND VCCX= 3.3 V, VT = 70 W to GND ZO = 50 W IN VT = Open ZO = 50 W IN GND NB7VQ1006M NB7VQ1006M IN 50 W VT = VREFAC* ZO = 50 W 50 W IN GND GND GND Figure 15. Capacitor-Coupled Differential Interface (VT Connected to External VREFAC) Figure 14. Standard 50 W Load CML Interface *VREFAC bypassed to ground with a 0.01 mF capacitor ECLinPS is a trademark of Semiconductor Components Industries, GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN24, 4x4, 0.5P CASE 485L ISSUE B 1 24 SCALE 2:1 D PIN 1 REFEENCE 2X 0.15 C 2X ÉÉÉ ÉÉÉ ÉÉÉ 0.15 C DETAIL A E ALTERNATE CONSTRUCTIONS ÉÉÉ ÉÉÉ ÇÇÇ EXPOSED Cu DETAIL B 0.10 C SEATING PLANE L 24X 7 DIM A A1 A3 b D D2 E E2 e L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 4.00 BSC 2.70 2.90 4.00 BSC 2.70 2.90 0.50 BSC 0.30 0.50 0.05 0.15 XXXXX XXXXX ALYWG G 13 E2 1 24 A1 A3 GENERIC MARKING DIAGRAM* D2 DETAIL A ÉÉ ÉÉ ÇÇ ALTERNATE TERMINAL CONSTRUCTIONS C A1 SIDE VIEW MOLD CMPD DETAIL B A A3 NOTE 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L1 TOP VIEW 0.08 C L L A B DATE 05 JUN 2012 19 e e/2 24X b 0.10 C A B 0.05 C BOTTOM VIEW NOTE 3 RECOMMENDED SOLDERING FOOTPRINT 4.30 24X 0.55 2.90 XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 1 4.30 2.90 0.50 PITCH 24X 0.32 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98AON11783D QFN24, 4X4, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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