1.8 V/2.5 V/3.3 V
8 GHz/14 Gbps Differential
1:4 Clock/Data CML Fanout
Buffer w/ Selectable Input
Equalizer
Multi−Level Inputs w/ Internal Termination
www.onsemi.com
NB7VQ14M
MARKING
DIAGRAM*
16
Description
The NB7VQ14M is a high performance differential 1:4 CML fanout
buffer with a selectable Equalizer receiver. When placed in series with
a Clock /Data path operating up to 8 GHz or 14 Gb/s, respectively, the
NB7VQ14M inputs will compensate the degraded signal transmitted
across a FR4 PCB backplane or cable interconnect and output four
identical CML copies of the input signal with a 1.8 V, 2.5 V or 3.3 V
power supply. Therefore, the serial data rate is increased by reducing
Inter−Symbol Interference (ISI) caused by losses in copper
interconnect or long cables. The EQualizer ENable pin (EQEN)
allows the IN/IN inputs to either flow through or bypass the Equalizer
section. Control of the Equalizer function is realized by setting EQEN;
When EQEN is set Low, the IN/IN inputs bypass the Equalizer. When
EQEN is set High, the IN/IN inputs flow through the Equalizer. The
default state at start−up is LOW. As such, NB7VQ14M is ideal for
SONET, GigE, Fiber Channel, Backplane and other Clock/Data
distribution applications.
The differential inputs incorporate internal 50 W termination
resistors that are accessed through the VT pin. This feature allows the
NB7VQ14M to accept various logic level standards, such as LVPECL,
CML or LVDS. The 1:4 fanout design was optimized for low output
skew applications.
The NB7VQ14M is a member of the GigaComm™ family of high
performance clock products.
1
1
QFN−16
MN SUFFIX
CASE 485G
A
L
Y
W
G
NB7V
Q14M
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
SIMPLIFIED BLOCK DIAGRAM
EQ
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Data Rate > 14 Gb/s, Typical
Input Clock Frequency > 8 GHz, Typical
165 ps Typical Propagation Delay
30 ps Typical Rise and Fall Times
< 15 ps Maximum Output Skew
< 0.8 ps Maximum RMS Clock Jitter
< 10 ps pp of Data Dependent Jitter
Differential CML Outputs, 400 mV Peak−to−Peak, Typical
Selectable Input Equalization
Operating Range: VCC = 1.71 V to 3.6 V with GND = 0 V
Internal Input Termination Resistors, 50 W
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2010
May, 2021 − Rev. 1
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Publication Order Number:
NB7VQ14M/D
NB7VQ14M
Multi−Level Inputs
LVPECL, LVDS, CML
CML Outputs
Q0
IN
Q0
50 W
VT
0
50 W
IN
Q1
Q1
2:1
MUX
VREFAC
VCC
EQ
Q2
1
Q2
GND
Q3
Q3
EQEN
(Equalizer Enable)
75 kW
Figure 1. Detailed Block Diagram of NB7VQ14M
GND Q0
16
IN
1
VT
2
15
Q0
VCC Exposed Pad (EP)
14
13
EQEN
12 Q1
VREFAC 3
IN / IN Inputs By−pass the Equalizer section
1
Inputs flow through the Equalizer
10 Q2
4
9
5
6
EQEN Q3
7
8
Q3
VCC
Q2
Figure 2. QFN−16 Pinout (Top View)
www.onsemi.com
2
Function
0
11 Q1
NB7VQ14M
IN
Table 1. EQUALIZER ENABLE FUNCTION
NB7VQ14M
Table 2. PIN DESCRIPTION
Pin
Name
I/O
1
IN
LVPECL, CML,
LVDS Input
Description
Non−inverted Differential Input. (Note 1)
2
VT
3
VREFAC
4
IN
LVPECL, CML,
LVDS Input
Inverted Differential Input. (Note 1)
5
EQEN
LVCMOS Input
Equalizer Enable Input; pin will default LOW when left open (has internal pull−down resistor)
6
Q3
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
7
Q3
CML Output
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
8
VCC
−
9
Q2
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
10
Q2
CML Output
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
Internal 100 W Center−tapped Termination Pin for IN / IN
Output Voltage Reference for Capacitor−Coupled Inputs, only
Positive Supply Voltage
11
Q1
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
12
Q1
CML Output
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
13
VCC
−
14
Q0
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
15
Q0
CML Output
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
16
GND
−
Negative Supply Voltage
−
EP
−
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is electrically connected to the die, and must be electrically and thermally
connected to GND on the PC board.
Positive Supply Voltage
1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal
is applied on IN / IN input, then, the device will be susceptible to self−oscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
www.onsemi.com
3
NB7VQ14M
Table 3. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
> 2 kV
> 200 V
RPD − EQEN Input Pulldown Resistor
75 kW
Moisture Sensitivity (Note 3)
16−QFN
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
210
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
VCC
Positive Power Supply − Core
VIO
Positive Input/Output Voltage
VINPP
IIN
IOUT
Condition 2
Rating
Unit
GND = 0 V
4.0
V
GND = 0 V
−0.5 to VCC + 0.5
V
Differential Input Voltage |IN − IN|
1.89
V
Input Current Through RT (50 W Resistor)
±40
mA
Output Current Through RT (50 W Resistor)
±40
mA
IVFREFAC
VREFAC Sink/Source Current
±1.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
θJA
Thermal Resistance (Junction−to−Ambient)
(Note 4)
16 QFN
16 QFN
42
35
°C/W
°C/W
θJC
Thermal Resistance (Junction−to−Case) (Note 4)
16 QFN
4
°C/W
Tsol
Wave Solder
265
°C
16 QFN
0 lfpm
500 lfpm
Pb−Free
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
www.onsemi.com
4
NB7VQ14M
Table 5. DC CHARACTERISTICS, MULTI−LEVEL INPUTS VCC = 1.71 V to 3.6 V, GND = 0 V, TA = −40°C to 85°C (Note 5)
Symbol
Characteristic
Min
Typ
Max
Unit
3.135
2.375
1.71
3.3
2.5
1.8
3.6
2.625
1.89
V
170
210
mA
POWER SUPPLY CURRENT
VCC
Power Supply Voltage
ICC
Power Supply Current (Inputs and Outputs Open)
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
CML OUTPUTS (Note 6)
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
VCC – 30
3270
2470
1770
VCC – 5
3295
2495
1795
VCC
3300
2500
1800
mV
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
VCC – 525
2775
1975
1275
VCC – 425
2875
2075
1375
VCC – 325
2975
2175
1475
mV
VCC
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 5 and 7) (Note 7)
VIH
Single−ended Input HIGH Voltage
Vth + 100
VIL
Single−ended Input LOW Voltage
GND
Vth −100
mV
Vth
Input Threshold Reference Voltage Range (Note 8)
1050
VCC − 100
mV
Single−ended Input Voltage Amplitude (VIH − VIL)
200
2800
mV
VCC – 350
2950
2150
1450
mV
1200
VCC
mV
VISE
VREFAC
VREFAC
Output Reference Voltage @ 100 mA for capacitor* coupled inputs,
only (Note 9)
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
VCC – 650
2650
1850
1150
VCC – 500
2800
2000
1300
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 6 and 8) (Note 9)
VIHD
Differential Input HIGH Voltage
VILD
Differential Input LOW Voltage
0
VIHD − 100
mV
VID
Differential Input Voltage (VIHD − VILD)
100
1200
mV
Input Common Mode Range (Differential Configuration) (Note 10)
(Figure 9)
1050
VCC − 50
mV
IIH
Input HIGH Current IN / IN, (VT Open)
−150
150
mA
IIL
Input LOW Current IN / IN, (VT Open)
−150
150
mA
VCMR
CONTROL INPUTS (EQEN)
VIH
Input HIGH Voltage for Control Pins
VCC x 0.65
VCC
V
VIL
Input LOW Voltage for Control Pins
GND
VCC x 0.35
V
IIH
Input HIGH Current
−150
150
mA
IIL
Input LOW Current
−150
150
mA
TERMINATION RESISTORS
RTIN
RTOUT
Internal Input Termination Resistor
45
50
55
W
Internal Output Termination Resistor
45
50
55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
5. Input and output parameters vary 1:1 with VCC.
6. CML outputs loaded with 50 W to VCC for proper operation.
7. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. VIHD, VILD, VID, and VCMR parameters must be complied with simultaneously.
10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the crosspoint side of the differential input
signal.
www.onsemi.com
5
NB7VQ14M
Table 6. AC CHARACTERISTICS VCC = 1.71 V to 3.6 V, GND = 0 V, TA = −40°C to 85°C (Note 11)
Symbol
fMAX
fDATAMAX
VOUTPP
Characteristic
Maximum Input Clock Frequency;
Typ
7
8.5
GHz
10
14
Gbps
fin ≤ 7 GHz
200
400
mV
IN to Qx
125
175
225
ps
3
15
15
50
ps
50
60
%
Maximum Operating Data Rate NRZ, (PRBS23)
Output Voltage Amplitude, EQEN = 0 or 1 (Note 15)
(See Figure 10)
tPLH,
tPHL
Propagation Delay
tSKEW
Duty Cycle Skew (Note 12)
Output – Output Within Device Skew
Device to Device Skew
tDC
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
FN
Phase Noise, fin = 1 GHz
tŐFN
Integrated Phase Jitter fin = 1 GHz, 12 kHz − 20 MHz
Offset (RMS)
tJITTER
Min
VOUT ≥ 200 mV
fin ≤ 7 GHz
40
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
RMS Random Clock Jitter (Note 13)
fin ≤ 7 GHz
tr
tf
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 15)
dBc
35
fs
0.2
100
Output Rise/Fall Times @ 1.0 GHz
(20% − 80%)
Qx, Qx
15
Unit
−134
−136
−150
−151
−151
−151
Peak−to−Peak Data Dependent Jitter (Note 14)
fIN ≤ 14 Gbps EQEN = 0 (≤ 3” FR4)
fIN ≤ 10 Gbps EQEN = 1 (12” FR4)
VINPP
Max
30
0.8
ps rms
10
10
ps pk−pk
ps pk−pk
1200
mV
45
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
11. Measured by forcing VINPP 400mV from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps
(20% − 80%).
12. Skew is measured between outputs under identical transitions and conditions @ 0.5 GHz. Duty cycle skew is measured between differential
outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz.
13. Additive RMS jitter with 50% duty cycle clock signal.
14. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS23.
15. Input and output voltage swings are single−ended measurements operating in a differential mode.
OUTPUT VOLTAGE AMPLITUDE
(mV)
600
500
Q AMP (mV)
400
300
200
100
0
0
1
2
3
4
5
6
7
8
fin, CLOCK INPUT FREQUENCY (GHz)
9
10
Figure 3. CLOCK Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typical)
www.onsemi.com
6
NB7VQ14M
VCC
IN
50 W
VT
50 W
IN
Figure 4. Input Structure
IN
VIH
IN
Vth
VIL
IN
IN
Vth
Figure 5. Differential Input Driven
Single−Ended
VCC
Vthmax
Figure 6. Differential Inputs
Driven Differentially
VIHmax
VILmax
Vth
IN
Vthmin
GND
VIH
Vth
VIL
IN
IN
VCMRmax
VILmin
VIHD(MAX)
Figure 8. Differential Inputs Driven Differentially
INx
VILD(MAX)
VINPP = VIH(IN) − VIL(IN)
INx
VCMR
VIHD
VID = VIHD − VILD
Q
VILD
VCMRmin
GND
VILD
VIHmin
Figure 7. Vth Diagram
VCC
VID = |VIHD(IN) − VILD(IN)|
VIHD
VOUTPP = VOH(Q) − VOL(Q)
Q
VIHD(MIN)
tPHL
tPLH
VILD(MIN)
Figure 9. VCMR Diagram
Figure 10. AC Reference Measurement
www.onsemi.com
7
NB7VQ14M
VCC
VCC
NB7VQ14M
ZO = 50 W
LVPECL
Driver
VCC
VCC
ZO = 50 W
IN
50 W
VT = VCC − 2 V
ZO = 50 W
LVDS
Driver
50 W
50 W
50 W
IN
GND/VEE
GND
GND
GND
Figure 11. LVPECL Interface
Figure 12. LVDS Interface
VCC
VCC
CML
Driver
IN
VT = Open
ZO = 50 W
IN
VCC
VCC
NB7VQ14M
ZO = 50 W
NB7VQ14M
ZO = 50 W
IN
50 W
VT = VCC
ZO = 50 W
Differential
Driver
50 W
IN
NB7VQ14M
IN
50 W
VT = VREFAC*
ZO = 50 W
50 W
IN
GND
GND
GND
GND
Figure 14. Capacitor−Coupled
Differential Interface
(VT Connected to VREFAC)
Figure 13. Standard 50 W Load CML Interface
*VREFAC bypassed to ground with a 0.01 mF capacitor
VCC
VCC
ZO = 50 W
Differential
Driver
NB7VQ14M
IN
50 W
VT = VREFAC*
50 W
IN
GND
Figure 15. Capacitor−Coupled
Single−Ended Interface
(VT Connected to VREFAC)
www.onsemi.com
8
GND
NB7VQ14M
NB7VQ14M
Receiver
VCC
VCC =
VCC (Receiver)
50 W
50 W
VCC (Receiver)
50 W
50 W
16 mA
GND
Figure 16. Typical CML Output Structure
and Termination
VCC
VT
Driver
FR4 − 12 Inch Backplane
Q
NB7VQ14M
EQualizer
EQEN = 1
IN
IN
Q
DJ1
DJ2
DJ3
Figure 17. Typical NB7VQ14M Equalizer Application and Interconnect with PRBS23 pattern at 6.5 Gbps, EQEN = 1
ORDERING INFORMATION
Device
Package
Shipping†
NB7VQ14MMNG
QFN−16
(Pb−Free)
123 Units / Tube
NB7VQ14MMNHTBG
QFN−16
(Pb−Free)
100 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
www.onsemi.com
9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G
ISSUE G
1
SCALE 2:1
DATE 08 OCT 2021
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
XXXXX
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON04795D
QFN16 3X3, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
onsemi Website: www.onsemi.com
◊
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
工商网监
湘ICP备2023018690号
