NBC12430AFAG

3.3 V/5 V Programmable PLL Synthesized Clock Generator 50 MHz to 800 MHz NBC12430, NBC12430A The NBC12430 and NBC12430A are general purpose, PLL based synthesized clock sources. The VCO will operate over a frequency range of 400 MHz to 800 MHz. The VCO frequency is sent to the N−output divider, where it can be configured to provide division ratios of 1, 2, 4, or 8. The VCO and output frequency can be programmed using the parallel or serial interfaces to the configuration logic. Output frequency steps of 250 kHz, 500 kHz, 1.0 MHz, 2.0 MHz can be achieved using a 16 MHz crystal, depending on the output dividers settings. The PLL loop filter is fully integrated and does not require any external components. Features • • • • • • • • • • Best−in−Class Output Jitter Performance, ±20 ps Peak−to−Peak 50 MHz to 800 MHz Programmable Differential PECL Outputs Fully Integrated Phase−Lock−Loop with Internal Loop Filter Parallel Interface for Programming Counter and Output Dividers During Powerup Minimal Frequency Overshoot Serial 3−Wire Programming Interface Crystal Oscillator Interface Operating Range: VCC = 3.135 V to 5.25 V CMOS and TTL Compatible Control Inputs Pin and Function Compatible with Motorola MC12430 and MPC9230 0°C to 70°C Ambient Operating Temperature (NBC12430) • • −40°C to 85°C Ambient Operating Temperature (NBC12430A) • Pb−Free Packages are Available www.onsemi.com MARKING DIAGRAMS 1 28 NBC12430xG AWLYYWW PLCC−28 FN SUFFIX CASE 776 NBC12 430 AWLYYWWG LQFP−32 FA SUFFIX CASE 561AB 1 1 32 QFN32 MN SUFFIX CASE 488AM x A WL, L YY, Y WW, W G or G NBC12 430A AWLYYWWG G = Blank or A = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet. © Semiconductor Components Industries, LLC, 2010 May, 2021 − Rev. 14 1 Publication Order Number: NBC12430/D NBC12430, NBC12430A +3.3 or 5.0 V  16 PHASE DETECTOR 4 10−20MHz XTAL1 9−BIT  M COUNTER 2 OSC 5 21, 25 24 23 N (1, 2, 4, 8) LATCH FOUT FOUT TEST LATCH 28 LATCH 7 0 S_CLOCK 400−800 MHz VCC 20 XTAL2 6 P_LOAD S_DATA +3.3 or 5.0 V VCO 2 FREF_EXT S_LOAD 1 PLL_VCC 3 XTAL_SEL OE 1 MHz FREF with 16 MHz Crystal 27 1 0 1 2−BIT SR 9−BIT SR 3−BIT SR 26 17, 18 8 → 16 9 M[8:0] 22, 19 2 N[1:0] Figure 1. Block Diagram (PLCC−28) Table 1. OUTPUT DIVISION Table 2. XTAL_SEL And OE N [1:0] Output Division Input 0 1 00 01 10 11 2 4 8 1 XTAL_SEL OE FREF_EXT Outputs Disabled XTAL Outputs Enabled www.onsemi.com 2 VCC FOUT FOUT GND VCC TEST GND NBC12430, NBC12430A 25 24 23 22 21 20 19 S_DATA 27 17 N[0] S_LOAD 28 16 M[8] PLL_VCC 1 15 M[7] FREF_EXT 2 14 M[6] XTAL_SEL 3 13 M[5] XTAL1 4 12 M[4] 7 8 9 10 11 M[3] 6 OE XTAL2 5 M[2] N[1] M[1] 18 M[0] 26 P_LOAD S_CLOCK S_DATA 2 23 N[1] S_LOAD 3 22 PLL_VCC 4 PLL_VCC 5 FREF_EXT 6 19 M[6] XTAL_SEL 7 12 13 14 15 16 P_LOAD M[0] M[1] M[2] M[3] N/C 30 29 28 27 26 25 24 N/C N[0] S_DATA 2 23 N[1] 21 M[8] S_LOAD 3 22 N[0] 20 M[7] PLL_VCC 4 21 M[8] PLL_VCC 5 20 M[7] FREF_EXT 6 19 M[6] 18 M[5] XTAL_SEL 7 18 M[5] 17 XTAL1 8 17 M[4] M[4] Exposed Pad (EP) Figure 3. 32−Lead QFN (Top View) 9 10 11 12 13 14 15 16 N/C 11 31 1 M[3] 10 32 S_CLOCK M[2] 9 OE 8 XTAL2 XTAL1 GND N/C TEST 24 VCC 1 VCC S_CLOCK GND 25 M[1] GND 26 M[0] TEST 27 FOUT VCC 28 P_LOAD VCC 29 FOUT GND 30 OE FOUT 31 VCC FOUT 32 XTAL2 VCC Figure 2. 28−Lead PLCC (Top View) Figure 4. 32−Lead LQFP (Top View) www.onsemi.com 3 NBC12430, NBC12430A The following gives a brief description of the functionality of the NBC12430 and NBC12430A Inputs and Outputs. Unless explicitly stated, all inputs are CMOS/TTL compatible with either pullup or pulldown resistors. The PECL outputs are capable of driving two series terminated 50 W transmission lines on the incident edge. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 3. PIN FUNCTION DESCRIPTION Pin Name Function Description INPUTS XTAL1, XTAL2 Crystal Inputs These pins form an oscillator when connected to an external series−resonant crystal. S_LOAD* CMOS/TTL Serial Latch Input (Internal Pulldown Resistor) This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this signal is HIGH; thus, the data must be stable on the HIGH−to−LOW transition of S_LOAD for proper operation. S_DATA* CMOS/TTL Serial Data Input (Internal Pulldown Resistor) This pin acts as the data input to the serial configuration shift registers. S_CLOCK* CMOS/TTL Serial Clock Input (Internal Pulldown Resistor) This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge. P_LOAD** CMOS/TTL Parallel Latch Input (Internal Pullup Resistor) This pin loads the configuration latches with the contents of the parallel inputs. The latches will be transparent when this signal is LOW; therefore, the parallel data must be stable on the LOW−to−HIGH transition of P_LOAD for proper operation. M[8:0]** CMOS/TTL PLL Loop Divider Inputs (Internal Pullup Resistor) These pins are used to configure the PLL loop divider. They are sampled on the LOW−to−HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB. N[1:0]** CMOS/TTL Output Divider Inputs (Internal Pullup Resistor) These pins are used to configure the output divider modulus. They are sampled on the LOW−to−HIGH transition of P_LOAD. OE** CMOS/TTL Output Enable Input (Internal Pullup Resistor) Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the FOUT output. FREF_EXT* CMOS/TTL Input (Internal Pulldown Resistor) This pin can be used as the PLL Reference XTAL_SEL** CMOS/TTL Input (Internal Pullup Resistor) This pin selects between the crystal and the FREF_EXT source for the PLL reference signal. A HIGH selects the crystal input. FOUT, FOUT PECL Differential Outputs These differential, positive−referenced ECL signals (PECL) are the outputs of the synthesizer. TEST PECL Output The function of this output is determined by the serial configuration bits T[2:0]. VCC Positive Supply for the Logic The positive supply for the internal logic and output buffer of the chip, and is connected to +3.3 V or +5.0 V. PLL_VCC Positive Supply for the PLL This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V. GND Negative Power Supply These pins are the negative supply for the chip and are normally all connected to ground. − Exposed Pad for QFN−32 only The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to GND. OUTPUTS POWER * When left Open, these inputs will default LOW. ** When left Open, these inputs will default HIGH. www.onsemi.com 4 NBC12430, NBC12430A Table 4. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 37.5 kW ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 150 V > 1 kV Moisture Sensitivity (Note 1) PLCC LQFP QFN Pb−Free Pkg Level 3 Level 2 Level 1 Flammability Rating Oxygen Index: 28 to 34’ UL 94 V−0 @ 0.125 in Transistor Count 2011 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 5. MAXIMUM RATINGS Symbol VCC Parameter Condition 1 Positive Supply GND = 0 V VI Input Voltage GND = 0 V Iout Output Current Continuous Surge TA Operating Temperature Range Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm qJC Thermal Resistance (Junction−to−Case) qJA Condition 2 VI ≤ VCC NBC12430 NBC12430A Rating Units 6 V 6 V 50 100 mA mA 0 to 70 −40 to +85 °C −65 to +150 °C PLCC−28 PLCC−28 63.5 43.5 °C/W °C/W Standard Board PLCC−28 22 to 26 °C/W Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm LQFP−32 LQFP−32 80 55 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board LQFP−32 12 to 17 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm QFN−32 QFN−32 31 27 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P QFN−32 12 °C/W Tsol Wave Solder 265 °C Pb−Free 2, fractional values of FOUT can be realized. The size of the programmable frequency steps (and thus, the indicator of the fractional output frequencies achievable) will be equal to FXTAL ÷ 16 ÷ N. For input reference frequencies other than 16 MHz, see Table 11, which shows the usable VCO frequency and M divider range. www.onsemi.com 9 NBC12430, NBC12430A ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 11. FREQUENCY OPERATING RANGE Output Frequency (MHz) for FXTAL = 16 MHz and for N = VCO Frequency (MHz) Range for a Crystal Frequency (MHz) of: M M[8:0] 10 12 14 16 18 20 160 010100000 400 170 010101010 425 180 010110100 405 450 190 010111110 427.5 475 200 011001000 400 450 210 011010010 420 220 011011100 230 011100110 240 250 B1 B2 B4 B8 500 400 200 100 50 472.5 525 420 210 105 52.5 440 495 550 440 220 110 55 402.5 460 517.5 575 460 230 115 57.5 011110000 420 480 540 600 480 240 120 60 011111010 437.5 500 562.5 625 500 250 125 62.5 260 100000100 455 520 585 650 520 260 130 65 270 100001110 405 472.5 540 607.5 675 540 270 135 67.5 280 100011000 420 490 560 630 700 560 280 140 70 290 100100010 435 507.5 580 652.5 725 580 290 145 72.5 300 100101100 450 525 600 675 750 600 300 150 75 310 100110110 465 542.5 620 697.5 775 620 310 155 77.5 320 101000000 400 480 560 640 720 800 640 320 160 80 330 101001010 412.5 495 577.5 660 742.5 660 330 165 82.5 340 101010100 425 510 595 680 765 680 340 170 85 350 101011110 437.5 525 612.5 700 787.5 700 350 175 87.5 360 101101000 450 540 630 720 720 360 180 90 370 101110010 462.5 555 647.5 740 740 370 185 92.5 380 101111100 475 570 665 760 760 380 190 95 390 110000110 487.5 585 682.5 780 780 390 195 97.5 400 110010000 500 600 700 800 800 400 200 100 410 110011010 512.5 615 717.5 420 110100100 525 630 735 430 110101110 537.5 645 752.5 440 110111000 550 660 770 450 111000010 562.5 675 787.5 460 111001100 575 690 470 111010110 587.5 705 480 111100000 600 720 490 111101010 612.5 735 500 111110100 625 750 510 111111110 637.5 765 www.onsemi.com 10 NBC12430, NBC12430A Most of the signals available on the TEST output pin are useful only for performance verification of the device itself. However, the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110, the device is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives the user more control on the test clocks sent through the clock tree. Figure 7 shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 250 MHz or less. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 250 MHz as the minimum divide ratio of the N counter is 1. Note that the M counter output on the TEST output will not be a 50% duty cycle due to the way the divider is implemented. ÇÇÇÇ ÇÇÇÇ Table 12. T2 T1 T0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TEST (Pin 20) ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ M[8:0] N[1:0] SHIFT REGISTER OUT HIGH FREF M COUNTER OUT FOUT LOW PLL BYPASS FOUT  4 VALID ts P_LOAD ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ th M, N to P_LOAD Figure 5. Parallel Interface Timing Diagram S_CLOCK S_DATA ts C1 th T2 ÇÇÇÇ ÇÇÇÇ C2 T1 C3 C4 C5 C6 C7 C8 M7 M6 C10 C11 C12 C13 C14 T0 N1 N0 M8 M5 M4 M3 M2 M1 M0 Last Bit First Bit S_LOAD th ts S_CLOCK to S_LOAD Figure 6. Serial Interface Timing Diagram FREF_EXT MCNT PLL 12430 VCO_CLK 0 1 SCLOCK M COUNTER DECODE SDATA C9 S_DATA to S_CLOCK SHIFT REG T0 14−BIT T1 T2 FOUT (VIA ENABLE GATE) N (1, 2, 4, 8) FDIV4 MCNT LOW FOUT MCNT FREF HIGH 7 TEST MUX 0 LATCH Reset SLOAD • T2=T1=1, T0=0: Test Mode PLOAD • SCLOCK is selected, MCNT is on TEST output, SCLOCK  N is on FOUT pin. PLOAD acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin. Figure 7. Serial Test Clock Block Diagram www.onsemi.com 11 TEST NBC12430, NBC12430A APPLICATIONS INFORMATION Using the On−Board Crystal Oscillator Table 13. CRYSTAL SPECIFICATIONS The NBC12430 and NBC12430A feature a fully integrated on−board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. The series resonant design provides better stability and eliminates the need for large load capacitors per Figure 8 (do not use crystal load caps). The oscillator is totally self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs, the user is advised to mount the crystal as close to the device as possible to avoid any board level parasitics. To facilitate co−location, surface mount crystals are recommended, but not required. Because the series resonant design is affected by capacitive loading on the crystal terminals, loading variation introduced by crystals from different vendors could be a potential issue. For crystals with a higher shunt capacitance, it may be required to place a resistance, optional Rshunt, across the terminals to suppress the third harmonic. Although typically not required, it is a good idea to layout the PCB with the provision of adding this external resistor. The resistor value will typically be between 500 W and 1 kW. Parameter Value Crystal Cut Fundamental AT Cut Resonance Series Resonance* Frequency Tolerance ±75 ppm at 25°C Frequency/Temperature Stability ±150 ppm 0 to 70°C Operating Range 0 to 70°C Shunt Capacitance 5−7 pF Equivalent Series Resistance (ESR) 50 to 80 W Correlation Drive Level 100 mW Aging 5 ppm/Yr (First 3 Years) * See accompanying text for series versus parallel resonant discussion. Power Supply Filtering The NBC12430 and NBC12430A are mixed analog/digital product and as such, it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The NBC12430 and NBC12430A provide separate power supplies for the digital circuitry (VCC) and the internal PLL (PLL_VCC) of the device. The purpose of this design technique is to try and isolate the high switching noise of the digital outputs from the relatively sensitive internal analog phase−locked loop. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simplest form of isolation is a power supply filter on the PLL_VCC pin for the NBC12430 and NBC12430A . Figure 9 illustrates a typical power supply filter scheme. The NBC12430 and NBC12430A are most susceptible to noise with spectral content in the 1 KHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the PLL_VCC pin of the NBC12430 and NBC12430A . From the data sheet, the PLL_VCC current (the current sourced through the PLL_VCC pin) is typically 24 mA (30 mA maximum). Assuming that a minimum of 2.8 V must be maintained on the PLL_VCC pin, very little DC voltage drop can be tolerated when a 3.3 V VCC supply is used. The resistor shown in Figure 9 must have a resistance of 10−15 W to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the Figure 8. Crystal Application The oscillator circuit is a series resonant circuit and thus, for optimum performance, a series resonant crystal should be used. Unfortunately, most crystals are characterized in a parallel resonant mode. Fortunately, there is no physical difference between a series resonant and a parallel resonant crystal. The difference is purely in the way the devices are characterized. As a result, a parallel resonant crystal can be used with the device with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified (a few hundred ppm translates to kHz inaccuracies). In a general computer application, this level of inaccuracy is immaterial. Table 13 below specifies the performance requirements of the crystals to be used with the device. www.onsemi.com 12 NBC12430, NBC12430A ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ series resonant point of an individual capacitor, it’s overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. 3.3 V or 5.0 V 3.3 V or 5.0 V RS = 10−15 W C1 ÉÉÉ ÉÉÉ R1 L=1000 mH R=15 W C3 1 C2 R1 = 10−15 W C1 = 0.01 mF C2 = 22 mF C3 = 0.1 mF PLL_VCC 22 mF 0.01 mF NBC12430 NBC12430A ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ C1 XTAL VCC Rshunt 0.01 mF ÉÉÉ ÉÉÉ = VCC = GND = Via Figure 9. Power Supply Filter Opt. Rshunt = 500 W − 1 kW Figure 10. PCB Board Layout (PLCC−28) A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. Figure 9 shows a 1000 mH choke. This value choke will show a significant impedance at 10 KHz frequencies and above. Because of the current draw and the voltage that must be maintained on the PLL_VCC pin, a low DC resistance inductor is required (less than 15 W). Generally, the resistor/capacitor filter will be cheaper, easier to implement, and provide an adequate level of supply filtering. The NBC12430 and NBC12430A provide sub−nanosecond output edge rates and therefore a good power supply bypassing scheme is a must. Figure 10 shows a representative board layout for the NBC12430 and NBC12430A . There exists many different potential board layouts and the one pictured is but one. The important aspect of the layout in Figure 10 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the device outputs. It is imperative that low inductance chip capacitors are used. It is equally important that the board layout not introduce any of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. Note the dotted lines circling the crystal oscillator connection to the device. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on−board oscillator. Note the provisions for placing a resistor across the crystal oscillator terminals as discussed in the crystal oscillator section of this data sheet. Although the NBC12430 and NBC12430A have several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise−related problems in most designs. Jitter Performance Jitter is a common parameter associated with clock generation and distribution. Clock jitter can be defined as the deviation in a clock’s output transition from its ideal position. Cycle−to−Cycle Jitter (short−term) is the period variation between two adjacent cycles over a defined number of observed cycles. The number of cycles observed is application dependent but the JEDEC specification is 1000 cycles. www.onsemi.com 13 NBC12430, NBC12430A T0 analysis capabilities on non−contiguous clocks with their histogram and statistics capabilities. The Tektronix TDSJIT2/3 Jitter Analysis software provides many key timing parameter measurements and will extend that capability by making jitter measurements on contiguous clock and data cycles from single−shot acquisitions. M1 by Amherst was used as well and both test methods correlated. This test process can be correlated to earlier test methods and is more accurate. All of the jitter data reported on the NBC12430 and NBC12430A was collected in this manner. Figure 14 shows the jitter as a function of the output frequency. The graph shows that for output frequencies from 50 to 800 MHz the jitter falls within the 20 ps peak−to−peak specification. The general trend is that as the output frequency is increased, the output edge jitter will decrease. Figure 13 illustrates the RMS jitter performance of the NBC12430 and NBC12430A across its specified VCO frequency range. Note that the jitter is a function of both the output frequency as well as the VCO frequency. However, the VCO frequency shows a much stronger dependence. The data presented has not been compensated for trigger jitter. Long−Term Period Jitter is the maximum jitter observed at the end of a period’s edge when compared to the position of the perfect reference clock’s edge and is specified by the number of cycles over which the jitter is measured. The number of cycles used to look for the maximum jitter varies by application but the JEDEC spec is 10,000 observed cycles. The NBC12430 and NBC12430A exhibit long term and cycle−to−cycle jitter, which rivals that of SAW based oscillators. This jitter performance comes with the added flexibility associated with a synthesizer over a fixed frequency oscillator. The jitter data presented should provide users with enough information to determine the effect on their overall timing budget. The jitter performance meets the needs of most system designs while adding the flexibility of frequency margining and field upgrades. These features are not available with a fixed frequency SAW oscillator. T1 TJITTER(cycle−cycle) = T1 − T0 Figure 11. Cycle−to−Cycle Jitter RMS or one Sigma Jitter Typical Gaussian Distribution Time Peak−to−Peak Jitter (8 s) Jitter Amplitude Peak−to−Peak Jitter is the difference between the highest and lowest acquired value and is represented as the width of the Gaussian base. Figure 12. Peak−to−Peak Jitter 25 25 20 20 RMS JITTER (ps) RMS JITTER (ps) There are different ways to measure jitter and often they are confused with one another. The typical method of measuring jitter is to look at the timing signal with an oscilloscope and observe the variations in period−to−period or cycle−to−cycle. If the scope is set up to trigger on every rising or falling edge, set to infinite persistence mode and allowed to trace sufficient cycles, it is possible to determine the maximum and minimum periods of the timing signal. Digital scopes can accumulate a large number of cycles, create a histogram of the edge placements and record peak−to−peak as well as standard deviations of the jitter. Care must be taken that the measured edge is the edge immediately following the trigger edge. These scopes can also store a finite number of period durations and post−processing software can analyze the data to find the maximum and minimum periods. Recent hardware and software developments have resulted in advanced jitter measurement techniques. The Tektronix TDS−series oscilloscopes have superb jitter 15 10 N=8 N=4 15 10 5 5 N=1 0 N=2 400 500 600 700 0 800 VCO FREQUENCY (MHz) 100 200 300 400 500 600 OUTPUT FREQUENCY (MHz) Figure 13. RMS Jitter vs. VCO Frequency 700 Figure 14. RMS Jitter vs. Output Frequency www.onsemi.com 14 800 NBC12430, NBC12430A S_DATA S_CLOCK tHOLD tSETUP Figure 15. Setup and Hold S_DATA S_LOAD tHOLD tSETUP Figure 16. Setup and Hold M[8:0] N[1:0] P_LOAD tHOLD tSETUP Figure 17. Setup and Hold FOUT FOUT Pulse Width tPERIOD Figure 18. Output Duty Cycle www.onsemi.com 15 DCO  tpw tPERIOD NBC12430, NBC12430A FOUT D Receiver Device Driver Device FOUT D 50 W 50 W V TT V TT = V CC − 2.0 V Figure 19. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 − Termination of ECL Logic Devices.) ORDERING INFORMATION Device Package Shipping† NBC12430FAR2G LQFP−32 (Pb−Free) 2000 / Tape & Reel NBC12430FNG PLCC−28 (Pb−Free) 37 Units / Tube NBC12430FNR2G PLCC−28 (Pb−Free) 500 / Tape & Reel NBC12430AFNG PLCC−28 (Pb−Free) 37 Units / Tube NBC12430AMNG QFN−32 (Pb−Free) 74 Units / Tube †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 16 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN32 5x5, 0.5P CASE 488AM ISSUE A 1 32 SCALE 2:1 A D PIN ONE LOCATION ÉÉ ÉÉ NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L B DATE 23 OCT 2013 L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E DIM A A1 A3 b D D2 E E2 e K L L1 0.15 C 0.15 C EXPOSED Cu A DETAIL B 0.10 C (A3) A1 0.08 C DETAIL A 9 32X L ALTERNATE CONSTRUCTION GENERIC MARKING DIAGRAM* K D2 1 XXXXXXXX XXXXXXXX AWLYYWWG G 17 8 MOLD CMPD DETAIL B SEATING PLANE C SIDE VIEW NOTE 4 ÉÉ ÉÉ ÇÇ TOP VIEW MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.18 0.30 5.00 BSC 2.95 3.25 5.00 BSC 2.95 3.25 0.50 BSC 0.20 −−− 0.30 0.50 −−− 0.15 E2 1 32 25 e e/2 32X b 0.10 M C A B 0.05 M C BOTTOM VIEW XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 5.30 32X 0.63 3.35 3.35 5.30 0.50 PITCH 32X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON20032D QFN32 5x5 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS LQFP−32, 7x7 CASE 561AB−01 ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON30893E 32 LEAD LQFP, 7X7 DATE 19 JUN 2008 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS 28 LEAD PLCC CASE 776−02 ISSUE G DATE 06 APR 2021 281 SCALE 1:1 B Y BRK −N− 0.007 (0.180) U M T L-M 0.007 (0.180) M N S T L-M S S N S D Z −M− −L− W 28 D X V 1 G1 0.010 (0.250) T L-M S N S S VIEW D−D Z A 0.007 (0.180) R 0.007 (0.180) M M T L-M T L-M S S N N H S 0.007 (0.180) M T L-M N S S S K1 C E 0.004 (0.100) G S SEATING PLANE K F 0.007 (0.180) M T L-M S N S VIEW S G1 0.010 (0.250) −T− J T L-M S N NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DOCUMENT NUMBER: DESCRIPTION: VIEW S S GENERIC MARKING DIAGRAM* 1 28 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.021 0.050 BSC 0.026 0.032 0.020 --0.025 --0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2_ 10_ 0.410 0.430 0.040 --- 98ASB42596B 28 LEAD PLCC MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.53 1.27 BSC 0.66 0.81 0.51 --0.64 --11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2_ 10_ 10.42 10.92 1.02 --- XXXXXXXXXXXX XXXXXXXXXXXG AWLYYWW XXXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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