NBVSPA013LN1TAG

NBVSPA013 2.5 V, 212.00 MHz LVDS Voltage-Controlled Clock Oscillator (VCXO) PureEdget Product Series The NBVSPA013 voltage−controlled crystal oscillator (VCXO) is designed to meet today’s requirements for 2.5 V LVDS clock generation applications. These devices use a high Q fundamental mode crystal and Phase Locked Loop (PLL) multiplier to provide 212.00 MHz with a pullable range of ±100 ppm and a frequency stability of ±50 ppm. The silicon−based PureEdget products design provides users with exceptional frequency stability and reliability. They produce an ultra low jitter and phase noise LVDS differential output. The NBVSPA013 is a member of ON Semiconductor’s PureEdge clock family that provides accurate and precision clock generation solutions. Available in the industry standard 5.0 x 7.0 x 1.8 mm SMD (CLCC) package on 16 mm tape and reel in quantities of 1,000 and 100. http://onsemi.com MARKING DIAGRAMS 6 PIN CLCC LN SUFFIX CASE 848AB A WL YY WW G NBVSPA013 212.0000 AWLYYWWG = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Features • • • • • • • • • • LVDS Differential Output Uses High Q Fundamental Mode Crystal Ultra Low Jitter and Phase Noise − 0.5 ps (12 kHz − 20 MHz) Pullable Range Minimum of ±100 ppm Frequency Stability of ±50 ppm Control Voltage with Positive Slope Voltage Control Linearity of ±10% Hermetically Sealed Ceramic SMD Packages of size 5.0 x 7.0 x 1.8 mm Operating Range: 2.5 V ±5% These Devices are Pb−Free and are RoHS Compliant ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Applications • Networking • Networking Base Stations • Broadcasting © Semiconductor Components Industries, LLC, 2012 April, 2012 − Rev. 0 1 Publication Order Number: NBVSPA013/D NBVSPA013 VDD 6 CLK CLK 5 4 PLL Clock Multiplier Crystal LVDS 1 VC 2 OE 3 GND Figure 1. Simplified Logic Diagram VC 1 6 VDD OE 2 5 CLK GND 3 4 CLK Figure 2. Pin Connections (Top View) Table 1. PIN DESCRIPTION Pin No. Symbol I/O Description 1 VC (Note 1) Analog Input Analog control voltage input pin that adjusts output oscillation frequency. f0 =VC = 1.25 V 2 OE LVTTL/LVCMOS Control Input 3 GND Power Supply Ground at 0 V. Electrical and Case Ground. 4 CLK LVDS Output Non−Inverted Clock Output. Typically loaded with 100 W receiver termination resistor across differential pair. 5 CLK LVDS Output Inverted Clock Output. Typically loaded with 100 W receiver termination resistor across differential pair. 6 VDD Power Supply Positive Power Supply Voltage. Voltage should not exceed 2.5 V ±5%. Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. See OE pin description Table 2. 1. Control voltage has a positive slope with a typical linearity of ±10%; VC = 1.25 V ± 1 V. Table 2. OUTPUT ENABLE TRI−STATE FUNCTION OE Pin Output Pins Open Active HIGH Level Active LOW Level High Z Table 3. ATTRIBUTES Characteristic Value Input Default State Resistor ESD Protection 170 kW Human Body Model Machine Model Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test http://onsemi.com 2 2 kV 200 V NBVSPA013 Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 VDD Positive Power Supply VIN Control Input (VC and OE) IOSC Output Short Circuit Current CLK to CLK CLK or CLK to GND Condition 2 GND = 0 V Rating Units 4.6 V VIN ≤ VDD + 200 mV VIN ≥ GND − 200 mV Continuous Continuous V 12 24 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −55 to +120 °C Tsol Wave Solder 260 °C See Figure 5 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 5. DC CHARACTERISTICS (VDD = 2.5 V ±5%, GND = 0 V, TA = −40°C to +85°C) (Note 2) Symbol Characteristic Conditions Min. Typ. Max. Units 75 100 mA VDD mV IDD Power Supply Current VIH OE and FSEL Input HIGH Voltage 2000 VIL OE and FSEL Input LOW Voltage GND − 300 800 mV IIH Input HIGH Current OE −100 +100 mA IIL Input LOW Current OE −100 +100 mA 25 mV 1375 mV 1 25 mV 1425 1600 mV DVOD VOS DVOS Change in Magnitude of VOD for Complementary Output States (Note 3) Offset Voltage Change in Magnitude of VOS for Complementary Output States 0 1 1125 (Note 3) 0 VOH Output HIGH Voltage VOL Output LOW Voltage 900 VOD Differential Output Voltage 250 1075 mV 450 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 4. 3. Parameter guaranteed by design verification not tested in production. http://onsemi.com 3 NBVSPA013 Table 6. AC CHARACTERISTICS (VDD = 2.5 ±5%, GND = 0 V, TA = −40°C to +85°C) (Note 4) Symbol Characteristic Conditions fCLKOUT Output Clock Frequency NBVSPA013 Df Frequency Stability (Note 5) tjit(f) RMS Phase Jitter 12 kHz to 20 MHz tjitter Min. Typ. Max. 212.00 0.4 Unit MHz ±50 ppm 0.9 ps Cycle to Cycle, RMS 1000 Cycles 3 8 ps Cycle to Cycle, Peak−to−Peak 1000 Cycles 15 30 ps Period, RMS 10,000 Cycles 2 4 ps Period, Peak−to−Peak 10,000 Cycles 10 20 ps 200 ns tOE/OD Output Enable/Disable Time FP Crystal Pullability (Note 6) 0 V ≤ VC ≤ VDD ±100 −3 dB 20 VC(bw) Control Voltage Bandwidth tDUTY_CYCLE Output Clock Duty Cycle (Measured at Cross Point) tR 45 ppm KHz 50 55 % Output Rise Time (20% and 80%) 245 400 ps tF Output Fall Time (80% and 20%) 245 400 ps tstart Start−up Time 1 5 ms 3 ppm 1st Aging Year Every Year After 1st 1 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 4. 5. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration and first year aging. 6. Gain transfer is positive with a rate of 130 ppm/V. Table 7. PHASE NOISE PERFORMANCE FOR NBVSPA013 Parameter Characteristic Condition 212.00 MHZ Unit fNOISE Output Phase−Noise Performance 100 Hz of Carrier −82 dBc/Hz 1 kHz of Carrier −110 dBc/Hz 10 kHz of Carrier −122 dBc/Hz 100 kHz of Carrier −123 dBc/Hz 1 MHz of Carrier −132 dBc/Hz 10 MHz of Carrier −160 dBc/Hz http://onsemi.com 4 NBVSPA013 Figure 3. Typical Phase Noise Plot at 212.00 MHz http://onsemi.com 5 NBVSPA013 Table 8. RELIABILITY COMPLIANCE ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Parameter Standard Method Shock Mechanical MIL−STD−833, Method 2002, Condition B Solderability Mechanical MIL−STD−833, Method 2003 Vibration Mechanical MIL−STD−833, Method 2007, Condition A Solvent Resistance Mechanical MIL−STD−202, Method 215 Thermal Shock Environment MIL−STD−833, Method 1011, Condition A Moisture Level Sensitivity Environment MSL1 260°C per IPC/JEDEC J−STD−020D NBVSPA013 Zo = 50 W CLK D Driver Device Receiver Device 100 W CLK D Zo = 50 W Figure 4. Typical Termination for Output Driver and Device Evaluation temp. 260°C 20 − 40 sec. max. peak Temperature (°C) 260 6°C/sec. max. 3°C/sec. max. 217 ramp−up 175 150 cooling pre−heat reflow 60180 sec. Time 60150 sec. Figure 5. Recommended Reflow Soldering Profile Table 9. ORDERING INFORMATION Device Output Frequency (MHz) Package Shipping† 5.0 x 7.0 x 1.8 mm NBVSPA013LN1TAG 212.0000 CLCC−6, Pb−Free 1000 / Tape & Reel NBVSPA013LNHTAG 212.0000 CLCC−6, Pb−Free 100 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and Reel Packaging Specification Brochure, BRD8011/D http://onsemi.com 6 NBVSPA013 PACKAGE DIMENSIONS 6 PIN CLCC, 7x5, 2.54P CASE 848AB ISSUE C A D 4X D1 0.15 C E2 TERMINAL 1 INDICATOR NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. B H E1 DIM A A1 A2 A3 b D D1 D2 D3 E E1 E2 E3 e H L R E D2 TOP VIEW A3 A2 0.10 C A SIDE VIEW A1 C 6.17 6.66 4.37 4.65 1.17 SOLDERING FOOTPRINT* 2 3 e 6X R 1.50 E3 0.10 C A B 0.05 C 0.08 1.30 MILLIMETERS NOM MAX 1.80 1.90 0.70 REF 0.36 REF 0.10 0.12 1.40 1.50 7.00 BSC 6.20 6.23 6.81 6.96 5.08 BSC 5.00 BSC 4.40 4.43 4.80 4.95 3.49 BSC 2.54 BSC 1.80 REF 1.27 1.37 0.70 REF SEATING PLANE D3 1 MIN 1.70 6X b 6 5 4 6X 5.06 L BOTTOM VIEW 2.54 PITCH 6X 1.50 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PureEdge is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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