NCP1230
PWM Controller, Fixed
Frequency, Current Mode
The NCP1230 represents a major leap towards achievingstandby
low
power in medium−to−high power Switched−Mode Power Supplies
such as notebook adapters, off
−line battery chargers andconsumer
electronics equipment. Housed in a compact 8−pin package (SOIC−8,
SOIC−7, or PDIP−7), the NCP1230 contains all needed
control
functionality to build a rugged and efficient power supply. The
NCP1230 is a current mode controller with internal ramp
compensation. Among the unique features offered by the NCP1230 is
an event management scheme that can disable the front−end PFC
circuit during standby, thus reducing the no load power consumption.
The NCP1230 itself goes into cycle skipping at light loads while
limiting peak current (to 25% of nominal peak) so that no acoustic
noise is generated. The NCP1230 has a high
−voltage startup circuit
that eliminates external components and reduces power consumption.
The NCP1230 also features an internal latching function that can be
used for OVP protection. This latch is triggered by pulling the CS pin
above 3.0 V and can only be reset by pulling VCC to ground. True
overload protection, internal 2.5 ms soft−start, internal leading edge
blanking, internal frequency dithering for low EMI are some of the
other important features offered by the NCP1230.
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MARKING
DIAGRAM
8
SOIC−8 VHVIC
D SUFFIX
CASE 751
8
1
•
•
•
•
•
•
•
•
•
•
Current−Mode Operation with Internal Ramp Compensation
Internal High−Voltage Startup Current Source for Loss−Less Startup
Extremely Low No−Load Standby Power
Skip−Cycle Capability at Low Peak Currents
Direct Connection to PFC Controller for Improved No−Load Standby
Power
Internal 2.5 ms Soft−Start
Internal Leading Edge Blanking
Latched Primary Overcurrent and Overvoltage Protection
Short−Circuit Protection Independent of Auxiliary Level
Internal Frequency Jittering for Improved EMI Signature
+500 mA/−800 mA Peak Current Drive Capability
Available in Three Frequency Options: 65 kHz, 100 kHz, and 133 kHz
Direct Optocoupler Connection
SPICE Models Available for TRANsient and AC Analysis
This is a Pb−Free Device
Typical Applications
• High Power AC−DC Adapters for Notebooks, etc.
• Offline Battery Chargers
• Set−Top Boxes Power Supplies, TV, Monitors, etc.
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 12
8
SOIC−7
D1 SUFFIX
CASE 751U
8
1
1
Features
•
•
•
•
•
1
1
30D16
ALYWG
G
1230Pxxx
AWL
YYWWG
PDIP−7 VHVIC
P SUFFIX
CASE 626B
8
230Dy
ALYWy
G
1
xxx
= Device Code: 65, 100, 133
y
= Device Code: 6, 1, 1
y
= Device Code: 5, 0, 3
A
= Assembly Location
L
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
PFC Vcc
FB
CS
GND
1
8
HV
VCC
DRV
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 4 of this data sheet.
1
Publication Order Number:
NCP1230/D
NCP1230
HV
+
+
CBulk
1
8
2
7
3
4
PFC_VCC
1
8
2
7
6
3
6
5
4
5
OVP
Vout
OVP
GND
NCP1230
MC33262/33260
Ramp Comp
Rsense
10 k
VCC Cap
GND
Figure 1. Typical Application Example
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Pin Description
1
PFC VCC
This pin provides
the bias voltage to
the PFC controller.
This pin is a direct connection to the VCC pin (Pin 6) via a low impedance switch. In
standby and during the startup sequence, the switch is open and the PFC VCC is
shut down. As soon as the aux. winding is stabilized, Pin 1 connects to the VCC pin
and provides bias to the PFC controller. It goes down in standby and fault conditions.
2
FB
Feedback Signal
An optocoupler collector pulls this pin low to regulate. When the current setpoint
reaches 25% of the maximum peak, the controller skips cycles.
3
CS/OVP
Current Sense
This pin incorporates three different functions: the current sense function, an internal
ramp compensation signal and a 3.0 V latch−off level which latches the output off
until VCC is recycled.
4
GND
IC Ground
5
DRV
Driver Output
With a drive capability of +500 mA / −800 mA, the NCP1230 can drive large Qg
MOSFETs.
6
VCC
VCC Input
The controller accepts voltages up to 18 V and features a UVLO turn−off threshold of
7.7 V typical.
7
NC
−
8
HV
High−Voltage
−
−
This pin connects to the bulk voltage and offers a lossless startup sequence. The
charging current is high enough to support the bias needs of a PWM controller
through Pin 1.
www.onsemi.com
2
3
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Figure 2. Internal Circuit Architecture
4
GND
3.0 Vdc
Fault
−
S
R
Q
2.3 Vpp
Ramp
OSC
Vccreset
Frequency
Modulation
Thermal
Shutdown
2.5 msec
SS Timer
Latch−Off
PWM
−
+
10 V
LEB
Vdd
1.25 Vdc
PFC_Vcc
Soft−Start Ramp (1V max)
−
+
3
18k
25k
55k
Error
−
−
Skip
+
CS
10 V
FB
20k
Vdd_fb
0.75 Vdc
+
125 msec
Timer
PFC_Vcc
SW1
+
/2
4Vcomp
S
R
Q
4.0 Vdc
−
+
2
1
PFC_Vcc
Internal
Bias
Vcc Mgmt
Vccoff=12.6V
Vccmin=7.7V
Vcclatch=5.6V
20V
DRV
VCC
3.2 mAdc
HV
5
6
8
NCP1230
NCP1230
MAXIMUM RATINGS (Notes 1 and 2)
Symbol
Value
Unit
Maximum Voltage on Pin 8
Maximum Current
VDS
IC2
−0.3 to 500
100
V
mA
Power Supply Voltage, Pin 6
Current
VCC
ICC2
−0.3 to 18
100
V
mA
Drive Output Voltage, Pin 5
Drive Current
VDV
Io
18
1.0
V
A
Voltage Current Sense Pin, Pin 3
Current
Vcs
Ics
10
100
V
mA
Voltage Feedback, Pin 2
Current
Vfb
Ifb
10
100
V
mA
Voltage, Pin 1
Maximum Continuous Current Flowing from Pin 1
VPFC
IPFC
18
35
V
mA
Thermal Resistance, Junction−to−Air, PDIP Version
RJA
100
°C/W
RJA
178
°C/W
Pmax
1.25
0.702
W
Rating
Thermal Resistance, Junction−to−Air, SOIC Version
Maximum Power Dissipation @ TA = 25°C
PDIP
SOIC
Maximum Junction Temperature
TJ
150
°C
Storage Temperature Range
Tstg
−60 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Pin 1−6: Human Body Model 2000 V per JEDEC Standard JES22, Method A114E.
Machine Model Method 200 V per JEDEC Standard JESD22, Method A115A.
Pin 8 is the HV startup of the device and is rated to the maximum rating of the part, or 500 V.
2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
ORDERING INFORMATION
Package
Shipping†
NCP1230D165R2G
SOIC−7
(Pb−Free)
2500 / Tape & Reel
NCP1230D65R2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP1230D100R2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP1230D133R2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP1230P65G
PDIP−7
(Pb−Free)
50 Units/ Rail
NCP1230P100G
PDIP−7
(Pb−Free)
50 Units/ Rail
NCP1230P133G
PDIP−7
(Pb−Free)
50 Units/ Rail
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
4
NCP1230
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C,
VCC = 13 V, VPIN8 = 30 V unless otherwise noted.)
Characteristic
Symbol
Pin
Min
Typ
Max
Unit
Turn−On Threshold Level, VCC Going Up (Vfb = 2.0 V)
VCCOFF
6
11.6
12.6
13.6
V
Minimum Operating Voltage after Turn−On
VCC(min)
6
7.0
7.7
8.4
V
VCC Decreasing Level at which the Latch−Off Phase Ends (Vfb = 3.5 V)
VCClatch
6
5.0
5.6
6.2
V
VCC Level at which the Internal Logic gets Reset
VCCreset
6
−
4.0
−
V
Internal IC Consumption, No Output Load on Pin 6 (Vfb = 2.5 V)
ICC1
6
0.6
1.1
1.8
mA
Internal IC Consumption, 1.0 nF Output Load on Pin 6, FSW = 65 kHz
(Vfb = 2.5 V)
ICC2
6
1.3
1.8
2.5
mA
Internal IC Consumption, 1.0 nF Output Load on Pin 6, FSW = 100 kHz
ICC2
6
1.3
2.2
3.0
mA
Internal IC Consumption, 1.0 nF Output Load on Pin 6, FSW = 133 kHz
ICC2
6
1.3
2.8
3.3
mA
Internal IC Consumption, Latch−Off Phase
ICC3
6
400
680
1000
A
High−Voltage Current Source, 1.0 nF Load
(VCCOFF −0.2 V, Vfb = 2.5 V, VPIN8 = 30 V)
IC1
8
1.8
3.2
4.2
mA
High−Voltage Current Source (VCC = 0 V)
IC2
8
1.8
4.4
5.6
mA
Minimum Startup Voltage (Ic = 0.5 mA, VCCOFF −0.2 V, Vfb = 2.5 V)
VHVmin
8
−
20
23
V
Startup Leakage (VPIN8 = 500 V)
IHVLeak
8
10
30
80
A
Output Voltage Rise−Time @ CL = 1.0 nF, 10−90% of Output Signal
Tr
5
−
40
−
ns
Output Voltage Fall−Time @ CL = 1.0 nF, 10−90% of Output Signal
Tf
5
−
15
−
ns
Source Resistance, RLoad 300 (Vfb = 2.5 V)
ROH
5
6.0
12.3
25
Sink Resistance, at 1.0 V on Pin 5 (Vfb = 3.5 V)
ROL
5
3.0
7.5
18
RPFC
1
6.0
11.7
23
IIB
3
−
0.02
−
A
ILimit
3
1.010
0.979
1.063
−
1.116
1.127
V
Vskip
3
600
750
900
mV
Default Internal Setpoint to Leave Standby
Vstby−out
−
1.0
1.25
1.5
V
Propagation Delay from CS Detected to Gate Turned Off (VGate = 10 V)
(Pin 5 Loaded by 1.0 nF)
TDEL CS
3
−
90
180
ns
TLEB
3
100
200
350
ns
Soft−Start Period (Note 3)
SS
−
−
2.5
−
ms
Temperature Shutdown, Maximum Value (Note 3)
TSD
−
150
165
−
°C
TSD hyste
−
−
25
−
°C
Supply Section (All frequency versions, otherwise noted)
Internal Startup Current Source
Drive Output
Pin 1 Output Impedance (or Rdson between Pin 1 and Pin 6 when SW1
is closed) Rload on Pin 1 = 680
Current Comparator and Thermal Shutdown
Input Bias Current @ 1.0 V Input Level on Pin 3
Maximum Internal Current Setpoint
Tj = 25°C
Tj = −40°C to +125°C
Default Internal Setpoint for Skip Cycle Operation and Standby
Detection
Leading Edge Blanking Duration
Hysteresis while in Temperature Shutdown (Note 3)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Verified by Design.
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5
NCP1230
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C,
VCC = 13 V, VPIN8 = 30 V unless otherwise noted.)
Characteristic
Symbol
Pin
Min
Typ
Max
Unit
Internal Oscillator
Oscillation Frequency, 65 kHz Version (Vfb = 2.5 V)
Tj = 25°C
Tj = 0°C to +125°C
Tj = −40°C to +125°C
fOSC
−
60
58
55
65
−
−
70
72
72
kHz
Oscillation Frequency, 100 kHz Version
Tj = 25°C
Tj = 0°C to +125°C
Tj = −40°C to +125°C
fOSC
−
93
90
85
100
−
−
107
110
110
kHz
Oscillation Frequency, 133 kHz Version
Tj = 25°C
Tj = 0°C to +125°C
Tj = −40°C to +125°C
fOSC
−
123
120
113
133
−
−
143
146
146
kHz
Internal Modulation Swing, in Percentage of Fsw (Vfb = 2.5 V) (Note 4)
−
−
−
"6.4
−
%
Internal Swing Period (Note 4)
−
−
−
5.0
−
ms
Dmax
−
75
80
85
%
Rup
3
9.0
18
36
k
−
3
−
2.3
−
Vpp
−
2
200
235
270
A
Iratio
−
−
2.8
−
−
Timeout before Validating Short−Circuit or PFC VCC (Note 4)
TDEL
−
−
125
−
ms
Latch−Off Level
Vlatch
3
2.7
3.0
3.3
V
Maximum Duty−Cycle (CS = 0, Vfb = 2.5 V)
Internal Ramp Compensation
Internal Resistor (Note 4)
Ramp Compensation Sawtooth Amplitude
Feedback Section
Opto Current Source (Vfb = 0.75 V)
Pin 3 to Current Setpoint Division Ratio (Note 4)
Protection
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Verified by Design.
TYPICAL PERFORMANCE CHARACTERISTICS
8.0
13.0
VPIN8 = 30 V
VPIN8 = 30 V
12.8
VCC(min) THRESHOLD (V)
VCC(off), THRESHOLD (V)
VCC = 0 V
12.6
12.4
12.2
12.0
−50
−25
0
25
50
75
100
125
7.8
7.6
7.4
7.2
7.0
−50
150
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. VCC(OFF) Threshold vs. Temperature
Figure 4. VCC(min) Threshold vs. Temperature
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6
NCP1230
TYPICAL PERFORMANCE CHARACTERISTICS
1.6
VPIN8 = 30 V
VCC = 13 V
5.8
1.35
5.6
ICC1 (mA)
VCC LATCH THRESHOLD (V)
6.0
5.4
1.1
0.85
5.2
5.0
−50
−25
0
25
50
75
100
125
0.6
−50
150
−25
Figure 5. VCC Latch Threshold vs. Temperature
50
75
125 150
100
800
VCC = 13 V
133 kHz
700
2.3
100 kHz
1.9
65 kHz
1.5
−50
−25
0
25
50
ICC3 (A)
2.7
ICC2 (mA)
25
Figure 6. ICC1 Internal Current Consumption, No Load
vs. Temperature
3.1
600
500
75
100
400
−50
125 150
−25
0
25
50
75
125 150
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. ICC2 Internal Current Consumption,
1.0 nF Load vs. Temperature
Figure 8. ICC3 Internal Consumption,
Latch−Off Phase vs. Temperature
5.0
4.0
VCC = VCC − 0.2 V
VPIN8 = 30 V
VPIN8 = 30 V
IC2 (mA)
3.0
4.0
2.5
2.0
−50
VCC = 0 V
4.5
3.5
IC1 (mA)
0
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
3.5
−25
0
25
50
75
100
125
150
3.0
−50
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. IC1 Startup Current vs. Temperature
Figure 10. IC2 Startup Current vs. Temperature
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7
150
NCP1230
TYPICAL PERFORMANCE CHARACTERISTICS
22.0
VCC = 13 V
LEAKAGE CURRENT (A)
VHV MINIMUM (V)
21.5
100
VCC = VCC(off) − 0.2 V
21.0
20.5
20.0
19.5
19.0
−50
−25
0
25
50
75
100
125
75
TJ = −40 °C
50
TJ = +25 °C
25
0
150
TJ = +125 °C
1
10
50
TJ, JUNCTION TEMPERATURE (°C)
DRIVE SINK RESISTANCE ()
DRIVE SOURCE RESISTANCE ()
VCC = 13 V
14
12
10
−25
0
25
50
75
100
14
850
950
VCC = 13 V
13
12
11
10
9.0
8.0
7.0
6.0
5.0
−50
125 150
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. Drive Source Resistance vs. Temperature
Figure 14. Drive Sink Resistance vs. Temperature
18
1.20
VCC = 13 V
VCC = 13 V
1.15
16
15
max
1.10
14
ILimit (V)
RPFC, RESISTANCE ()
800
15
16
13
12
1.05
typ
1.00
11
min
10
9.0
8.0
−50
600
Figure 12. Leakage Current vs. Temperature
18
17
400
VDRAIN, VOLTAGE (V)
Figure 11. Minimum Startup Voltage vs. Temperature
8.0
−50
200
0.95
−25
0
25
50
75
100
0.90
−50
125 150
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. RPFC vs. Temperature
Figure 16. ILimit vs. Temperature
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8
125
150
NCP1230
TYPICAL PERFORMANCE CHARACTERISTICS
1.40
800
VCC = 13 V
VCC = 13 V
1.35
Vstby−out (V)
Vskip (mV)
775
750
1.30
1.25
1.20
725
1.15
700
−50
−25
0
25
50
75
100
125
1.10
−50
150
−25
0
25
50
75
100
125
150
125
150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. Vskip vs. Temperature
Figure 18. Vstby−out vs. Temperature
80
4.0
VCC = 13 V
75
FREQUENCY (kHz)
SOFT−START (ms)
3.5
3.0
2.5
2.0
70
65
60
55
1.5
−50
−25
0
25
50
75
100
125
50
−50
150
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. Soft−Start vs. Temperature
Figure 20. Frequency (65 kHz) vs. Temperature
110
145
VCC = 13 V
VCC = 13 V
141
FREQUENCY (kHz)
106
FREQUENCY (kHz)
−25
102
98
94
137
133
129
90
−50
−25
0
25
50
75
100
125
125
−50
150
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. Frequency (100 kHz) vs. Temperature
Figure 22. Frequency (133 kHz) vs. Temperature
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9
150
NCP1230
81.0
10.0
VCC = 13 V
fosc = 65 kHz
VCC = 13 V
9.0
DUTY CYCLE MAX (%)
INTERNAL MODULATION SWING (%)
TYPICAL PERFORMANCE CHARACTERISTICS
8.0
7.0
6.0
5.0
4.0
−50
−25
0
25
50
75
100
80.5
80.0
79.5
79.0
−50
125 150
−25
TJ, JUNCTION TEMPERATURE (°C)
24
22
240
230
125 150
VCC = 13 V
18
16
12
210
−25
0
25
50
75
100
125
10
−50
150
−25
TJ, JUNCTION TEMPERATURE (°C)
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 25. Iopto vs. Temperature
Figure 26. Internal Ramp Compensation Resistor
vs. Temperature
3.50
150
140
3.25
130
Vlatch (V)
TDEL FAULT TIME DELAY (ms)
100
14
220
120
3.00
2.75
110
100
−50
75
20
250
Rup (k)
Iopto (A)
260
200
−50
50
Figure 24. Maximum Duty Cycle
vs. Temperature
Vfb = 0.75 V
270
25
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. Internal Modulation Swing
vs. Temperature
280
0
−25
0
25
50
75
100
125
150
2.50
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 27. Fault Time Delay vs. Temperature
Figure 28. Vlatch vs. Temperature
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10
125
150
NCP1230
OPERATING DESCRIPTION
Introduction
PFC_VCC
The NCP1230 is a current mode controller which provides
a high level of integration by providing all the required
control logic, protection, and a PWM Drive Output into a
single chip which is ideal for low cost, medium to high
power off−line application, such as notebook adapters,
battery chargers, set−boxes, TV, and computer monitors.
The NCP1230 can be connected directly to a high voltage
source providing lossless startup, and eliminating external
startup circuitry. In addition, the NCP1230 has a PFC_VCC
output pin which provides the bias supply power for a Power
Factor Correction controller, or other logic. The NCP1230
has an event management scheme which disables the
PFC_VCC output during standby, and overload conditions.
As shown on the internal NCP1230 diagram, an internal
low impedance switch SW1 routes Pin 6 (VCC) to Pin 1
when the power supply is operating under nominal load
conditions. The PFC_VCC signal is capable of delivering up
to 35 mA of continuous current for a PFC Controller, or
other logic.
Connecting the NCP1230 PFC_VCC output to a PFC
Controller chip is very straight forward, refer to the “Typical
Application Example” all that is generally required is a
small decoupling capacitor (0.1 F).
High Voltage
+
1
8
2
PFC_VCC
1
8
7
2
7
3
6
3
6
4
5
4
5
MC33262/33260
Vout
GND
NCP1230
Rsense
VCC Cap
GND
Figure 29. Typical Application Example
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11
NCP1230
Feedback
Ipk + 0.75
Rs @ 3
The feedback pin has been designed to be connected
directly to the open−collector output of an optocoupler. The
pin is pulled−up through a 20 k resistor to the internal
Vdd_fb supply (5 volts nominal). The feedback input signal
is divided down, by a factor of three, and connected to the
negative (−) input of the PWM comparator. The positive (+)
input to the PWM comparator is the current sense signal
(Figure 30).
The NCP1230 is a peak current mode controller, where
the feedback signal is proportional to the output power. At
the beginning of the cycle, the power switch is turns−on and
the current begins to increase in the primary of the
transformer, when the peak current crosses the feedback
voltage level, the PWM comparators switches from a logic
level low, to a logic level high, resetting the PWM latching
Flip−Flop, turning off the power switch until the next
oscillator clock cycle begins.
where:
Ipk @ Rs + 1V
where:
Pin = is the power level where the NCP1230 will go into
the skip mode
Lp = Primary inductance
f = NCP1230 controller frequency
L @ f @ Ipk2
Pin + p
2
Pin + Pout
Eff
where:
Eff = the power supply efficiency
Vdd_fb
2
Rout + Eout
Pout
20k
2
55k
FB
−
10 V
Ǹ2L@p P@inf
Ipk +
25k
PWM
+
+
2.3 Vpp
Ramp
Vskip
/ Vstby−out
1.25 V
+
S is rising edge triggered
R is falling edge triggered
−
125 ms
S
R
18k
3
LEB
Vdd_fb
Figure 30.
The feedback pin input is clamped to a nominal 10 volt for
ESD protection.
Vskip
Skip Mode
The feedback input is connected in parallel with the skip
cycle logic (Figure 31). When the feedback voltage drops
below 25% of the maximum peak current (1.0 V/Rsense) the
IC prevents the current from decreasing any further and
starts to blank the output pulses. This is called the skip cycle
mode. While the controller is in the burst mode the power
transfer now depends upon the duty cycle of the pulse burst
width which reduces the average input power demand.
PFC_VCC
−
FB
+
0.75 V
Latch
Reset
+
CS Cmp
Figure 31.
During the skip mode the PFC_Vcc signal (pin 1) is
asserted into a high impedance state when a light load
condition is detected and confirmed, Figure 32 shows
typical waveforms. The first section of the waveform shows
a normal startup condition, where the output voltage is low,
as a result the feedback signal will be high asking the
controller to provide the maximum power to the output. The
second phase is under normal loading, and the output is in
regulation. The third phase is when the output power drops
below the 25% threshold (the feedback voltage drops to 0.75
volts). When this occurs, the 125 msec timer starts, and if the
conditions is still present after the time output period, the
Vc + Ipk @ Rs @ 3
where:
Vc = control voltage (Feedback pin input),
Ipk = Peak primary current,
Rs = Current sense resistor,
3 = Feedback divider ratio.
SkipLevel + 3V @ 25% + 0.75V
www.onsemi.com
12
NCP1230
Ramp Compensation
NCP1230 confirms that the low output power condition is
present, and the internal SW1 opens, and the PFC_Vcc
signal output is shuts down. While the NCP1230 is in the
skip mode the FB pin will move around the 750 mV
threshold level, with approximately 100 mVp−p of
hysteresis on the skip comparator, at a period which depends
upon the (light) loading of the power supply and its various
time constants. Since this ripple amplitude superimposed
over the FB pin is lower than the second threshold (1.25
volt), the PFC_Vcc comparator output stays high (PFC_Vcc
output Pin 1 is low).
In Phase four, the output power demands have increases
and the feedback voltage rises above the 1.25 volts
threshold, the NCP1230 exits the skip mode, and returns to
normal operation.
In Switch Mode Power Supplies operating in Continuous
Conduction Mode (CCM) with a duty−cycle greater than
50%, oscillation will take place at half the switching
frequency. To eliminate this condition, Ramp Compensation
can be added to the current sense signal to cure sub harmonic
oscillations. To lower the current loop gain one typically
injects between 50 and 100% of the inductor down slope.
The NCP1230 provides an internal 2.3 Vpp ramp which
is summed internally through a 18 k resistor to the current
sense pin. To implement ramp compensation a resistor needs
to be connected from the current sense resistor, to the current
sense pin 3.
Example:
If we assume we are using the 65 kHz version of the
NCP1230, at 65 kHz the dv/dt of the ramp is 130 mV/s.
Assuming we are designing a FLYBACK converter which
has a primary inductance, Lp, of 350 H, and the SMPS has
a +12 V output with a Np:Ns ratio of 1:0.1. The OFF time
primary current slope is given by:
Max IP
Regulation
VFB
Ns
(Vout ) Vf) @ Np
= 371 mA/s or 37 mV/s
Skip + 60%
1.25 V
Lp
0.75 V
PFC is Off
PFC is Off
PFC is On
125 ms
Delay
when imposed on a current sense resistor (Rsense) of 0.1 .
If we select 75% of the inductor current downslope as our
required amount of ramp compensation, then we shall inject
27 mV/s.
With our internal compensation being of 130 mV, the
divider ratio (divratio) between Rcomp and the 18 k is
0.207. Therefore:
No Delay
PFC is On
Figure 32.
Rcomp + 18k @ divratio = 4.69 k
(1 * divratio)
Leaving Standby (Skip Mode)
2.3 V
When the feedback voltage rises above the 1.25 volts
reference (leaving standby) the skip cycle activity stops and
SW1 immediately closes and restarts the PFC, there is no
delay in turning on SW1 under these conditions, refer to
Figure 32.
0V
18 k
Current Sense
The NCP1230 is a peak current mode controller, where
the current sense input is internally clamped to 1.0 V, so the
sense resister is determined by Rsense = 1.0 V /Ipk
maximum.
There is a 18k resistor connected to the CS pin, the other
end of the 18k resistor is connect to the output of the internal
oscillator for ramp compensation (refer to Figure 33).
Rcomp
LEB
+
CS
−
Fb/3
Figure 33.
www.onsemi.com
13
Rsense
NCP1230
Leading Edge Blanking
isolated secondary output and on the auxiliary winding.
Because the auxiliary winding and diode form a peak
rectifier, the auxiliary Vcc capacitor voltage can be charged
up to the peak value rather than the true plateau which is
proportional to the output level.
To resolve these issues the NCP1230 monitors the 1.0 V
error flag. As soon as the internal 1.0 V error flag is asserted
high, a 125 ms timer starts. If at the end of the 125 ms timeout
period, the error flag is still asserted then the controller
determines that there is a true fault condition and stops the
PWM drive output, refer to Figure 35. When this occurs,
Vcc starts to decrease because the power supply is locked
out. When Vcc drops below UVLOlow (7.7 V typical), it
enters a latch−off phase where the internal consumption is
reduced down to 680 A (typical). The voltage on the Vcc
capacitor continues to drop, but at a lower rate. When Vcc
reaches the latch−off level (5.6 V), the current source is
turned on and pulls Vcc above UVLOhigh. To limit the fault
output power, a divide−by−two circuit is connected to the
Vcc pin that requires two startup sequences before
attempting to restart the power supply. If the fault has gone
and the error flag is low, the controller resumes normal
operations.
Under transient load conditions, if the error flag is
asserted, the error flag will normally drop prior to the 125 ms
timeout period and the controller continues to operate
normally.
If the 125 msec timer expires while the NCP1230 is in the
Skip Mode, SW1 opens and the PFC_Vcc output will shut
down and will not be activated until the fault goes away and
the power supply resumes normal operations.
While in the Skip Mode, to avoid any thermal runaway it
is desirable for the Burst duty cycle to be kept below
20%(the burst duty−cycle is defined as Tpulse / Tfault).
In Switch Mode Power Supplies (SMPS) there can be a
large current spike at the beginning of the current ramp due
to the Power Switch gate to source capacitance, transformer
interwinding capacitance, and output rectifier recovery
time. To prevent prematurely turning off the PWM drive
output, a Leading Edges Blanking (LEB) (Figure 34) circuit
is place is series with the current sense input, and PWM
comparator. The LEB circuit masks the first 250 ns of the
current sense signal.
2.3 Vpp
Ramp
3
CS
18 k
Thermal Shutdown
Skip
125 msec Timer
PWM Comparator
FB/3
+
Vccreset
LEB
10 V
250 ns
+
-
R Q
Latch−Off
S
3V
Figure 34.
Short−Circuit Condition
The NCP1230 is different from other controllers which
use an auxiliary windings to detect events on the isolated
secondary output. There maybe some conditions (for
example when the leakage inductance is high) where it can
be extremely difficult to implement short−circuit and
overload protection. This occurs because when the power
switch opens, the leakage inductance superimposes a large
spike on the switch drain voltage. This spike is seen on the
www.onsemi.com
14
NCP1230
12.6V
7.7V
125ms
125ms
125ms
125ms
Figure 35.
The latch−off phase can also be initiated, more classically,
when Vcc drops below UVLO (7.7 V typical). During this
fault detection method, the controller will not wait for the
Regulation
125 ms time−out, or the error flag before it goes into the
latch−off phase, operating in the skip mode under these
conditions, refer to Figure 36.
Fault
12.6 V
VCC PWM
Regulation
7.7 V
5.6 V
Timer
2.5 ms
SS
125 ms
125 ms
1V
Flag
PFC
VCC
Figure 36.
www.onsemi.com
15
NCP1230
Current Sense Input Pin Latch−Off
Vccoff (12.6 V typically), the current source is turned off
reducing the amount of power being dissipated in the chip.
The NCP1230 then turns on the drive output to the external
MOSFET in an attempt to increase the output voltage and
charge up the Vcc capacitor through the Vaux winding in the
transformer.
During the startup sequence, the controller pushes for the
maximum peak current, which is reached after the 2.5 ms
soft−start period. As soon as the maximum peak set point is
reached, the internal 1.0 V Zener diode actively limits the
current amplitude to 1.0 V/Rsense and asserts an error flag
indicating that a maximum current condition is being
observed. In this mode, the controller must determine if it is
a normal startup period (or transient load) or is the controller
is facing a fault condition. To determine the difference
between a normal startup sequence, and a fault condition, the
error flag is asserted, and the 125 ms timer starts to count
down. If the error flag drops prior to the 125 ms time−out
period, the controller resets the timer and determines that it
was a normal startup sequence and enables the low
impedance switch (SW1), enabling the PFC_Vcc output.
If at the end of the 125 ms period the error flag is still
asserted, then the controller assumes that it is a fault
condition and the PWM controller enters the skip mode and
does not enable the PFC_Vcc output.
The NCP1230 features a fast comparator (Figure 34) that
monitors the current sense pin during the controller off time.
If for any reason the voltage on pin 3 increases above 3.0 V,
the NCP1230 immediately stops the PWM drive pulses and
permanently stays latched off until the bias supply to the
NCP1230 is cycled down (Vcc must drop below 4.0 V, e.g.
when the user unplugs the converter from the mains). This
offers the designer the flexibility to implement an externally
shutdown circuit (for example for overvoltage or
overtemperature conditions). When the controller is latched
off through pin 3 (current sense), SW1 opens and shuts off
PFC_Vcc output.
Figure 37 shows how to implement the external latch via
a Zener diode and a simple PNP transistor. The PNP actually
samples the Zener voltage during the OFF time only, hence
leaving the CS information un−altered during the ON time.
Various component arrangements can be made, e.g. adding
a NTC device for the Over Temperature Protection (OTP).
HV
Vz
1
8
2
7
3
6
4
5
8
12.6 V/
5.6 V
1k
+
−
HV
3.2 mA or 0
6
Ramp
CVcc
CVcc
Aux
4
Figure 38.
ON Semiconductor recommends that the Vcc capacitor be at
least 47 F to be sure that the Vcc supply voltage does not drop
below Vccmin (7.7 V typical) during standby power mode and
unusual fault conditions.
Figure 37.
Connecting the PNP to the drive only activates the offset
generation during Toff. Here is a solution monitoring the
auziliary Vcc rail.
Soft−Start
Drive Output
The NCP1230 features an internal 2.5 ms soft−start
circuit. As soon as Vcc reaches a nominal 12.6 V, the
soft−start circuit is activated. The soft−start circuit output
controls a reference on the minus (−) input to an amplifier
(refer to Figure 39), the positive (+) input to the amplifier is
the feedback input (divided by 3). The output of the
amplifier drives a FET which clamps the feedback signal. As
the soft−start circuit output ramps up, it allow the feedback
pin input to the PWM comparator to gradually increased
from near zero up to the maximum clamping level of 1.0
V/Rsense. This occurs over the entire 2.5 ms soft−start
period until the supply enters regulation. The soft−start is
also activated every time a restart is attempted. Figure 40
shows a typical soft−start up sequence.
The NCP1230 provides a Drive Output which can be
connected through a current limiting resistor to the gate of
a MOSFET. The Driver output is capable of delivering drive
pulses with a rise time of 40 ns, and a fall time of 15 ns
through its internal source and sink resistance of 12.3 ohms
(typical), measured with a 1.0 nF capacitive load.
Startup Sequence
The NCP1230 has an internal High Voltage Startup
Circuit (Pin 8) which is connected to the high voltage DC
bus (Refer to Figure 36). When power is applied to the bus,
the NCP1230 internal current source (typically 3.2 mA) is
biased and charges up the external Vcc capacitor on pin 6,
refer to Figure 38. When the voltage on pin 6 (Vcc) reaches
www.onsemi.com
16
NCP1230
Vdd_fb
Vdd
20k
2
55k
FB
Error
Skip
Comparators
10V
25k
CS
+
PWM
+
-
Soft−Start
Ramp (1V max)
Figure 39.
VCC
12.6 V
0 V (Fresh PON)
or
6 V (OCP)
Current
Sense
Max IP
2.5 ms
Figure 40. Soft−Start is Activated during a Startup
Sequence or an OCP Condition
www.onsemi.com
17
2.5 msec
SS Timer
OSC
NCP1230
NCP1230 offers a nominal ±6.4% deviation of the nominal
switching frequency. The sweep sawtooth is internally
generated and modulates the clock up and down with a 5 ms
period. Figure 41 illustrates the NCP1230 behavior:
Frequency Jittering
Frequency jittering is a method used to soften the EMI
signature by spreading out the average switching energy
around the controller operating switching frequency. The
62.4 kHz
Internal Ramp
65 kHz
67.6 kHz
Internal Sawtooth
5 ms
Figure 41. An Internal Ramp is used to Introduce Frequency Jittering on the Oscillator Saw Tooth
Thermal Protection
drops below 4.0 volts and the Vccreset circuit is activated,
the controller will restart. If the user is using a fixed bias
supply (the bias supply is provided from a source other than
from an auxiliary winding, refer to the typical application )
and Vcc is not allow to drop below 4.0 volts under a thermal
shutdown condition, the NCP1230 will not restart. This
feature is provided to prevent catastrophic failure from
accidentally overheating the device.
An internal Thermal Shutdown is provided to protect the
integrated circuit in the event that the maximum junction
temperature is exceeded. When activated (165°C typically)
the controller turns off the PWM Drive Output. When this
occurs, Vcc will drop (the rate is dependent on the NCP1230
loading and the size of the Vcc capacitor) because the
controller is no longer delivering drive pulses to the
auxiliary winding charging up the Vcc capacitor. When Vcc
www.onsemi.com
18
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−7 (PDIP−8 LESS PIN 7)
CASE 626B
ISSUE D
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. NOT USED
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98AON12198D
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PDIP−7 (PDIP−8 LESS PIN 7)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−7
CASE 751U−01
ISSUE E
DATE 20 OCT 2009
SCALE 1:1
−A−
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5
−B− S
0.25 (0.010)
B
M
M
1
4
G
C
R
X 45 _
J
−T−
SEATING
PLANE
H
0.25 (0.010)
K
M
D 7 PL
M
T B
S
A
DIM
A
B
C
D
G
H
J
K
M
N
S
INCHES
MIN MAX
0.189 0.197
0.150 0.157
0.053 0.069
0.013 0.020
0.050 BSC
0.004 0.010
0.007 0.010
0.016 0.050
0_
8_
0.010 0.020
0.228 0.244
S
GENERIC
MARKING DIAGRAM
SOLDERING FOOTPRINT*
8
1.52
0.060
7.0
0.275
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
1
XXX
A
L
Y
W
G
4.0
0.155
0.6
0.024
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
1.270
0.050
SCALE 6:1
XXXXX
ALYWX
G
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
98AON12199D
DESCRIPTION:
7−LEAD SOIC
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−7
CASE 751U−01
ISSUE E
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6.
7. NOT USED
8. EMITTER
DATE 20 OCT 2009
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. NOT USED
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. NOT USED
8. SOURCE, #1
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5.
6.
7. NOT USED
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6.
7. NOT USED
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. NOT USED
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR (DIE 1)
2. BASE (DIE 1)
3. BASE (DIE 2)
4. COLLECTOR (DIE 2)
5. COLLECTOR (DIE 2)
6. EMITTER (DIE 2)
7. NOT USED
8. COLLECTOR (DIE 1)
STYLE 9:
PIN 1. EMITTER (COMMON)
2. COLLECTOR (DIE 1)
3. COLLECTOR (DIE 2)
4. EMITTER (COMMON)
5. EMITTER (COMMON)
6. BASE (DIE 2)
7. NOT USED
8. EMITTER (COMMON)
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. NOT USED
8. GROUND
STYLE 11:
PIN 1. SOURCE (DIE 1)
2. GATE (DIE 1)
3. SOURCE (DIE 2)
4. GATE (DIE 2)
5. DRAIN (DIE 2)
6. DRAIN (DIE 2)
7. NOT USED
8. DRAIN (DIE 1)
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. NOT USED
8. COMMON CATHODE
DOCUMENT NUMBER:
98AON12199D
DESCRIPTION:
7−LEAD SOIC
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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