NCP1370
Product Preview
Dimmable Quasi-Resonant
Primary Side Current-Mode
Controller for LED TV
Backlight
The NCP1370 is a PWM current mode controller targeting isolated
flyback and non−isolated constant current topologies. The controller
operates in a quasi−resonant mode to provide high efficiency. Thanks
to a novel control method, the device is able to precisely regulate a
constant LED current from the primary side. This removes the need
for secondary side feedback circuitry, biasing and an opto−coupler.
The device is highly integrated with a minimum number of external
components. A robust suite of safety protection is built in to simplify
the design. This device supports analog/digital dimming and both
modes can be combined to enhance dimming precision. The NCP1370
has a programmable peak current limit to optimize design
compatibility over a wide range of applications. The controller
features a standby mode with reduced current consumption.
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QUASI−RESONANT PWM
CONTROLLER FOR
LED DRIVERS
MARKING
DIAGRAM
8
8
1
SOIC−8
D SUFFIX
CASE 751
NCP1370x
ALYW
G
1
Features
•
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•
•
•
•
•
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•
NCP1370 = Specific Device Code
Quasi−resonant Peak Current−mode Control Operation
x
= Device Option (A or B)
A
= Assembly Location
Primary Side Sensing (no opto−coupler needed)
L
= Wafer Lot
Wide VCC Range
Y
= Year
Source 300 mA / Sink 500 mA Totem Pole Driver with 12 V Gate
W
= Work Week
G
= Pb−Free Package
Clamp
Precise LED Constant Current Regulation ±1% Typical
Line Feed−forward for Enhanced Regulation Accuracy
PIN CONNECTIONS
Low LED Current Ripple
1
ILIM
DIM
500 mV ±1.2% Guaranteed Voltage Reference for Current
ZCD
VIN
Regulation
CS
VCC
Programmable Cycle−by−Cycle Peak Current Limit
GND
DRV
Low VCC(on) Allowing to use a Standby Power Supply to Power the
(Top View)
Device
Analog or Digital Dimming
ORDERING INFORMATION
Wide Temperature Range of −40 to + 125°C
See detailed ordering and shipping information in the package
Robust Protection Features
dimensions section on page 18 of this data sheet.
♦ LED Open Circuit Protection
♦ VCC Over Voltage Protection
♦ Secondary Diode Short Protection
♦ Output Short Circuit Protection
♦ Shorted Current Sense Pin Fault Detection
Typical Applications
♦ Brown−out
♦ VCC Under Voltage Lockout
• TV Backlight
♦ Thermal Shutdown
• Lighting with Auxiliary Power Supply
Pb−free, Halide−free MSL1 Product
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. P1
1
Publication Order Number:
NCP1370/D
NCP1370
.
Aux
.
.
VDIM
1
8
2
7
3
6
4
5
VBIAS
Figure 1. Typical Application Schematic for NCP1370
Table 1. PRODUCTS TABLE
Block or Electrical Parameter
Brown−out blanking time tBO(blank)
Blanking circuit for leakage inductance reset detection
VCC OVP
Switching cycles count before activating the output diode short circuit
protection: VCS > VCS(stop)
NCP1370B
NCP1370A
100 ms
2 ms
ON
ON
Auto−recovery
Latched
4 cycles
4 cycles
Output Diode Short Circuit protection
Auto−recovery
Latched
Adjustable OVP Auto−recovery timer
1 second
4 seconds
CS short circuit protection (impedance measurement before startup)
ON
OFF
High mains valley switching
3rd
2nd
(all HL valleys incremented by 1)
Propagation delay from ZCD to DRV high state tZCD(DEM)
ON
ON
Table 2. PIN FUNCTION DESCRIPTION
Pin N5
Pin Name
Function
Pin Description
2nd
1
ILIM
Peak current limit and
over current protection
This pin sets the cycle−by−cycle peak current limit threshold and the threshold for
secondary diode short detection
2
ZCD
Zero Crossing Detection
Connected to the auxiliary winding, this pin detects the core reset event.
3
CS
Current sense
This pin monitors the primary peak current.
4
GND
−
The controller ground
5
DRV
Driver output
The driver’s output to an external MOSFET
6
VCC
Supplies the controller
This pin is connected to an external power supply.
7
VIN
Brown−Out
Input voltage sensing
Over Voltage Protection
This pin observes the HV rail and protects the circuit in case of low main conditions.
This pin also sense the line voltage for the valley selection and the line feed−forward
A Zener diode can also be used to pull−up the pin and stop the controller for
adjustable OVP protection
8
DIM
Analog / PWM dimming
This pin is used for analog or PWM dimming control. An analog signal than can
be varied between VDIM(EN) and VDIM100 can be used to vary the current, or a
PWM signal with an amplitude greater than VDIM100.
This pin is also used for the OFF mode
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2
NCP1370
Internal Circuit Architecture
Disable
CS_NOK
Internal
Thermal
Shutdown
VCC
UVLO
VCC Management
Standby
Aux_SCP
Peak Current Limits
Threshold
Generation
VILIMIT
VCC_OVP
VCC Over Voltage
Protection
Ipkmax
VCS(stop)
VREF
OFF
OVP2
Fault
Management
ILIM
VDD
STOP
CS_STOP
BO_NOK
Qdrv
ZCD
VREF
VVIN
VCC
Clamp
Circuit
Zero Crossing Detection
Valley Selection
Aux. Winding
Short Circuit Prot.
S
Aux_SCP
V VIN
DRV
Qdrv
Q
VVLY
R
Line
Feedforward
STOP
V REF
OFF Mode
Detection
Standby
CS
Leading
Edge
Blanking
Constant−Current
Control
DIM
CS_reset
Dimming
Type
Detection
VDIMA
Ipkmax STOP
Enable V DIMA
VILIMIT
Max. Peak
Current
Limit
VIN
CS Short
Protection
GND
VCS(stop)
Disable
V VIN
Ipkmax
Winding and
Output diode
Short Circuit
Protection
BO_NOK
Brown−Out
CS_NOK
OVP2
CS_STOP
Figure 2. Internal Circuit Architecture
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3
Over Voltage
Protection
NCP1370
Table 3. MAXIMUM RATINGS TABLE
Symbol
Rating
Value
Unit
VCC(MAX)
ICC(MAX)
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum current for VCC pin
−0.3, +35
Internally limited
V
mA
VDRV(MAX)
IDRV(MAX)
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3, VDRV (Note 1)
−500, +800
V
mA
VMAX
IMAX
Maximum voltage on low power pins (except pins DIM, DRV and VCC)
Current range for low power pins (except pins DRV and VCC)
−0.3, +5.5
−2, +5
V
mA
VDIM(MAX)
Maximum voltage for DIM pin
−0.3, +7
V
RθJ−A
Thermal Resistance Junction−to−Air
289
°C/W
TJ(MAX)
Maximum Junction Temperature
150
°C
Operating Temperature Range
−40 to +125
°C
Storage Temperature Range
−60 to +150
°C
ESD Capability, HBM model (Note 2)
4
kV
ESD Capability, MM model (Note 2)
200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC unless otherwise noted.
2. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per Mil−Std−883, Method 3015.
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V)
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Test Condition
Symbol
Min
Typ
Max
VCC increasing
VCC decreasing
VCC decreasing
VCC(on)
VCC(off)
VCC(HYS)
VCC(reset)
11
9
1.8
9
12
9.5
−
9.5
13
10
–
10
Over Voltage Protection
VCC OVP threshold
VCC(OVP)
26
28
30
V
VCC(off) noise filter
VCC(reset) noise filter
tVCC(off)
tVCC(reset)
–
–
5
20
–
–
ms
ICC(start)
–
−
100
mA
−
250
Description
Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Hysteresis VCC(on) – VCC(off)
Internal logic reset equal to VCC(off)
V
Startup current
Starting time from exiting OFF Mode to
1st
DRV pulse
tCC(start)
Supply Current
Device Disabled/Fault
Device Enabled/No output load on pin 5
Device Switching (Fsw = 65 kHz)
ms
mA
VCC > VCC(off)
Fsw = 65 kHz
CDRV = 470 pF,
Fsw = 65 kHz
Supply Current in OFF mode
ICC1
ICC2
ICC3
0.8
–
–
1.2
2.3
2.7
ICC(off)
1.4
4.0
5.0
50
mA
210
mA
CURRENT SENSE AND ILIM PIN
ILIM(REF)
Reference current for maximum peak current limit threshold
190
Minimum value for internal VILIMIT
VpinILIM < 0.5 V
VILIMIT(MIN)
Maximum value for internal VILIMIT
Pin ILIM open
VILIMIT(MAX)
Difference between internal VILIMIT and ILIM pin voltage
VpinILIM = 1.5 V
VILIMIT(offset)
−30
VCS(stop) at VpinILIM = 1.5 V
VpinILIM = 1.5 V
VCS(stop)1
Leading Edge Blanking Duration for VILIM (Tj = −40°C to
125°C)
Minimum on−time (equal to tLEB)
Propagation delay from current detection to gate off−state
Maximum on−time
4. Guaranteed by design
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4
200
0.5
2.34
V
2.6
2.86
V
30
mV
2.037
2.1
2.163
V
tLEB
280
330
380
ns
ton(MIN)
280
330
380
ns
tILIM
–
50
150
ns
ton(MAX)
37.5
50
62.5
ms
NCP1370
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V)
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
Minimum threshold value for immediate fault protection activation
VpinILIM < 0.5 V
VCS(stop)MIN
0.7
V
Minimum threshold value for immediate fault protection activation
Pin ILIM open
VCS(stop)MAX
3.64
V
CURRENT SENSE AND ILIM PIN
Ratio between internal VCS(stop) and internal VILIMIT
KSTOP/ILIMIT
140
%
Leading Edge Blanking Duration for VCS(stop)
tBCS
–
200
–
ns
Current source for CS to GND short detection
ICS(short)
400
500
600
mA
Timer for measuring CS to GND short
tCS(short)
12
17
22
ms
Drive Resistance
DRV Sink
DRV Source
RSNK
RSRC
–
–
13
30
–
–
Drive current capability
DRV Sink (Note 4)
DRV Source (Note 4)
ISNK
ISRC
–
–
500
300
–
–
GATE DRIVE
W
mA
Rise Time (10 % to 90 %)
CDRV = 470 pF
tr
–
40
–
ns
Fall Time (90 % to 10 %)
CDRV = 470 pF
tf
–
30
–
ns
DRV Low Voltage
VCC = VCC(off)+0.2 V
CDRV = 470 pF,
RDRV=33 kW
VDRV(low)
8
–
–
V
DRV High Voltage
VCC = 30 V
CDRV = 470 pF,
RDRV=33 kW
VDRV(high)
10
12
14
V
ZCD threshold voltage
VZCD increasing
VZCD(THI)
30
50
70
mV
ZCD threshold voltage (Note 4)
VZCD decreasing
VZCD(THD)
20
40
60
mV
ZCD hysteresis (Note 4)
VZCD increasing
VZCD(HYS)
8
–
–
mV
VZCD(short)
0.8
1
1.2
V
tOVLD
70
90
110
ms
trecovery
3
4
5
ZERO VOLTAGE DETECTION CIRCUIT
Threshold voltage for output short circuit or aux. winding
short circuit detection
Short circuit detection Timer
VZCD < VZCD(short)
Auto−recovery timer duration
Input clamp voltage
High state
Low state
s
V
Ipin1 = 3.0 mA
Ipin1 = −2.0 mA
VZCD(CH)
VZCD(CL)
–
−0.9
8
−0.6
–
−0.3
Propagation Delay from valley detection to DRV high
VZCD decreasing
tZCD(DEM)
−
−
480
ns
Delay from valley lockout output to DRV latch set
VZCD decreasing
tLEB4
125
250
375
ns
Blanking delay after on−time
VREF > 100 mV
tZCD(BLANK1)
1.2
1.6
2
ms
Blanking delay after on−time at light load
VREF < 75 mV
tZCD(BLANK2)
0.6
0.8
1
ms
tTIMO
5
6.5
8
ms
Timeout after last demag transition
LINE FEED−FORWARD
KLFF
15
17
19
mA/V
Ioffset(MAX)
67.5
76.5
85.5
mA
Reference Voltage (after division by 2) (Tj = 25°C)
VREF
495
500
505
mV
Reference Voltage (after division by 2) (Tj = 0°C to 85°C)
VREF
492
500
508
mV
Reference Voltage (after division by 2) (Tj =−40°C to 125°C)
VREF
488
500
512
mV
VVIN to ICS(offset) conversion ratio
Offset current maximum value
VpinVIN = 4.5 V
CONSTANT CURRENT CONTROL
4. Guaranteed by design
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5
NCP1370
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V)
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
VCS(low)
25
55
85
mV
CONSTANT CURRENT CONTROL
Current sense lower threshold for detection of the leakage
inductance reset time
Blanking time for leakage inductance reset detection
tCS(low)
130
ns
VREF value below which the ZCD blanking time is divided by
2 (light load)
VREF decreases
VREF(off)
75
mV
VREF value above which ZCD blanking time is tZCD(blank1)
VREF increases
VREF(on)
100
mV
Threshold for line range detection Vin increasing
(1st to 2nd valley or 1st to 3rd transition for VREF > 0.375 V)
VVIN increases
VHL
2.28
2.4
2.52
V
Threshold for line range detection Vin decreasing
(2nd to 1st valley or 1st to 3rd transition for VREF > 0.375 V)
VVIN decreases
VLL
2.18
2.3
2.42
V
tHL(blank)
15
25
35
ms
VREF decreases
VVLY1−2/2−3
350
373
396
VREF increases
VVLY2−1/3−2
366
390
414
VREF decreases
VVLY2−4/3−5
231
248
265
VREF increases
VVLY4−2/5−3
249
267
285
VREF decreases
VVLY4−7/5−8
–
150
–
VREF increases
VVLY7−4/8−5
–
165
–
VREF decreases
VVLY7−11/8−12
–
75
–
VREF increases
VVLY11−7/12−8
–
100
–
VREF decreases
VVLY11−13/12−15
–
30
–
VREF increases
VVLY13−11/15−12
–
40
–
VREF decreases
VVLY1−2/2−3
70
74.5
79
VREF increases
VVLY2−1/3−2
73
78
83
VREF decreases
VVLY2−4/3−5
46
49.5
53
VREF increases
VVLY4−2/5−3
50
53.5
57
VREF decreases
VVLY4−7/5−8
–
30
–
VREF increases
VVLY7−4/8−5
–
33
–
VREF decreases
VVLY7−11/8−12
–
15
–
VREF increases
VVLY11−7/12−8
–
20
–
VREF decreases
VVLY11−13/12−15
–
6
–
VREF increases
VVLY13−11/15−12
–
8
–
VALLEY SELECTION
Blanking time for line range detection
Valley thresholds (VREF = 500 mV)
1st to 2nd valley transition at LL and 2nd to 3rd valley HL
(3rd to 4th valley HL for version B) VREF decreases
2nd to 1st valley transition at LL and 3rd to 2nd valley HL
(4th to 3rd valley HL for version B), VREF incr.
2nd to 4th valley transition at LL and 3rd to 5th valley HL
(4th to 6th valley HL for version B), VREF decr.
4th to 2nd valley transition at LL and 5th to 3rd valley HL
(6th to 4th valley HL for version B), VREF incr.
4th to 7th valley transition at LL and 5th to 8th valley HL
(6th to 9th valley HL for version B), VREF decr.
7th to 4th valley transition at LL and 8th to 5th valley HL
(9th to 6th valley HL for version B), VREF incr.
7th to 11th valley transition at LL and 8th to 12th valley HL
(9th to 13th valley HL for version B), VREF decr.
11th to 7th valley transition at LL and 12th to 8th valley HL
(13th to 9th valley HL for version B), VREF incr.
11th to 13th valley transition at LL and 12th to 15th valley HL
(13th to 16th valley HL for version B), VREF decr.
13th to 11th valley transition at LL and 15th to 12th valley HL
(16th to 13th valley HL for version B), VREF incr.
Valley thresholds in percentage of VREF
1st to 2nd valley transition at LL and 2nd to 3rd valley HL
(3rd to 4th valley HL for version B) VREF decreases
2nd to 1st valley transition at LL and 3rd to 2nd valley HL
(4th to 3rd valley HL for version B), VREF incr.
2nd to 4th valley transition at LL and 3rd to 5th valley HL
(4th to 6th valley HL for version B), VREF decr.
4th to 2nd valley transition at LL and 5th to 3rd valley HL
(6th to 4th valley HL for version B), VREF incr.
4th to 7th valley transition at LL and 5th to 8th valley HL
(6th to 9th valley HL for version B), VREF decr.
7th to 4th valley transition at LL and 8th to 5th valley HL
(9th to 6th valley HL for version B), VREF incr.
7th to 11th valley transition at LL and 8th to 12th valley HL
(9th to 13th valley HL for version B), VREF decr.
11th to 7th valley transition at LL and 12th to 8th valley HL
(13th to 9th valley HL for version B), VREF incr.
11th to 13th valley transition at LL and 12th to 15th valley HL
(13th to 16th valley HL for version B), VREF decr.
13th to 11th valley transition at LL and 15th to 12th valley HL
(16th to 13th valley HL for version B), VREF incr.
mV
4. Guaranteed by design
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6
%
NCP1370
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V)
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
DIMMING SECTION
DIM pin voltage for zero output current (OFF voltage)
VDIM decreasing
VDIM(EN)
0.67
0.7
0.73
V
VDIM(EN) comparator hysteresis
VDIM increasing
VEN(HYS)
−
50
−
mV
VDIM100
2.9
3
3.1
V
DIM pin voltage for maximum output current (TJ = −40 to
125°C)
DIM pin voltage for maximum output current at TJ = 25°C
VDIM100
2.94
3
3.06
V
Dimming range
VDIM(range)
–
2.3
–
V
Clamping voltage for DIM pin
VDIM(CLP)
–
7
–
V
Dimming pin pull−up current source
IDIM(pullup)
–
5
–
mA
TSHDN
130
150
170
°C
TSHDN(HYS)
–
50
–
°C
VBO(on)
0.90
1
1.10
V
THERMAL SHUTDOWN
Thermal Shutdown (Note 4)
Device switching
(FSW around 65 kHz)
Thermal Shutdown Hysteresis (Note 4)
BROWN−OUT AND OVP
Brown−Out ON level (IC start pulsing)
VVIN increasing
Brown−Out OFF level (IC shuts down)
VVIN decreasing
VBO(off)
0.85
0.9
0.95
V
BO comparators delay
tBO(delay)
–
30
–
ms
Brown−Out blanking time for version A
tBO(blank1)
1.4
2
2.6
ms
Brown−Out blanking time for version B
tBO(blank2)
50
100
150
ms
IBO(bias)
−250
–
250
nA
VVIN(clamp)
3.9
4.1
4.3
Brown−out pin bias current
Clamped voltage (VIN pin left open)
VIN pin open
VIN pin Clamp series resistor
VIN pin detection level for OVP
RVIN(clamp)
VVIN increasing
VOVP
1
4.75
5
V
kW
5.25
V
tOVP(delay)
50
ms
Adjustable OVP auto−recovery timer (version B)
tOVP(recovery1)
1
s
Adjustable OVP auto−recovery timer (version A)
tOVP(recovery2)
4
s
Delay before OVP confirmation
4. Guaranteed by design
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NCP1370
Application Information
The NCP1370 is a LED driver for flyback and
non−isolated buck−boost / SEPIC converters. It implements
a current−mode architecture quasi−resonant architecture to
prevent valley−jumping instability. A proprietary circuitry
ensures accurate regulation of the output current without the
need of a secondary side feedback. The circuit features
powerful protections to ensure a robust LED driver design
without the need of extra external components or
overdesign.
• Quasi−Resonance Current−Mode Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCP1370 optimizes the
efficiency by switching in the valley of the MOSFET
drain−source voltage. Thanks to smart control
algorithm, the controller locks−out in a selected valley
and remains locked until the input voltage or the output
current set point significantly changes.
• Primary Side Constant Current Control: thanks to a
proprietary circuit, the controller accurately controls the
output current without requiring a secondary side
feedback (no optocoupler needed). An output current
deviation below ±2% is typically obtained.
• VCC Over Voltage Protection: if the voltage on VCC
pin exceeds an internal limit, the controller shuts down
and waits 4 seconds before restarting pulsing (version
B) or stays latched (A version).
• Adjustable peak current limit: the cycle−by−cycle
maximum peak current limit and the second over
current protection level can be adjusted externally by
connecting a resistor between ILIM pin and ground.
• Brown−Out: the controller includes a brown−out
circuit which safely stops the controller in case the
input voltage is too low. The device will automatically
restart if the line recovers.
• Adjustable Over voltage protection: By connecting a
zener diode to the VIN pin, an adjustable over voltage
protection can be implemented to protect against open
LEDs. Upon detection, the controller waits 4 s
(version A) or 1 s (version B) before attempting to
restart switching.
• Cycle−by−cycle peak current limit: when the current
sense voltage exceeds pin ILIM voltage VILIM, the
•
•
•
•
•
MOSFET is turned off for the rest of the switching
cycle.
Winding Short−Circuit Protection (2nd over current
protection level): an additional comparator with a short
LEB filter (tBCS) senses the CS signal and stops the
controller if VCS reaches 140% of VILIMIT). For noise
immunity reasons, this comparator is enabled only
during the main LEB duration tLEB.
Output Short−circuit protection: If a very low
voltage is applied on ZCD pin for 90 ms (nominal), the
controllers assume that the output or the ZCD pin is
shorted to ground and enters shutdown. After waiting
for 4 seconds, the controller restarts switching.
Linear or PWM dimming: the DIM pin allows
implementing both analog and PWM dimming.
OFF Mode: The IC enters in OFF mode after detecting
a fault and whenever the DIM pin voltage stays low
during more than 4 seconds. In this mode, the IC is off
and has a reduced current consumption. This allows
simplifying the PCB design around the ON/OFF
opto−coupler.
Floating or Short pin detection: The NCP1370
protections help passing safety tests. For instance, the
circuit stops operating when the CS pin is grounded or
when the GND pin is open.
Constant Current Control
Capitalizing on the constant current control technique
developed in the NCL3008X product, the NCP1370
accurately regulates the output current of a flyback
converter from its primary side.
By connecting the clamping capacitor of the flyback
converter to the sense resistor as shown in the typical
application schematic (Figure 1), we have an image of the
drain current waveform and of the leakage inductance
current waveform. Thus, by looking at the current sense pin
waveform, the controller is able to detect the reset of the
transformer leakage inductance. Indeed, the leakage
inductance limits the output rectifier peak current as shown
in Figure 3 where it is shown that: Nsp * ID,pk < IL,pk.
Also, by monitoring the auxiliary winding voltage
through the ZCD pin, we can detect the end of conduction
of the secondary rectifier.
www.onsemi.com
8
NCP1370
IL,pk
NspID,pk
Ipri(t)
Isec(t)
time
T2
t1
ton
tdemag
Vaux(t)
time
Figure 3. Flyback Currents and Auxiliary Winding Voltage in DCM
The constant current control block picks up the leakage
inductor current, the end of conduction of the output rectifier
and controls the drain current to maintain the output current
constant.
We have:
I out +
V REF
2N spR sense
R sense +
V REF
2N spI out
(eq. 2)
From (Equation 1), the first key point is that the output
current is independent of the inductor value. Moreover, the
leakage inductance does not influence the output current
value as the reset time is taken into account by the controller.
(eq. 1)
Soft−Start
Where:
• VREF is the output current internal reference
• Nsp is the secondary to primary transformer turns ratio:
Nsp = Ns / Np
• Rsense is the current sense resistor
At startup or after recovering from a fault, there is a small
internal soft−start of 200 ms maximum.
In addition, during startup, as the output voltage is zero
volts, the demagnetization time is long and the constant
current control block will slowly increase the peak current
towards its nominal value as the output voltage grows.
Figure 5 shows a soft−start simulation example for a 9 W
LED power supply.
The output current value is set by choosing the sense
resistor:
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9
NCP1370
16.0
(V)
12.0
1
Vout
2
I out
4
VControl
3
VCS
8.00
4.00
0
800m
(A)
600m
400m
200m
0
800m
(V)
600m
400m
200m
0
604u
1.47m
2.34m
time in seconds
3.21m
4.07m
Figure 4. Startup Simulation showing the Natural Soft−start
V ILIMIT + V ILIM + I LIM(REF)R ILIM
Adjustable Cycle−by−Cycle Current Limit
The pin ILIM allows adjusting the threshold for maximum
peak current limit VILIMIT and also the 2nd over current
protection (OCP2) threshold VCS(stop) which helps
protecting against short circuit of the secondary winding or
of the output diode.
More precisely, the maximum peak current threshold
VILIMIT is equal to the ILIM pin voltage and VCS(stop) value
is derived from VILIMIT. By connecting a resistor between
ILIM and GND pins, the value of internal cycle−by−cycle
current limit VILIMIT is:
(eq. 3)
The threshold for immediate short circuit protection
VCS(stop) is given by:
V CS(stop) + 1.4 @ V ILIMIT
(eq. 4)
Practically, VILIMIT can be adjusted from 0.5 V to 2.6 V,
meaning VCS(stop) range is from 0.7 V to 3.64 V.
When the current sense voltage exceeds the internal
threshold VILIMIT, the MOSFET is turned off for the rest of
the switching cycle. Figure 5 shows the schematic of ILIM
pin.
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10
NCP1370
Vdd
V ILIM(MAX)
ILIM(REF)
Clamp
ILIM
Buffer
VILIM
Gain
VCS(stop)
Clamp
RILIM
V ILIM(MIN)
VILIM
Figure 5. Block Diagram of ILIM Pin
Winding and Output diode Short−Circuit Protection
(OCP2)
The cycle−by−cycle peak current limit threshold VILIMIT
also set the maximum duty cycle for a given application.
The maximum duty cycle is given by:
D MAX + 1 *
V REF
t
* v
V ILIMIT T sw
In parallel with the cycle−by−cycle sensing of the CS pin,
another comparator with a reduced LEB (tBCS ) and a higher
threshold (VCS(stop)) is able to sense winding short−circuit
and stop the controller. In version B, the controller stops the
DRV pulses after counting 4 cycles of VCS > VCS(stop). The
controller attempts to re−start after waiting 4 seconds. In
version A, after counting 4 cycles of VCS > VCS(stop), the
controller stays latched.
The controller is unlatched by one of the 3 following events:
• VCC < VCC(off)
• Standby by VDIM < VDIM(EN) during 4 seconds
• BO_NOK becomes high
(eq. 5)
Where:
• tv is the valley duration
• Tsw is the switching period
For switching frequencies below 100 kHz, the term tv/Tsw
can be neglected:
D MAX [ 1 *
V REF
V ILIMIT
(eq. 6)
After being unlatched, the controller goes into OFF Mode.
S
DRV
Q
Vdd
aux
UVLO
Q
CS
Vcc
management
R
LEB1
+
Vcontrol
PWMreset
−
4−s timer
+
VCCreset
Ipkmax
−
VILIMIT
LEB2
STOP
+
−
CS_STOP
1 pulse
or
4 pulses
S
OFF
Q
VCS(stop)
Q
R
4−s timer
from Fault Management Block
Figure 6. Winding Short Circuit Protection, Max. Peak Current Limit Circuits
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11
VCC
NCP1370
PWM or Linear Dimming Detection
Practically, when VDIM < VDIM(EN), the controller
decreases the peak current from its current state to nearly
zero before stopping the DRV pulses.
This allows having a very good correlation between the
dimming duty−cycle and the output current value when
dimming at low duty−cycle.
Also, it is important to note that for good correlation
between the dimming duty−cycle (which represent the
expected output current value relative to the nominal value)
and the actual measured output current, the high state
duration of the dimming signal should not be below 200 ms.
Figure 8 shows the drain source waveform during
soft−stop.
The pin DIM allows dimming the LED light. Analog
dimming or digital (PWM) dimming can be used.
If the power supply designer apply an analog signal
varying from VDIM(EN) to VDIM100 to the DIM pin, the
output current will increase or decrease proportionally to the
voltage applied. For VDIM = VDIM100, the power supply
delivers the maximum output current.
If a voltage lower than VDIM(EN) is applied to the DIM pin,
the DRV pulses are disabled. Thus, for digital dimming, a
PWM signal with a low state value lower than VDIM(EN) and
a high state value higher than VDIM100 should be applied.
The DIM pin is pulled up internally by a small current
source or resistor. Thus, if the pin is left open, the controller
is able to start.
OFF Mode with DIM Pin
The OFF Mode is entered when VDIM stays below
VDIM(EN) for 4 seconds. In this mode, IC consumption is
reduced to ICC(off) (below 50 mA). The OFF mode is exited
only when VDIM becomes higher than VDIM(EN)+VEN(HYS).
Soft Stop during PWM Dimming
The NCP1370 features an internal soft−stop of 200 ms
maximum in order to compensate the output current
decrease caused by the soft−start during PWM dimming.
VDIM
3V
0.7 V
Analog dimming
V DIM100
100% Iout
V DIM(EN)
0% Iout
PWM dimming
Deep PWM dimming
Figure 7. Pin DIM Chronograms
VDIM
Vdrain
Figure 8. Soft−stop
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12
NCP1370
goes through a complete sequence OFF Mode → FAULT
Mode (see Fault Management section for more information)
In the latched mode, the controller stops pulsing and waits
that one of the 3 following events occurs to reset the latch:
• VCC < VCC(off)
• Standby by VDIM < VDIM(EN) during 4 seconds
• BO_NOK becomes high
When the OVP Latch is reset, the controller goes into OFF
Mode.
VCC Over Voltage Protection
In order to protect itself against too high supply voltage,
the controller features an over voltage protection for the VCC
pin. When the VCC voltage reaches the VCC(OVP) threshold,
the controller stops the DRV pulses and shutdown.
Depending on the version, the controller goes in
auto−recovery mode (version B) or in latched mode
(version A).
In the auto−recovery mode, the controller waits 4 s and
tries to re−start. In order to restart pulsing, the controller
VCC
VCC(OVP)
OVP
VCC(on)
VCC(off)
VDIM
VDIM(100)
VDIM(EN)
STATE
VDRV
RESET
OFF
RUN
4−s Timer
RUN
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
FAULT
CS impedance check
OFF
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
FAULT
CS impedance check
Figure 9. VCC Over Voltage Protection Chronograms
Valley Selection
The input voltage is sensed by the VIN pin. The internal
logic selects the operating valley according to VIN pin
voltage and DIM pin voltage.
By default, when the output current is not dimmed, the
controller operates in the first valley at low line and in the
second valley at high line for version A. For version B, the
controller operates in the 3rd valley at high line. Table 5
summarizes the valley selected by the controller as a
function of the output current and the input voltage. The
numbers in blue are the selected valleys for version B.
Quasi−Square wave resonant systems have a wide
switching frequency excursion. The switching frequency
increases when the output load decreases or when the input
voltage increases. The switching frequency of such systems
must be limited.
The NCP1370 changes valley as the input voltage
increases and as the output current set−point is varied during
dimming. This limits the switching frequency excursion.
Once a valley is selected, the controller stays locked in the
valley until the input voltage or the output current set−point
varies significantly.
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13
NCP1370
Table 5. VALLEY SELECTION
VIN pin voltage for valley change
Iout value at which the
controller changes valley
(Iout decreasing)
0
−− LL −−
100%
75%
50%
30%
15%
2.3 V
−− HL −−
(Iout increasing)
5V
100%
1st
2nd (3rd)
2nd
3rd (4th)
4th
5th (6th)
7th
8th (9th)
11th
12th (13th)
13th
15th (16th)
78%
Iout increases
Iout decreases
Iout value at which the
controller changes valley
VVIN decreases
53%
33%
20%
6%
8%
0%
0
−− LL −−
2.4 V
−− HL −−
0%
5V
VVIN increases
VIN pin voltage for valley change
Zero Crossing Detection Block
At startup or in case of extremely damped free
oscillations, the ZCD comparator may not be able to detect
the valleys. To avoid such a situation, the NCP1370 features
a Time−Out circuit that generates pulses if the voltage on
ZCD pin stays below the 55−mV threshold for 6.5 ms.
The Time−out also acts as a substitute clock for the valley
detection and simulates a missing valley in case of too
damped free oscillations (Figure 11).
The ZCD pin allows detecting when the drain−source
voltage of the power MOSFET reaches a valley.
A valley is detected when the voltage on pin 1 crosses
down the 55−mV internal threshold.
In order to decrease the capacitor value needed on ZCD
pin to turn−on the MOSFET right in the valley or in some
case remove it, a small delay (250 ns) is added internally
before turning−on the MOSFET.
Tblank
Time−Out
ZCD
.
VZCD(TH)
+
Clock
−
Tblank
VZCD(short)
+
−
90−ms
Timer
Enable_b
S
Q
Q
R
4−s Timer
Figure 10. ZCD Block Schematic
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14
Aux_SCP
NCP1370
3
4
high
The 3rd valley is
validated
14
2nd , 3rd
low
high
VZCD
V ZCD(th )
12
The 2nd valley is detected
By the ZCD comparator
The 3rd valley is not detected by
the ZCD comp
low
high
15
low
ZCD
comp
16
TimeOut adds a pulse to account for the
missing 3rd valley
high
low
TimeOut
17
Clock
Figure 11. Time−out Chronograms
Output Short Circuit Protection
Line Feed−Forward
Because of the time−out function, if the ZCD pin or the
auxiliary winding is shorted, the controller will continue
switching leading to improper regulation of the LED
current.
Moreover during an output short circuit, the controller
will strive to maintain the constant current operation.
In order to avoid these scenarios, a secondary timer starts
counting when the ZCD voltage is below the VZCD(short)
threshold (Figure 10). If this timer reaches 90 ms, the
controller detects a fault and enters the auto−recovery fault
mode: the controller stops pulsing and waits 4−s before
going through a complete startup sequence.
This protection is disabled when VDIM < VDIM(EN).
Because of the propagation delays, the MOSFET is not
turned−off immediately when the current set−point is
reached. As a result, the primary peak current is higher than
expected and the output current increases. To compensate
the peak current increase brought by the propagation delays,
a positive voltage proportional to the line voltage is added
on the current sense signal. The amount of offset voltage can
be adjusted using the RCS resistor as shown in Figure 12.
V CS(offset) + K LFF V pinVIN R CS
(eq. 7)
The offset voltage is applied only during the MOSFET
on−time.
This offset voltage is always applied over the load range.
www.onsemi.com
15
NCP1370
noise delay
+
−
S
Q
Bulk rail
VOVP
OVP2
Q
R
Aux
4−s Timer
(1-s Timer version B)
vDD
VIN
.
I CS(offset)
CS
RCS
Clamp
Rclamp
R sense
Q_drv
Vclamp
+
Blanking
time
−
BO_NOK
1 V if BONOK high
0.9 V if BONOK low
Figure 12. Line Feed−Forward, Adjustable OVP and Brown−out Schematic
Adjustable Over Voltage Protection
A clamping circuit on VIN pin limits the voltage
excursion to 4.1 V (Figure 12). This level is high enough to
allow good linearity of the line feedforward current for
universal mains applications with an input voltage up to
265 V rms.
When the zener diode starts conducting, it injects current
inside the clamping circuit and the voltage on VIN pin
increases. When VVIN exceeds VOVP during tOVP(delay), the
circuit detects an over voltage condition and stops the DRV
pulses. The controller waits until the OVP timer
(tOVP(recovery)) has elapsed (4 s for version A, 1 s for
version B) and restarts switching.
•
Brown−out
In order to protect the supply against a very low input
voltage, the NCP1370 features a brown−out circuit with a
fixed ON/OFF threshold (Figure 12). The controller is
allowed to start if a voltage higher than 1 V is applied to the
VIN pin and shuts−down if the VIN pin voltage decreases
and stays below 0.9 V when the BO blanking timer has
elapsed (BO_NOK high). When a brown−out condition is
detected, the circuit stops pulsing and goes into the OFF
mode detailed in the “Fault Management Section”.
110 W typically, the circuit does not start pulsing and
shutdown. The circuit attempts to restart after waiting 4
seconds. In practice, it is recommended to place a
minimum of 250 W in series between the CS pin and
the current sense resistor to take into account parasitic
component effect and electrical parameters tolerance.
Fault of GND pin connection
If the GND pin is properly connected, the current
drawn from the positive terminal of the VCC capacitor
flows out of the GND pin to return to the negative
terminal of the VCC capacitor. If the GND pin is not
connected, the circuit ESD diodes offer another return
path. The accidental non−connection of the GND pin is
monitored by detecting that one of the ESD diode is
conduction. Practically, the ESD diode of CS pin is
monitored. If such a fault is detected for 200 ms, the
circuit stops generating DRV pulses.
Fault Management and Startup Sequence
Figure 13 and Figure 14 shows the state diagrams of the
NCP1370.
OFF Mode
At startup, as long as VCC is not high enough, the
controller is reset. Its current consumption is ICC(start). When
VCC > VCC(on), the controller goes in OFF mode and waits
for the enable signal (VDIM > VDIM(EN)). In OFF mode, the
IC consumption is very low (50 mA maximum).
Pin Connection Faults
• CS pin Short to ground
The circuit senses the CS pin impedance every time it
starts−up. If the measured impedance does not exceed
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16
NCP1370
• An Output / Auxiliary winding Short circuit is detected:
The OFF mode is exited only if VCC > VCC(on) and VDIM
> VDIM(EN). The controller then goes in FAULT mode.
More generally, the OFF mode is entered upon the
following events:
• VCC < VCC(off)
• Brown−out edge
• VDIM < VDIM(EN) after 4 seconds
• Die over temperature (TSD)
• The 4−s auto−recovery timer has elapsed
“Aux_SCP high”
• Second OCP level triggered
When the 4−s timer has elapsed, the controller goes in
OFF Mode.
Adjustable OVP Management
When the adjustable OVP on VIN pin is triggered, the
controller stops the DRV pulses and starts the OVP2 Timer
(4 s in version A, 1 s in version B).
When the OVP2 timer has elapsed, the controller goes in
FAULT mode and restart switching if no other fault is
detected.
FAULT Mode
In this mode, the controller measures CS pin impedance.
If CS pin is not shorted the controller is allowed to start the
DRV pulses. If CS pin is shorted, the controller starts the 4
seconds timer. No DRV pulse is generated in this mode.
Latched Protection (VCC OVP, Output Diode Short
Circuit Protection in Version A)
When VCC > VCC(OVP) or when the 2nd OCP is triggered,
the DRV pulses stop and the controller is latched
(Figure 14).
The Latch resets when one of the 3 following events occurs:
• VCC < VCC(off)
• VDIM < VDIM(EN) during 4 seconds
• BO_NOK becomes high
AR Mode
In the auto−recovery mode, the 4 seconds timer is
counting, DRV is not pulsing. The 4 seconds timer starts
counting when:
• VDIM < VDIM(EN)
• A short circuit on CS pin is detected
• VCC > VCC(OVP)
RESET
Timer ends (AR_end)
or BO_NOK edge
or TSD_end
or VCC < VCC(off)
VddINT POR
VCC too
low
OFF
BO_NOK edge
or TSD_end
or VCC < VCC(off)
BO_NOK edge
or TSD_end
or VCC < VCC(off)
VDIM > VDIM(EN)
and VCC > VCC(on)
Timer ends
OVP2
Timer
FAULT mode
OVP2
CS_OK
OVP2
CS_short high
or VCC_OVP high
or VDIM < VDIM(EN)
AR
mode
VDIM > VDIM(EN) and
all other faults low
RUN
VCC_OVP high or VDIM < VDIM(EN)
or CS_stop or Aux_SCP
à Controller is dead
With states: RESET
à Controller is in OFF Mode, ICC = ICC(off) (50 μA max.)
OFF
FAULT Mode à No switching, ICC = ICC1
à Controller is switching
RUN
à the 4−s auto−recovery timer is counting, No switching
AR Mode
OVP2 Timer à The OVP2 Timer (4−s or 1−s) is counting, No DRV pulses
Figure 13. Fault State Diagram with Auto−recovery Faults
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17
NCP1370
RESET
VddINT POR
VCC too
low
Timer ends (AR_end) or BO_NOK edge
or TSD_end or VCC < VCC(off)
OFF
BO_NOK edge
or TSD_end
or VCC < VCC(off)
BO_NOK edge
or TSD_end
or VCC < VCC(off)
VDIM > VDIM(EN)
and VCC > VCC(on)
Timer ends
OVP2
Timer
VCC < VCC(off) or BO_NOK high
or VDIM < VDIM(EN) during 4 s
FAULT mode
CS_short high
or VDIM < VDIM(EN)
OVP2
AR
mode
LATCH
VCC_OVP high
CS_OK
OVP2
VDIM > VDIM(EN) and
all other faults low
VDIM < VDIM(EN) or Aux_SCP
RUN
VCC_OVP high or CS_stop
With states: RESET
OFF
FAULT Mode
RUN
AR Mode
OVP2 Timer
à Controller is dead
à Controller is in OFF Mode, CC
I = ICC(off) (50 μA max.)
à No switching, ICC = ICC1
à Controller is switching
à the 4−s auto−recovery timer is counting, No switching
à The OVP2 Timer (4−s or 1−s) is counting, No DRV pulses
Figure 14. Fault State Diagram with Latched Faults
ORDERING INFORMATION
Device
NCP1370BDR2G
Package Type
Shipping†
SOIC−8
(Pb free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
18
NCP1370
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
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