DATA SHEET
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Cost Effective Power Factor
Controller
8
NCP1606
SO−8
D SUFFIX
CASE 751
The NCP1606 is an active power factor controller specifically
designed for use as a pre−converter in electronic ballasts, ac−dc
adapters and other medium power off line converters (typically up to
300 W). It embeds a Critical Conduction Mode (CRM) scheme that
substantially exhibits unity power factor across a wide range of input
voltages and power levels. Housed in a SOIC−8 package, the
NCP1606 minimizes the number of external components. Its
integration of comprehensive safety protection features makes it an
excellent driver for rugged PFC stages.
General Features
•
•
•
•
•
•
•
•
•
“Unity” Power Factor
No Need for Input Voltage Sensing
Latching PWM for Cycle by Cycle On Time Control (Voltage Mode)
High Precision Voltage Reference (±1.6% over temperature ranges)
Very Low Startup Current Consumption (≤ 40 mA)
Low Typical Operating Current (2.1 mA)
−500 mA / +800 mA Totem Pole Gate Driver
Undervoltage Lockout with Hysteresis
Pin to Pin Compatible with Industry Standards
MARKING DIAGRAM
8
1
x
A
L
Y
W
G
1606x
ALYW
G
= A or B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTION
Feedback
Control
Ct
CS
VCC
Drive
Ground
ZCD/STDWN
(Top View)
ORDERING INFORMATION
Safety Features
•
•
•
•
1
See detailed ordering and shipping information in the package
dimensions section on page 20 of this data sheet.
Programmable Overvoltage Protection
Protection against Open Loop (Undervoltage Protection)
Accurate and Programmable On Time Limitation
Overcurrent Limitation
Typical Applications
• Electronic Light Ballast
• AC Adapters, TVs, Monitors
• All Off Line Appliances Requiring Power Factor Correction
© Semiconductor Components Industries, LLC, 2010
September, 2022 − Rev. 9
1
Publication Order Number:
NCP1606/D
NCP1606
LBOOST
VOUT
DBOOST
LOAD
(Ballast,
SMPS, etc.)
RZCD
+
EMI
Filter
AC Line
ROUT1
Cin
4
6
GND
Ct
5
CS ZCD
Ct
+
CBULK
7
Ctrl DRV
3
ROUT2
8
CC
2
Ccomp
VCC
NCP1606
FB V
1
RSENSE
Figure 1. Typical Application
VCC
Shutdown
VOUT
nPOK
+
FB
300
mV
(Enable EA)
E/A −
ESD +
Enable
VCONTROL
Control
ESD
LBOOST
Ct
RSENSE
uVDD
Fault
nPOK
270 mA
PWM
−
+
Add VEAL
Offset
ESD
SQ
DRV
CS
VDD Reg
Static OVP
VEAL
Clamp Static OVP is triggered
when clamp is activated.
VDD
Ct
VDD
VDDGD
VEAH
Clamp
LEB
ESD
+
+
−
ZCD
RZCD
+
VCL(POS)
Clamp
2.1 V
+
−
+
VCL(NEG)
Active
Clamp
−
+
R Q
OCP
VCS(limit)
VDD
+
AC IN
UVLO
Dynamic OVP
Measure
IEAsink
VDD
2.5 V
CCOMP
+
−
Isink>Iovp
+
DBOOST
ROUT2
ESD
+
ROUT1
CBULK
VCC
UVP
−
+
1.6 V
Demag
+
−
RQ
RQ
VddGD
Off Timer
200 mV
uVDD
DRV
S Q
S Q
Reset
Shutdown
VCC
UVLO
uVDD
S Q
GND
RQ
S Q
POK
RQ
nPOK
*All SR Latches are Reset Dominant
*All values shown are typical only. Refer to the “Electrical Characteristics”
for complete specifications.
Figure 2. Block Diagram
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2
NCP1606
PIN FUNCTION DESCRIPTION
Pin Number
Name
Function
1
Feedback (FB)
2
Control
3
Ct
4
Current Sense
(CS)
5
Zero Current
Detection (ZCD)
6
Ground (GND)
7
Drive (DRV)
The powerful integrated driver is suitable to effectively switch a high gate charge power MOSFET.
8
VCC
This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 12 V (typ)
and turns off when VCC goes below 9.5 V (typ). After startup, the operating range is 10.3 V to 20 V.
The FB pin makes available the inverting input of the internal error amplifier. A simple resistor divider
scales and delivers the output voltage to the FB pin to maintain regulation. The feedback information
is also used for the programmable overvoltage and undervoltage protections.
The regulation block output is available on this pin. A compensation network is placed between FB
and Control to set the loop bandwidth low enough to yield a high power factor ratio and a low THD.
The Ct pin sources a 270 mA current to charge an external timing capacitor. The circuit controls the power
switch on time by comparing the Ct voltage to an internal voltage derived from the regulation block.
This pin limits the pulse by pulse current through the switch MOSFET when connected as show in
Figure 1. When the voltage exceeds 1.7 V (A version) or 0.5 V (B version), the drive turns off. The
maximum switch current can be adjusted by changing the sense resistor.
The voltage of an auxiliary winding should be applied to this pin to detect the moment when the coil is
demagnetized for critical conduction mode operation. Ground ZCD to shutdown the part.
Connect this pin to the pre−converter ground.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Supply Voltage
VCC
−0.3 to 20
V
Supply Current
ICC
±20
mA
DRV Voltage
VDRV
−0.3 to 20
V
DRV Current
IDRV
−800 to 500
mA
FB Voltage
VFB
−0.3 to 10
V
FB Current
IFB
±10
mA
Control Voltage
VControl
−0.3 to 10
V
Control Current
mA
IControl
−2 to 10
Ct Voltage
VCt
−0.3 to 6
V
Ct Current
ICt
±10
mA
CS Voltage
VCS
−0.3 to 6
V
CS Current
ICS
±10
mA
ZCD Voltage
VZCD
−0.3 to 10
V
ZCD Current
IZCD
±10
mA
PD(SO)
RqJA(SO)
450
178
mW
°C/W
TJ
−40 to +125
°C
TJ(MAX)
150
°C
TSTG
−65 to 150
°C
TL
300
°C
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation @ TA = 70°C
Thermal Resistance Junction−to−Air
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1.
This device series contains ESD protection and exceeds the following tests:
Pins 1−6, 8: Human Body Model 2000 V per JEDEC Standard JESD22−A114E,
Machine Model Method 200 V per JEDEC Standard JESD22−A115−A
Pin 7: Human Body Model 2000 V per JEDEC Standard JESD22−A114E,
Machine Model Method 180 V per JEDEC Standard JESD22−A115−A
2. This device contains latch−up protection and exceeds ±100 mA per JEDEC Standard JESD78.
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3
NCP1606
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified: For typical values, TJ = 25°C. For min/max values, TJ = −40°C to +125°C, VCC = 12 V, FB = 2.4 V, CDRV =
1 nF, Ct = 1 nF, CS = 0 V, Control = open, ZCD = open)
Symbol
Rating
Min
Typ
Max
Unit
VCC(on)
VCC Startup Threshold (Undervoltage Lockout Threshold, Vcc rising)
−25°C < TJ < +125°C
−40°C < TJ < +125°C
11.0
10.9
12.0
12.0
13.0
13.1
VCC(off)
VCC Disable Voltage after Turn On (Undervoltage Lockout Threshold, VCC falling)
−25°C < TJ < +125°C
−40°C < TJ < +125°C
8.7
8.5
9.5
9.5
10.3
10.5
HUVLO
Undervoltage Lockout Hysteresis
2.2
2.5
2.8
V
Icc consumption during startup: 0 V < VCC < VCC(on) − 200 mV
−
20
40
mA
ICC1
Icc consumption after turn on at VCC = 12 V, No Load, 70 kHz switching
−
1.4
2.0
mA
ICC2
Icc consumption after turn on at VCC = 12 V, 1 nF Load, 70 kHz switching
−
2.1
3
mA
Icc consumption after turn on at VCC = 12 V, 1 nF Load, no switching
(such as during OVP fault, UVP fault, or grounding ZCD)
−
1.2
1.6
mA
2.475
2.465
2.460
2.50
2.50
2.50
2.525
2.535
2.540
V
Vref Line Regulation from VCC(on) + 200 mV < VCC < 20 V, @ TJ = 25°C
−2
−
2
mV
Error Amplifier Current Capability:: (Note 3)
Sink (Control = 4 V, VFB = 2.6 V):
Source (Control = 4 V, VFB = 2.4 V):
8.0
−20
17
−6.0
30
−2
VCC UNDERVOLTAGE LOCKOUT SECTION
V
V
DEVICE CONSUMPTION
ICC(startup)
ICC(fault)
REGULATION BLOCK (ERROR AMPLIFIER)
VREF
VREF(line)
IEA
Voltage Reference
@ TJ = 25 °C
−25°C < TJ < +125°C
−40°C < TJ < +125°C
mA
GOL
Open Loop, Error Amplifier Gain (Note 4)
−
80
−
dB
BW
Unity Gain Bandwidth (Note 4)
−
1
−
MHz
IFB
FB Bias Current @ VFB = 3 V
−500
−
500
nA
IControl
Control Pin Bias Current @ FB = 0 V and Control = 4.0 V.
−1
−
1
mA
VEAH
VCONTROL @ IEASOURCE = 0.5 mA, VFB = 2.4 V
4.9
5.3
5.7
V
VEAL
VCONTROL @ IEASINK = 0.5 mA, VFB = 2.6 V
1.85
2.1
2.4
V
VEA(diff) = VEAH − VEAL. Difference between max and min Control voltages
3.0
3.2
3.4
V
Overcurrent Protection Threshold:
NCP1606A
NCP1606B
1.6
0.45
1.7
0.5
1.8
0.55
tLEB
Leading Edge Blanking duration
150
250
350
ns
tCS
Overcurrent protection propagation delay.
40
100
170
ns
ICS
CS bias current @ VCS = 2 V
−1
−
1
mA
VEA(diff)
CURRENT SENSE BLOCK
VCS(limit)
V
ZERO CURRENT DETECTION
VZCDH
Zero Current Detection Threshold (VZCD rising)
1.9
2.1
2.3
V
VZCDL
Zero Current Detection Threshold (VZCD falling)
1.45
1.6
1.75
V
VZCDH − VZCDL
300
500
800
mV
Maximum ZCD bias Current @ VZCD = 5 V
−2
−
+2
mA
5
5.7
6.5
V
5.0
8.5
−
mA
VZCD(HYS)
IZCD
VCL(POS)
Upper Clamp Voltage @ IZCD = 2.5 mA
ICL(POS)
Current Capability of the Positive Clamp at VZCD = VCL(POS) + 200 mV:
3. Parameter values are valid for transient conditions only.
4. Parameter characterized and guaranteed by design, but not tested in production.
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NCP1606
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified: For typical values, TJ = 25°C. For min/max values, TJ = −40°C to +125°C, VCC = 12 V, FB = 2.4 V, CDRV =
1 nF, Ct = 1 nF, CS = 0 V, Control = open, ZCD = open)
Symbol
Rating
Min
Typ
Max
Unit
VCL(NEG)
Negative Active Clamp Voltage @ IZCD = −2.5 mA
0.45
0.6
0.75
V
ICL(NEG)
Current Capability of the Negative Active Clamp:
in normal mode (VZCD = 300 mV)
in shutdown mode (VZCD = 100 mV)
2.5
35
3.7
70
5.0
100
mA
mA
VSDL
Shutdown Threshold (VZCD falling)
150
200
250
mV
VSDH
Enable Threshold (VZCD rising)
−
290
350
mV
Shutdown Comparator Hysteresis
−
90
−
mV
Zero current detection propagation delay
−
100
170
ns
tSYNC
Minimum detectable ZCD pulse width
−
70
−
ns
tSTART
Drive off restart timer
75
180
300
ms
243
235
270
270
297
297
mA
−
−
100
ns
2.9
2.9
3.2
3.2
3.3
3.4
V
−
150
220
ns
34
9.0
8.7
40
10.4
−
45
11.8
12.1
−
−
30
8.5
−
−
VSDHYS
tZCD
RAMP CONTROL
ICHARGE
tCT(discharge)
Charge Current (VCT = 0 V)
−25°C < TJ < +125°C
−40°C < TJ < +125°C
Time to discharge a 1 nF Ct capacitor from VCT = 3.4 V to 100 mV.
VCTMAX
Maximum Ct level before DRV switches off
tPWM
Propagation delay of the PWM comparator
−25°C < TJ < +125°C
−40°C < TJ < +125°C
OVER AND UNDERVOLTAGE PROTECTION
IOVP
IOVP(HYS)
Dynamic overvoltage protection (OVP) triggering current:
NCP1606A
NCP1606B @ TJ = 25°C
NCP1606B @ TJ = −40°C to +125°C
Hysteresis of the dynamic OVP current before the OVP latch is released:
NCP1606A
NCP1606B
VOVP
Static OVP Threshold Voltage
VUVP
Undervoltage protection (UVP) threshold voltage
mA
mA
VEAL +
100 mV
V
0.25
0.3
0.4
V
Gate Drive Resistance:
ROH @ ISOURCE = 100 mA
ROH @ ISOURCE = 20 mA
ROL @ ISINK = 100 mA
ROL @ ISINK = 20 mA
−
−
−
−
12
12
6
6
18
18
10
10
trise
Drive voltage rise time from 10% VCC to 90% VCC with CDRV = 1 nF and VCC = 12 V.
−
30
80
ns
tfall
Drive voltage fall time from 90% VCC to 10% VCC with CDRV = 1 nF and VCC = 12 V.
−
25
70
ns
Driver output voltage at VCC = VCC(on) − 200 mV and Isink = 10 mA
−
−
0.2
V
GATE DRIVE SECTION
ROH
ROL
VOUT(start)
W
3. Parameter values are valid for transient conditions only.
4. Parameter characterized and guaranteed by design, but not tested in production.
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5
NCP1606
274
14
272
12
270
10
Ct = 1 nF
ON TIME (ms)
268
266
4
262
2
260
−50
−25
0
25
50
75
100
125
0
150
0
1
2
3
4
5
6
TEMPERATURE (°C)
VCONTROL (V)
Figure 3. Oscillator Charge Current (ICHARGE)
vs. Temperature
Figure 4. Typical On Time (TON) vs. VCONTROL
Level
PWM PROPAGATION DELAY (ns)
170
3.25
3.20
3.15
3.10
3.05
3.00
−50
−25
0
25
50
75
100
125
150
140
−25
0
25
50
75
100
150
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. Maximum Ct Level (VCTMAX) vs.
Temperature
Figure 6. PWM Comparator Propagation Delay
(tPWM) vs. Temperature
2.505
100
2.500
80
200
160
GAIN
2.495
60
2.490
2.485
2.480
2.475
2.470
−50
160
130
−50
150
GAIN (dB)
MAXIMUM Ct LEVEL (V)
6
264
3.30
REFERENCE VOLTAGE (V)
8
−25
0
25
50
75
100
125
150
120
PHASE
PHASE (°)
OSCILLATOR CHARGE CURRENT (mA)
TYPICAL CHARACTERISTICS
40
80
20
40
0
0
−20
10E+0 100E+0
1E+3
10E+3
100E+3
−40
1E+6 10E+6
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 7. Reference Voltage (VREF) vs.
Temperature
Figure 8. Error Amplifier Open Loop Gain (GOL)
and Phase
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NCP1606
TYPICAL CHARACTERISTICS
DYNAMIC OVP CURRENT (mA)
IOVP
40
35
30
IOVP(HYS)
25
20
−50
SWITCHING SUPPLY CURRENT (ICC2) (mA)
12
−25
0
25
50
75
100
125
11
IOVP
10
9
8
−25
0
25
50
75
100
125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Overvoltage Activation Current vs.
Temperature for the A Version
Figure 10. Overvoltage Activation Current vs.
Temperature for the B Version
2.20
24
2.15
22
2.10
2.05
2.00
1.95
1.90
−50
IOVP(HYS)
7
−50
150
STARTUP CURRENT (mA)
DYNAMIC OVP CURRENT (mA)
45
−25
0
25
50
75
100
125
20
18
16
14
12
10
−50
150
−25
0
25
50
75
100
125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Supply Current (ICC2) vs.
Temperature
Figure 12. Startup Current ICC(startup) vs.
Temperature
13
200
RESTART TIMER (ms)
SUPPLY VOLTAGE (V)
VCC(on)
12
11
10
VCC(off)
9
8
−50
−25
0
25
50
75
100
125
150
190
180
170
160
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Supply Voltage Thresholds vs.
Temperature
Figure 14. Restart Timer (tSTART) vs.
Temperature
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150
NCP1606
TYPICAL CHARACTERISTICS
280
16
14
LEB FILTER DURATION (ns)
ROH
12
10
8
ROL
6
4
2
0
−50
−25
0
25
50
75
100
125
270
260
250
240
−50
150
−25
0
25
50
75
100
125
150
TEMPERATURE (°C)
Figure 16. LEB Duration (tLEB) vs. Temperature
A VERSION OVERCURRENT THRESHOLD (V)
TEMPERATURE (°C)
Figure 15. Output Gate Drive Resistance (ROH
and ROL) at 100 mA vs. Temperature
0.520
1.710
0.515
1.705
A
1.700
0.510
0.505
1.695
B
1.690
0.500
1.685
0.495
1.680
0.490
1.675
0.485
1.670
−50
−25
0
25
50
75
100
125
0.480
150
TEMPERATURE (°C)
B VERSION OVERCURRENT THRESHOLD (V)
OUTPUT DRIVE RESISTANCE (W)
18
Figure 17. Overcurrent Threshold VCS(limit) vs.
Temperature
0.35
0.320
SHUTDOWN THRESHOLD (V)
UVP THRESHOLD (V)
0.315
0.310
0.305
0.300
0.295
0.290
0.285
0.280
−50
−25
0
25
50
75
100
125
150
0.30
VSDH
0.25
VSDL
0.20
0.15
−50
TEMPERATURE (°C)
−25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 19. Shutdown Thresholds vs.
Temperature
Figure 18. Undervoltage Protection Threshold
(VUVP) vs. Temperature
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150
NCP1606
Introduction
The NCP1606 is a voltage mode power factor correction
(PFC) controller designed to drive cost effective
pre−converters to meet input line harmonic regulations.
This controller operates in critical conduction mode
(CRM) for optimal performance in applications up to about
300 W. Its voltage mode scheme enables it to obtain unity
power factor without the need for a line sensing network.
The output voltage is accurately controlled by a high
precision error amplifier. The controller also implements a
comprehensive array of safety features for robust designs.
The key features of the NCP1606 are as follows:
• Constant on time (Voltage Mode) CRM operation.
High power factor ratios are easily obtained without
the need for input voltage sensing. This allows for
optimal standby power consumption.
• Accurate and Programmable On Time Limitation. The
NCP1606 using an accurate current source and an
external capacitor to generate the on time.
• High Precision Voltage Reference. The error amplifier
reference voltage is guaranteed at 2.5 V ±1.6% over
process and temperature. This results in very accurate
output voltages.
• Very Low Startup Consumption. The circuit
consumption is reduced to a minimum (< 40 mA)
during the startup phase which allows fast, low loss,
charging of VCC. The architecture of the NCP1606
gives a controlled undervoltage lockout level and
provides ample VCC hysteresis during startup.
• Powerful Output Driver. A −500 mA / +800 mA totem
pole gate driver is used to provide rapid turn on and
turn off times. This translates into improved
efficiencies and the ability to drive higher power
MOSFETs. Additionally, a combination of active and
passive circuitry is used to ensure that the driver
output voltage does not float high while VCC is below
its turn on level.
• Programmable Overvoltage Protection (OVP). The
adjustable OVP feature protects the PFC stage against
excessive output overshoots that could damage the
application. These events can typically occur during
the startup phase or when the load is abruptly
removed. The NCP1606B gives a lower OVP
threshold, which can further reduce the application’s
standby power loss.
• Protection against Open Loop (Undervoltage
Protection). Undervoltage protection (UVP) disables
the PFC stage when the output voltage is excessively
low. This also protects the circuit in case of a failure in
the feedback network: if no voltage is applied to FB
because of a bad connection, UVP is activated and
shuts down the pre−converter.
• Overcurrent Limitation. The peak current is accurately
limited on a pulse by pulse basis. The level is
adjustable by modifying the switch sense resistor. The
•
NCP1606B uses a lower overcurrent threshold, which
can further reduce the application’s power dissipation.
An integrated LEB filter reduces the chance of noise
prematurely triggering the overcurrent limit.
Shutdown Features. The PFC pre−converter can be
easily placed in a shutdown mode by grounding either
the FB pin or the ZCD pin. During this mode, the ICC
current consumption is reduced and the error amplifier
is disabled.
Application information
Most electronic ballasts and switching power supplies
use a diode bridge rectifier and a bulk storage capacitor to
produce a dc voltage from the utility ac line (Figure 20).
This DC voltage is then processed by additional circuitry
to drive the desired output.
Rectifiers
AC
Line
Converter
+
Bulk
Storage
Capacitor
Load
Figure 20. Typical Circuit without PFC
This simple rectifying circuit draws power from the line
when the instantaneous ac voltage exceeds the capacitor
voltage. Since this occurs near the line voltage peak, the
resulting current draw is non sinusoidal and contains a very
high harmonic content. This results in a poor power factor
(typically < 0.6) and consequently, the apparent input
power is much higher than the real power delivered to the
load. Additionally, if multiple devices are tied to the same
input line, the effect is magnified and a “line sag” effect can
be produced (see Figure 21).
Vpk
Rectified DC
0
Line
Sag
AC Line Voltage
0
AC Line Current
Figure 21. Typical Line Waveforms without PFC
Increasingly, government regulations and utility
requirements necessitate control over the line current
harmonic content. To meet this need, power factor
correction is implemented with either a passive or active
circuit. Passive circuits usually contain a combination of
large capacitors, inductors, and rectifiers that operate at the
ac line frequency. Active circuits incorporate some form of
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9
NCP1606
a high frequency switching converter which regulates the
input current to stay in phase with the input voltage. These
circuits operate at a higher frequency and so they are
smaller, lighter in weight, and more efficient than a passive
circuit. With proper control of an active PFC stage, almost
any complex load can be made to appear in phase with the
PFC Preconverter
Rectifiers
AC Line
ac line, thus significantly reducing the harmonic current
content. Because of these advantages, active PFC circuits
have become the most popular way to meet harmonic
content requirements. Generally, they consist of inserting
a PFC pre−regulator between the rectifier bridge and the
bulk capacitor (Figure 22).
+
High
Frequency
Bypass
Capacitor
Converter
Bulk
Storage
Capacitor
+
NCP1606
Load
Figure 22. Active PFC Pre−Converter with the NCP1606
The boost (or step up) converter is the most popular
topology for active power factor correction. With the
proper control, it produces a constant voltage while
drawing a sinusoidal current from the line. For medium
power ( Iovp
2.5 V
Measure
ICONTROL
+
ROUT2
Fault
VDD
CCOMP
Enable
VEAL Static OVP
Clamp Static OVP is triggered
when clamp is activated.
VCONTROL
Control
ICONTROL
VEAH
Clamp
Figure 34. OVP and UVP Circuit Blocks
• Therefore, the error amplifier sinks:
When the output voltage is in steady state, ROUT1 and
ROUT2 regulate the FB voltage to 2.5 V. Also, during this
equilibrium state, no current flows through the
compensation capacitor (“CCOMP” of Figure 1). Therefore:
• The ROUT1 current is:
(V
)nom * 2.5 V
IR
+ OUT
R OUT1
OUT1
(eq. 11)
(V
) nom ) DV OUT−2.5 V 2.5 V
IR
−I R
+ OUT
−
R OUT1
R OUT2
OUT1
OUT2
The combination of Equations 2 and 11 leads to a very
simple expression of the current sunk by the error
amplifier:
(eq. 6)
where (VOUT)nom is the nominal output voltage.
• The ROUT2 current is:
IR
OUT2
+
2.5 V
R OUT2
ICONTROL + I R
OUT1
+I R
OUT2
å
(V OUT)nom * 2.5 V
2.5 V
+
R OUT1
ROUT2
(eq. 8)
OUT2
+
2.5 V
R OUT2
ROUT1 +
+
DV OUT
R OUT1
(eq. 12)
(V OUT)OVP * (VOUT) nom
I OVP
For instance if implementing the NCP1606B, and
420 V is the maximum output level and 400 V is the
nominal output level, then
(eq. 9)
ROUT1 + 420 * 400 + 1.9 MW
10.4 mA
(eq. 10)
OUT1
+
By simply adjusting ROUT1, the OVP limit can be easily
set. Therefore, one can compute the ROUT1 and ROUT2
resistances using the following procedure:
1. Select ROUT1 to set the desired overvoltage level:
• The ROUT1 current is:
IR
OUT2
(VOUT) OVP + (VOUT) nom ) (R OUT1 @ I OVP)
Under stable conditions, these equations are true.
Conversely when VOUT is not at its nominal level, the
output of the error amplifier sinks or sources the current
necessary to maintain 2.5 V on pin 1. In particular, in the
case of an overvoltage condition:
• The error amplifier maintains 2.5 V on pin 1, and the
ROUT2 current remains:
IR
* IR
Hence, the current absorbed by pin 2 (ICONTROL) is
proportional to the output voltage excess. The circuit
senses this current and disables the drive (pin 7) when
ICONTROL exceeds IOVP (typically 40 mA in NCP1606A,
10.4 mA in NCP1606B). This gives the OVP threshold as:
(eq. 7)
• And since no current flows through CCOMP,
IR
OUT1
2. Select ROUT2 to adjust the regulation level:
V OUT−2.5 V
(V
)nom ) DVOUT−2.5 V
+ OUT
R OUT1
R OUT1
ROUT2 +
where DVOUT is the output voltage excess.
www.onsemi.com
16
2.5 V @ ROUT1
V OUT(nom) * 2.5 V
NCP1606
Furthermore, the NCP1606 incorporates a novel startup
sequence which ensures that undervoltage conditions are
always detected at startup. It accomplishes this by waiting
approximately 180 ms after VCC reaches VCC(on) before
enabling the error amplifier (Figure 36). During this wait
time, it looks to see if the feedback (FB) voltage is greater
than the UVP threshold. If not, then the controller enters a
UVP fault and leaves the error amplifier disabled.
However, if the FB pin voltage increases and exceeds the
UVP level, then the controller will start the application up
normally.
For the above example, this leads to:
ROUT2 +
2.5 V
@ 1.9 MW + 12.0 kW.
400 V * 2.5 V
STATIC OVERVOLTAGE PROTECTION
If the OVP condition lasts for a long time, it may happen
that the error amplifier output reaches its minimum level
(i.e. Control = VEAL). It would then not be able to sink any
current and maintain the OVP fault. Therefore, to avoid any
discontinuity in the OVP disabling effect, the circuit
incorporates a comparator which detects when the lower
level of the error amplifier is reached. This event, called
“static OVP”, disables the output drives. Once the OVP
event is over, and the output voltage has dropped to normal,
then Control rises above the lower limit and the driver is
re−enabled (Figure 35).
VCC(on)
VCC
VCC(off)
VOUT(nom)
Vout(nom)
Vout
VOUT
FB
2.5 V
VUVP
Drive
VEAH
VEAH
Vcontrol
VEAL
UVP Fault is “Removed”
Control
VEAL
UVP Wait
UVP
IovpH
Icontrol
IovpL
UVP Wait
Figure 36. The NCP1606’s Startup Sequence with
and without a UVP Fault
Dynamic OVP
The voltage on the output which exits a UVP fault is
given by:
Static OVP
VOUT
Figure 35. OVP Timing Diagram
(UVP)
+
R OUT1 ) R OUT2
@ 300 mV
R OUT2
(eq. 13)
If ROUT1 = 1.9 MW and ROUT2 = 12.0 kW, then the VOUT
UVP threshold is 48 V. This corresponds to an input voltage
of approximately 34 Vac.
NCP1606 Undervoltage Protection (UVP)
When the PFC stage is plugged in, the output voltage is
forced to roughly equate the peak line voltage. The
NCP1606 detects an undervoltage fault when this output
voltage is unusually low, such that the feedback voltage is
below VUVP (300 mV typ). In an UVP fault, the drive
output and error amplifier (EA) are disabled. The latter is
done so that the EA does not source a current which would
increase the FB voltage and prevent the UVP event from
being accurately detected. The UVP feature helps to
protect the application if something is wrong with the
power path to the bulk capacitor (i.e. the capacitor cannot
charge up) or if the controller cannot sense the bulk voltage
(i.e. the feedback loop is open).
Overcurrent Protection (OCP)
A dedicated pin on the NCP1606 senses the peak current
and limits the driver on time if this current exceeds
VCS(limit). This level is 1.7 V (typ) on the NCP1606A and
0.5 V (typ) on the NCP1606B. Therefore, the maximum
peak current can be adjusted by changing RSENSE according
to:
Ipeak +
V CS(limit)
RSENSE
(eq. 14)
An internal LEB filter (Figure 37) reduces the likelihood
of switching noise falsely triggering the OCP limit. This
filter blanks out the first 250 ns (typical) of the current
sense signal. If additional filtering is necessary, a small RC
filter can be added between RSENSE and the CS pin.
www.onsemi.com
17
NCP1606
SHUTDOWN MODE
DRIVE
CS
+
RSENSE
OCP
+
−
LEB
The NCP1606 allows for two methods to place the
controller into a standby mode of operation. The FB pin can
be pulled below the UVP level (0.3 V typical) or the ZCD
pin can be pulled below the VSDL level (typically 200 mV).
If the FB pin is used for shutdown (Figure 38(a)), care must
be taken to ensure that no significant leakage current exists
on the shutdown circuitry. This could impact the output
voltage regulation. If the ZCD pin is used for shutdown
(Figure 38(b)), then any parasitic capacitance created by
the shutdown circuitry will add to the delay in detecting the
zero inductor current event.
VCS(limit)
optional
Figure 37. OCP Circuitry with Optional External RC
Filter
LBOOST
VOUT
ROUT1
NCP1606
NCP1606
Ccomp
Shutdown
ROUT2
1 FB
VCC 8
1 FB
2 Ctrl
DRV 7
2 Ctrl
DRV 7
3 Ct
GND 6
3 Ct
GND 6
4 Cs
ZCD 5
4 Cs
ZCD 5
VCC 8
RZCD
Shutdown
Figure 38(a)
Figure 38(b)
Figure 38. Shutting Down the PFC Stage by Pulling FB to GND (A) or Pulling ZCD to GND (B)
To activate the shutdown feature on ZCD, the internal
clamp must first be overcome. This clamp will draw a
maximum of ICL(NEG) (5.0 mA maximum) before releasing
and allowing the ZCD pin voltage to drop low enough to
shutdown the part (Figure 39). After shutdown, the
comparator includes approximately 90 mV of hysteresis to
ensure noise free operation. A small current source (70 mA
typ) is also activated to pull the unit out of the shutdown
condition when the external pull down is released.
5 mA
IZCD
~70 mA
Shutdown
VSDL VSDH
VCL(NEG)
~1 V
Figure 39. Shutdown Comparator and Current Draw to Overcome Negative Clamp
www.onsemi.com
18
NCP1606
BOOST DESIGN EQUATIONS Components are identified in Figure 1
RMS Input Current
POUT
h @ Vac(rms)
h (the efficiency of only the Boost
PFC stage) is generally in the range
of 90 − 95%
2 @ Ǹ2 @ P OUT
h @ Vac LL
Ipk(max) occurs at the lowest line voltage.
Iac(rms) +
Maximum Inductor Peak
Current
Ipk(max) +
Inductor Value
2 @ Vac 2 @
Lv
tON(max) +
Off Time
tOFF +
fSW +
Pin 3 Capacitor
Boost Turns to ZCD Turns
Ratio
Resistor from ZCD winding to the ZCD pin (pin 5)
Boost Output Voltage
Maximum VOUT voltage
prior to OVP activation and
the necessary ROUT1 and
ROUT2.
Minimum output voltage
necessary to exit undervoltage protection (UVP)
Bulk Cap Ripple
Inductor RMS Current
Boost Diode RMS Current
MOSFET RMS Current
V
OUT
Ǹ2
* Vac
Ǔ
fSW(min) is the minimum desired
switching frequency. The maximum L
must be calculated at low line and
high line.
VOUT @ Vac @ I pk(max) @ fSW(min)
Maximum On Time
Frequency
ǒ
Vac (rms) 2 @ h
2 @ L @ POUT
Ct w
The maximum on time occurs at the
lowest line voltage and maximum
output power.
2 @ L @ P OUT
h @ Vac LL 2
t ON
V
OUT
*1
Vac (rms)@Ťsin(q)Ť@Ǹ2
@
ǒ
1*
Vac (rms) @ |sin q| @ Ǹ2
V OUT
ICHARGE and VCTMAX are given in
the NCP1606 specification table.
2 @ P OUT @ L @ I CHARGE
h @ Vac RMS 2 @ V CTMAX
NB : N ZCD v
RZCD w
The turns ratio must be low enough
so as to trigger the ZCD comparators
at high line.
V OUT * Vac HL @ Ǹ2
V ZCDH
RZCD must be large enough so that
the shutdown comparator is not inadvertently activated.
Vac HL @ Ǹ2
I CL(NEG) @ (N B : N ZCD)
VOUT(nom) + 2.5 V @
ROUT1 ) ROUT2
ROUT2
IOVP is given in the NCP1606 specification table. IOVP is lower for the
NCP1606B, then for the NCP1606A
version.
VOUT(max) + V OUT(nom) ) R OUT1 @ I OVP
ROUT1 +
V OUT(max) * V OUT(nom)
IOVP
2.5 V @ ROUT1
ROUT2 +
V OUT(nom) * 2.5 V
VOUT
(UVP)
+
POUT
C bulk @ 2 @ p @ fline @ VOUT
IcoilRMS +
Id MAX(rms) + 4 @
3
VUVP is given in the NCP1606 specification table.
R OUT1 ) R OUT2
@ V UVP
R OUT2
Vripple (pk−pk) +
2 @ P OUT
Ǹ3 @ Vac @ h
LL
Ǹ2 @pǸ2 @
IM(rms) + 2 @ Pin @
Ǹ3 Vac
Ǹ
Ǔ
The off time is greatest at the peak of
the AC line voltage and approaches
zero at the AC line zero crossings.
Theta (q) represents the angle of the
AC line voltage.
P OUT
h @ ǸVac LL @ VOUT
1*
ǒ
8 @ Ǹ2 @ Vac
3 p @ V OUT
www.onsemi.com
19
Ǔ
Use fline = 47 Hz for worst case at
universal lines. The ripple must not
exceed the OVP level for VOUT.
NCP1606
BOOST DESIGN EQUATIONS Components are identified in Figure 1
MOSFET Sense Resistor
RSENSE +
VCS(limit) is given in the NCP1606
specification table. The NCP1606B
has a lower VCS(limit) level.
V CS(limit)
I pk
PRSENSE + I M(rms) 2 @ RSENSE
Bulk Capacitor RMS
Current
IC(rms) +
Type 1 CCOMP
Ǹ
32 @ Ǹ2 @ P OUT 2
* (ILOAD(rms)) 2
9 @ p @ Vac LL @ VOUT @ h2
CCOMP +
10 Gń20
4 @ p @ f line @ ROUT1
G is the desired attenuation in decibels (dB). Typically it is 60 dB.
ORDERING INFORMATION
Vcs(limit) (typ) (Note 5)
IOVP (typ) (Note 5)
Package
Shipping†
NCP1606ADR2G
1.7 V
40 mA
SOIC−8
2500 / Tape & Reel
NCP1606BDR2G
0.5 V
10 mA
SOIC−8
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
5. See the electrical specifications section for complete information on VCS and IOVP.
www.onsemi.com
20
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
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