NCP1652ADR2G

NCP1652, NCP1652A Controller, PFC, High Efficiency, Single Stage The NCP1652 is a highly integrated controller for implementing power factor correction (PFC) and isolated step down ac−dc power conversion in a single stage, resulting in a lower cost and reduced part count solution. This controller is ideal for notebook adapters, battery chargers and other off−line applications with power requirements between 75 W and 150 W. The single stage is based on the flyback converter and it is designed to operate in continuous conduction (CCM) or discontinuous conduction (DCM) modes. The NCP1652 increases the system efficiency by incorporating a secondary driver with adjustable nonoverlap delay for controlling a synchronous rectifier switch in the secondary side, an active clamp switch in the primary or both. In addition, the controller features a proprietary Soft−Skip™ to reduce acoustic noise at light loads. Other features found in the NCP1652 include a high voltage startup circuit, voltage feedforward, brown out detector, internal overload timer, latch input and a high accuracy multiplier. http://onsemi.com MARKING DIAGRAMS 20 SO−20 WB DW SUFFIX CASE 751D NCP1652 AWLYYWWG 1 NCP1652G AWLYWW Features • Dual Control Outputs with Adjustable Non Overlap Delay for • • • • • • • • • • • • Driving a Synchronous Rectifier Switch, an Active Clamp Switch or Both Voltage Feedforward Improves Loop Response Frequency Jittering Reduces EMI Signature Proprietary Soft−Skip™ at Light Loads Reduces Acoustic Noise Brown Out Detector Internal 150 ms Fault Timer Independent Latch−Off Input Facilitates Implementation of Overvoltage and Overtemperature Fault Detectors Single Stage PFC and Isolated Step Down Converter Continuous or Discontinuous Conduction Mode Operation Average Current Mode Control (ACMC), Fixed Frequency Operation High Accuracy Multiplier Reduces Input Line Harmonics Adjustable Operating Frequency from 20 kHz to 250 kHz These are Pb−Free Devices SOIC−16 D SUFFIX CASE 751B A WL YY WW G NCP1652AG AWLYWW = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 32 of this data sheet. Typical Applications • • • • Notebook Adapter High Current Battery Chargers Front Ends for Distributed Power Systems High Power Solid State Lighting © Semiconductor Components Industries, LLC, 2010 April, 2010 − Rev. 3 1 Publication Order Number: NCP1652/D NCP1652, NCP1652A SO−20 WB CT 1 SOIC−16 Ramp Comp 2 19 NC AC IN 3 18 NC 17 GND VFF 5 16 Out B CM 6 15 Out A NC 7 14 VCC NC 8 13 Ispos Latch−Off 10 16 Startup Ramp Comp 2 FB 4 AC COMP 9 CT 1 20 Startup 15 GND AC IN 3 14 OUT B FB 4 13 OUT A VFF 5 12 VCC CM 6 11 Ispos AC COMP 7 10 Iavg Latch−Off 8 9 Rdelay (Top View) 12 Iavg 11 Rdelay Figure 1. Pin Connections http://onsemi.com 2 NCP1652, NCP1652A FB overload comparator Jitter FB CT + Jitter Adj. + − Overload Timer tOVLD Enable S Q R VOVLD Clock Oscillator DC Max Sawtooth DC Max VFF + V Brown−Out FF Comparator − + VBO Ramp. Comp. OVLD Startup Enable x2 counter Reset Out Dual HV start−up current source BO Ramp Comp Adj. VCC(off) HV current Reset Ramp Comp + − + VCC Management Start VDD Reset V CCOK AC In skip comparator VDD VSSKIP(sync) VDD GND Output Driver Clock Soft−skip Ramp R FB FB skip Comparator + − + Inst. current B VSSKIP AC IN + Q R − V−to−I FB S + Ramp Comp OUTB Delay Transient Load Detect Comparator + − VSSKIP(TLD) OUTA Output Driver PWM Skip Comparator 21.33kW V−to−I Reference Generator + gm − V−to−I + inverter + − AC error Amplifier VFF 21.33kW VCC PWM comparator + BO OVLD 4V CM Latch Inst. current A Blanking tLEB gm AC COMP Blanking Inst. current B VDD VCCOK tLEB − + FB VFF Delay Adj. DC Max Delay tSSKIP Start Terminate Ispos Current sense amplifier OVP Comparator + Ilatch(clamp) Iavg + − Vlatch(high) blanking tLatch(delay) Latch−Off OTP Comparator Ilatch(shdn) Vlatch(clamp) + S − + Q R Vlatch(low) Reset Figure 2. Detailed Block Diagram http://onsemi.com 3 Latch Delay Rdelay NCP1652, NCP1652A PIN FUNCTION DESCRIPTION Pin 16 Pin 20 Pin Symbol Description 1 1 CT An external timing capacitor (CT) sets the oscillator frequency. A sawtooth between 0.2 V and 4 V sets the oscillator frequency and the gain of the multiplier. 2 2 RAMP COMP A resistor (RRC) between this pin and ground adjust the amount of ramp compensation that is added to the current signal. Ramp compensation is required to prevent subharmonic oscillations. This pin should not be left open. 3 3 AC IN The scaled version of the full wave rectified input ac wave is connected to this pin by means of a resistive voltage divider. The line voltage information is used by the multiplier. 4 4 FB An error signal from an external error amplifier circuit is fed to this pin via an optocoupler or other isolation circuit. The FB voltage is a proportional of the load of the converter. If the voltage on the FB pin drops below VSSKIP the controller enters Soft−Skip™ to reduce acoustic noise. 5 5 VFF Feedforward input. A scaled version of the filtered rectified line voltage is applied by means of a resistive divider and an averaging capacitor. The information is used by the Reference Generator to regulate the controller. 6 6 CM Multiplier output. A capacitor is connected between this pin and ground to filter the modulated output of the multiplier. 7 NC 8 NC 7 9 AC COMP Sets the pole for the ac reference amplifier. The reference amplifier compares the low frequency component of the input current to the ac reference signal. The response must be slow enough to filter out most of the high frequency content of the current signal that is injected from the current sense amplifier, but fast enough to cause minimal distortion to the line frequency information. The pin should not be left open. 8 10 Latch Latch−Off input. Pulling this pin below 1.0 V (typical) or pulling it above 7.0 V (typical) latches the controller. This input can be used to implement an overvoltage detector, an overtemperature detector or both. Refer to Figure 69 for a typical implementation. 9 11 Rdelay A resistor between this pin and ground sets the non−overlap time delay between OUTA and OUTB. The delay is adjusted to prevent cross conduction between the primary MOSFET and synchronous rectification MOSFET or optimize the resonant transition in an active clamp stage. 10 12 IAVG An external resistor and capacitor connected from this terminal to ground, to set and stabilizes the gain of the current sense amplifier output that drives the ac error amplifier. 11 13 ISpos Positive current sense input. Connects to the positive side of the current sense resistor. 12 14 VCC Positive input supply. This pin connects to an external capacitor for energy storage. An internal current source supplies current from the STARTUP pin VCC. Once the voltage on VCC reaches approximately 15.3 V, the current source turns off and the outputs are enabled. The drivers are disabled once VCC reaches approximately 10.3 V. If VCC drops below 0.85 V (typical), the startup current is reduced to less than 500 mA. 13 15 OUTA Drive output for the main flyback power MOSFET or IGBT. OUTA has a source resistance of 13 W (typical) and a sink resistance of 8 W (typical). 14 16 OUTB Secondary output of the PWM Controller. It can be used to drive synchronous rectifier, and active clamp switch, or both. OUTB has source and sink resistances of 22 W (typical) and 11 (typical), respectively. 15 17 GND Ground reference for the circuit. 18 NC 19 NC 20 HV 16 Connect the rectified input line voltage directly to this pin to enable the internal startup regulator. A constant current source supplies current from this pin to the capacitor connected to the VCC pin, eliminating the need for a startup resistor. The charge current is typically 5.5 mA. Maximum input voltage is 500 V. http://onsemi.com 4 NCP1652, NCP1652A MAXIMUM RATINGS (Notes 1 and 2) Rating Symbol Value Unit Start_up Input Voltage Start_up Input Current VHV IHV −0.3 to 500 $100 V mA Power Supply Input Voltage Power Supply Input Current VCC ICC −0.3 to 20 $100 V mA Latch Input Voltage Latch Input Current VLatch ILatch −0.3 to 10 $100 V mA OUTA Pin Voltage OUTA Pin Current VoutA IoutA −0.3 to 20 $1.0 V A OUTB Pin Voltage OUTB Pin Current VoutB IoutB −0.3 to 20 $600 V mA −0.3 to 6.5 $100 V mA All Other Pins Voltage All Other Pins Current Thermal Resistance, Junction−to−Air 0.1 in” Copper 0.5 in” Copper qJA 130 110 °C/W Thermal Resistance, Junction−to−Lead RΘJL 50 °C/W Maximum Power Dissipation @ TA = 25°C PMAX 0.77 W TJ −40 to 125 °C TSTG −55 to 150 °C Operating Temperature Range Storage Temperature Range Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: 16 pin package: Pin 1−15: Human Body Model 2000 V per JEDEC standard JESD22, Method A114. Machine Model 200 V per JEDEC standard JESD22, Method A115. Pin 16 is the high voltage startup of the device and is rated to the maximum rating of the part, 500 V. 20 pin package: Pin 1−19: Human Body Model 2000 V per JEDEC standard JESD22, Method A114. Machine Model 200 V per JEDEC standard JESD22, Method A115. Pin 20 is the high voltage startup of the device and it is rated to the maximum rating of the part, or 500 V. 2. This device contains Latchup protection and exceeds ±100 mA per JEDEC Standard JESD78. http://onsemi.com 5 NCP1652, NCP1652A VCC EMI Filter Latch + NTC + + _ FB 1 CT HV Ramp Comp FB GND AC IN OUTB FB OUTA VCC VFF NCP1652 CM Ispos AC COMP Latch VCC Iavg 10 11 LATCH Rdelay Figure 3. Typical Application Schematic http://onsemi.com 6 NCP1652, NCP1652A ELECTRICAL CHARACTERISTICS (VCC = 15 V, VAC IN = 3.8 V, VFB = 2.0 V, VFF = 2.4 V, VLatch = open, VISPOS = −100 mV, COUTA = 1 nF, CT = 470 pF, CIAVG = 0.27 nF, CLatch = 0.1 nF, CM = 10 nF, RIAVG = 76.8 kW, Rdelay = 49.9 kW, COUTB = 330 pF, RRC = 43 kW, For typical Value TJ = 25°C, for min/max values TJ = −40°C to 125°C, unless otherwise noted) Symbol Min Typ Max Unit fosc 90 100 110 kHz Frequency Modulation in Percentage of fOSC – 6.8 – % Frequency Modulation Period – 6.8 – ms Parameter Test Condition OSCILLATOR Frequency Ramp Peak Voltage VCT(peak) – 4.0 – V Ramp Valley Voltage VCT(valley) – 0.10 – V D 94 − – % VRCOMP(peak) – 4 – V 40 – mV Maximum Duty Ratio Rdelay = open Ramp Compensation Peak Voltage AC ERROR AMPLIFIER Input Offset Voltage (Note 3) Ramp IAVG, VFB = 0 V Error Amplifier Transconductance ACVIO gm – 100 – mS Source Current VAC COMP = 2.0 V, VAC IN = 2.0 V, VFF = 1.0 V IEA(source) 25 70 – mA Sink Current VAC COMP = 2.0 V, VA C_IN = 2.0 V, VFF = 5.0 V IEA(sink) −25 −70 – mA VISPOS = 0 V CAIbias 40 53 80 mA VAC COMP = 5.0 V, VISpos = 0 V CAVIO −20 0 20 mV force OUTA high, VAC COMP = 3.0 V, ramp VISPOS, VRamp_Comp = open VILIM 0.695 0.74 0.77 V tLEB – 200 – ns – 1.5 – MHz PWMk 4.0 5.3 6.0 V/V ISVk 15.4 18.5 23 V/V k – 0.55 – V CURRENT AMPLIFIER Input Bias Current Input Offset Voltage Current Limit Threshold Leading Edge Blanking Duration Bandwidth PWM Output Voltage Gain Current Limit Voltage Gain (See Current Sense Section) PWMk + 4 (V ILIM * C AVIO) ISVK + V (AVG) VI SPOS REFERENCE GENERATOR Reference Generator Gain k+ V AC_REF @ V FF 2 V FB @ V AC_IN Reference Generator output voltage (low input ac line and full load) VAC IN = 1.2 V, VFF = 0.765 V, VFB = 4 V RGout1 3.61 4.36 4.94 Vpk Reference Generator output voltage (high input ac line and full load) VAC IN = 3.75 V, VFF = 2.39 V, VFB = 4.0 V RGout2 1.16 1.35 1.61 Vpk Reference Generator output Voltage (low input as line and minimum load) VAC IN = 1.2 V, VFF = 0.765 V, VFB = 2.0 V RGout3 1.85 2.18 2.58 Vpk Reference Generator output voltage (high input ac line and minimum load) VAC IN = 3.75 V, VFF = 2.39 V, VFB = 2.0 V RGout4 0.55 0.65 0.78 Vpk RGoffset −100 – 100 mV Reference Generator output offset voltage 3. Guaranteed by Design http://onsemi.com 7 NCP1652, NCP1652A ELECTRICAL CHARACTERISTICS (VCC = 15 V, VAC IN = 3.8 V, VFB = 2.0 V, VFF = 2.4 V, VLatch = open, VISPOS = −100 mV, COUTA = 1 nF, CT = 470 pF, CIAVG = 0.27 nF, CLatch = 0.1 nF, CM = 10 nF, RIAVG = 76.8 kW, Rdelay = 49.9 kW, COUTB = 330 pF, RRC = 43 kW, For typical Value TJ = 25°C, for min/max values TJ = −40°C to 125°C, unless otherwise noted) Parameter Test Condition Symbol Min Typ Max Unit IAC IN(IB) – 0.01 – mA VOUTA = 1 V IOUTA = 100 mA RSNK1 RSRC1 – – 8 10.8 18 24 VOUTB = 1 V IOUTB = 100 mA RSNK2 RSRC2 – – 10 21 22 44 Rise Time (10% to 90%) OUTA OUTB tr1 tr2 – – 40 25 – – Fall Time (90% to 10%) OUTA OUTB tf1 tf2 – – 20 10 – – VOUTA(low) VOUTB(low) – – 1.0 1.0 100 100 tdelay(range) 0.08 – 2.8 AC INPUT Input Bias Current Into Reference Multiplier & Current Compensation Amplifier DRIVE OUTPUTS A and B Drive Resistance (Thermally Limited) OUTA Sink OUTA Source OUTB Sink OUTB Source DRV Low Voltage OUTA OUTB IOUTA = 100 mA IOUTB = 100 mA Non−Overlap Adjustable Delay Range (Note 3) Non−Overlap Adjustable Delay Leading Trailing Measured at 50% of VOUT, COUTA = COUTB = 100 pF OUTA Rising to OUTB falling OUTB Rising to OUTA falling W ns ns mV ms ns tdelay(lead) tdelay(trail) 250 250 450 420 550 550 OUTA Rising to OUTB Falling or OUTB Rising to OUTA Falling tdelay(match) – – 55 % Skip Synchronization to ac Line Voltage Threshold VACIN Increasing, VFB = 1.5 V VSSKIP(SYNC) 210 267 325 mV Skip Synchronization to ac Line Voltage Threshold Hysteresis VACIN Decreasing VSSKIP (SYNCHYS) – 40 – mV Skip Ramp Period (Note 3) tSSKIP − 2.5 – ms Skip Voltage Threshold NCP1652 NCP1652A VSSKIP 1.04 0.36 1.24 0.41 1.56 0.46 Skip Voltage Hysteresis VSSKIP(HYS) 45 90 140 mV VSSKIP(TLD) = VSSKIP +0.55 V VSSKIP(TLD) − 1.75 − V VFB= 0.5 V IFB 600 750 920 mA RFB – 6.7 – kW VFB(open) 5.3 5.7 6.3 V VCC Increasing VCC Decreasing VCC Decreasing VCC(on) VCC(off) VCC(reset) 14.3 9.3 – 15.4 10.2 7.0 16.3 11.3 – VHV = 40 V, Iinhibit = 500 mA Vinhibit − 0.83 1.15 Non−Overlap Adjustable Delay Matching Soft−Skip] Skip Transient Load Detect Threshold (Note 3) V FEEDBACK INPUT Pull−Up Current Source Pull−Up Resistor Open Circuit Voltage STARTUP AND SUPPLY CIRCUITS Supply Voltage Startup Threshold Minimum Operating Voltage Logic Reset Voltage Inhibit Threshold Voltage 3. Guaranteed by Design http://onsemi.com 8 V V NCP1652, NCP1652A ELECTRICAL CHARACTERISTICS (VCC = 15 V, VAC IN = 3.8 V, VFB = 2.0 V, VFF = 2.4 V, VLatch = open, VISPOS = −100 mV, COUTA = 1 nF, CT = 470 pF, CIAVG = 0.27 nF, CLatch = 0.1 nF, CM = 10 nF, RIAVG = 76.8 kW, Rdelay = 49.9 kW, COUTB = 330 pF, RRC = 43 kW, For typical Value TJ = 25°C, for min/max values TJ = −40°C to 125°C, unless otherwise noted) Parameter Test Condition Symbol Min Typ Max Unit VHV = 40 V, VCC = 0.8 * Vinhibit Iinhibit 40 - 500 mA Istart = 0.5 mA, VCC = VCC(on) – 0.5 V Vstart(min) – – 40 V VCC = VCC(on) – 0.5 V, VFB = Open Istart 3.0 5.62 8.0 mA VHV = 400 V, TJ = 25°C TJ = −40°C to 125°C IHV(off) – – 17 15 40 80 VFB = Open fOSC [ 100 kHz ICC1 ICC2 – – 0.72 6.25 1.2 7.2 Overload Timer tOVLD 120 162 360 ms Overload Detect Threshold VOVLD 4.7 4.9 5.2 V STARTUP AND SUPPLY CIRCUITS Inhibit Bias Current Minimum Startup Voltage Startup Current Off−State Leakage Current Supply Current Device Disabled (Overload) Device Switching mA mA FAULT PROTECTION Brown−Out Detect Threshold (entering fault mode) VFF Decreasing, VFB = 2.5 V, VAC IN = 2.0 V VBO(low) 0.41 0.45 0.49 V Brown−Out Exit Threshold (exiting fault mode) VFF Increasing, VFB = 2.5 V, VAC IN = 2.0 V VBO(high) 0.57 0.63 0.69 V VBO(HYS) − 174 − mV Vlatch(low) 0.9 0.98 1.1 V Brown−Out Hysteresis LATCH INPUT Pull−Down Latch Voltage Threshold Pull−Up Latch Voltage Threshold VLatch Decreasing VLatch Increasing Vlatch(high) 5.6 7.0 8.4 V VLatch = Vlatch(high) tlatch(delay) 30 56 90 ms Latch Clamp Current (Going Out) VLatch = 1.5 V Ilatch(clamp) 42 51 58 mA Latch Clamp Voltage (ILatch Going In) ILatch = 50 mA Vlatch(clamp) 2.5 3.27 4.5 V VLatch Increasing Ilatch(shdn) − 95 − mA Latch Propagation Delay Latch−Off Current Shutdown (Going In) 3. Guaranteed by Design http://onsemi.com 9 NCP1652, NCP1652A 8.0 OSCILLATOR FREQUENCY MODULATION (%) fOSC, OSCILLATOR FREQUENCY (kHz) 110 105 100 95 90 −50 −25 0 25 50 75 100 125 7.5 7.0 6.5 6.0 −50 150 −25 Figure 4. Oscillator Frequency (fOSC) vs. Junction Temperature VCT(peak), OSCILLATOR RAMP PEAK VOLTAGE (V) 7.0 6.5 −25 0 25 50 75 100 125 150 75 100 125 150 4.05 4.0 3.95 3.9 3.85 3.8 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 6. Oscillator Frequency Modulation Period vs. Junction Temperature Figure 7. Ramp Peak Voltage vs. Junction Temperature 100 D, MAXIMUM DUTY RATIO (%) 50 4.1 7.5 98 96 94 92 90 −50 25 Figure 5. Oscillator Frequency Modulation in Percentage of fOSC vs. Junction Temperature 8.0 6.0 −50 0 TJ, JUNCTION TEMPERATURE (°C) −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 VCOMP(peak), RAMP COMP PEAK VOLTAGE (V) OSCILLATOR FREQUENCY MODULATION PERIOD (ms) TJ, JUNCTION TEMPERATURE (°C) 150 4.1 4.05 4.0 3.95 3.9 3.85 3.8 −50 Figure 8. Maximum Duty Ratio vs. Junction Temperature −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) Figure 9. Ramp Compensation Peak Voltage vs. Junction Temperature http://onsemi.com 10 150 NCP1652, NCP1652A IEA(SINK), ERROR AMPLIFIER SINK CURRENT (mA) IEA(SOURCE), ERROR AMPLIFIER SOURCE CURRENT (mA) 90 85 80 75 70 65 60 55 50 −50 −25 0 25 50 75 100 125 90 85 80 75 70 65 60 55 50 −50 150 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 10. Error Amplifier Source Current vs. Junction Temperature Figure 11. Error Amplifier Sink Current vs. Junction Temperature 150 CAVBIAS, CURRENT AMPLIFIER INPUT BIAS CURRENT (mA) 60.0 57.5 55.0 52.5 50.0 47.5 45.0 42.5 40.0 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) 770 6.0 PWMk, PWM VOLTAGE GAIN (V/V) VILIM, CURRENT LIMIT THRESHOLD (mV) Figure 12. Current Amplifier Input Bias Current vs. Junction Temperature 760 750 740 730 720 710 700 −50 −25 0 25 50 75 100 125 150 5.8 5.6 5.4 5.2 5.0 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 13. Current Limit Threshold vs. Junction Temperature Figure 14. PWM Output Voltage Gain vs. Junction Temperature http://onsemi.com 11 150 NCP1652, NCP1652A 5.25 20 19 18 17 −25 0 25 50 75 100 125 150 RGout1 4.75 4.25 3.75 3.25 2.75 RGout3 2.25 1.75 RGout2 1.25 RGout4 0.75 0.25 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 15. Oscillator CS Limit Voltage Gain vs. Junction Temperature Figure 16. Oscillator Reference Generator Output Voltage vs. Junction Temperature 14 16 12 14 RSRC1, OUTA SOURCE RESISTANCE (W) RSNK1, OUTA SINK DRIVE RESISTANCE (W) 16 −50 10 8.0 6.0 4.0 −50 −25 0 25 50 75 100 125 150 150 12 10 8.0 6.0 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 17. OUTA Sink Resistance vs. Junction Temperature Figure 18. OUTA Source Drive Resistance vs. Junction Temperature 16 RSNK2, OUTB SINK DRIVE RESISTANCE (W) RGout, REFERENCE GENERATOR OUTPUT VOLTAGE (V) 21 32 VCC = 15 V VCC = 15 V CI = 100 pF 30 14 RSRC2, OUTB SOURCE RESISTANCE (W) ISVk, CURRENT LIMIT VOLTAGE GAIN (V/V) 22 12 10 8.0 28 26 24 22 20 18 16 6.0 −50 −25 0 25 50 75 100 125 150 14 −50 TJ, JUNCTION TEMPERATURE (°C) −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 19. OUTB Sink Resistance vs. Junction Temperature Figure 20. OUTB Source Drive Resistance vs. Junction Temperature http://onsemi.com 12 NCP1652, NCP1652A 160 VOUTB(LOW), OUTB LOW VOLTAGE (mV) VOUTA(low), OUTA LOW VOLTAGE (mV) 130 110 90 70 50 30 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 140 120 100 80 60 −50 Figure 21. OUTA Low Voltage vs. Junction Temperature tdelay, NON−OVERLAP ADJUSTABLE DELAY MATCHING (%) tdelay, NON−OVERLAP ADJUSTABLE DELAY (ns) 500 OUTA Rising to OUTB Falling 450 OUTB Rising to OUTA Falling 400 350 −25 0 25 50 75 100 125 150 7 5 3 1 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 23. Non−Overlap Adjustable Delay vs. Junction Temperature Figure 24. Non−Overlap Adjustable Delay Matching vs. Junction Temperature 300 150 1.25 VSSKIP, SKIP VOLTAGE THRESHOLD (V) VSSKIP(SYNC), SKIP SYNC TO AC LINE VOLTAGE THRESHOLD (mV) 150 9 550 280 1.24 260 1.23 240 1.22 220 200 −50 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) Figure 22. OUTB Low Voltage vs. Junction Temperature 600 300 −50 −25 1.21 −25 0 25 50 75 100 125 150 1.20 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 25. Skip Synchronization to ac Line Voltage Threshold vs. Junction Temperature Figure 26. Skip Voltage Threshold vs. Junction Temperature http://onsemi.com 13 780 100 IFB, FEEDBACK PULL−UP CURRENT SOURCE (mA) VSSKIP, SKIP VOLTAGE HYSTERESIS (mV) NCP1652, NCP1652A 95 90 85 80 −50 −25 0 25 50 75 100 125 150 730 705 680 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 27. Skip Voltage Hysteresis vs. Junction Temperature Figure 28. Feedback Pull−Up Current Source vs. Junction Temperature 15.75 VCC(on), STARTUP THRESHOLD (V) 6.2 6.0 5.8 5.6 5.4 5.2 −50 −25 0 25 50 75 100 125 150 15.55 15.35 15.15 14.95 14.75 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 29. Feedback Open Circuit Voltage vs. Junction Temperature Figure 30. Startup Threshold vs. Junction Temperature 10.5 VCC(off), MINIMUM OPERATING VOLTAGE (V) VFB(open), FEEDBACK OPEN CIRCUIT VOLTAGE (V) 755 10.3 10.1 9.9 9.7 9.5 −50 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 Figure 31. Minimum Operating Voltage vs. Junction Temperature http://onsemi.com 14 150 150 NCP1652, NCP1652A Iinhibit, INHIBIT BIAS CURRENT (mA) 950 900 850 800 750 700 650 −50 Vstartup(min), MINIMUM STARTUP VOLTAGE (V) 25.0 24.5 −25 0 25 50 75 100 125 310 290 270 250 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) Figure 33. Inhibit Bias Current vs. Junction Temperature 23.5 23.0 22.5 −25 0 25 150 6.0 50 75 100 125 150 5.8 5.6 5.4 5.2 5.0 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 34. Minimum Startup Voltage vs. Junction Temperature Figure 35. Startup Current vs. Junction Temperature 150 850 ICC1, SUPPLY CURRENT DEVICE DISABLED (mA) 30 IHV(off), OFF−STATE LEAKAGE CURRENT (mA) 330 TJ, JUNCTION TEMPERATURE (°C) 24.0 25 20 15 10 −50 350 Figure 32. Inhibit Threshold Voltage vs. Junction Temperature VCC = VCC − 0.5 V Istart = 0.5 mA 22.0 −50 150 Istart, STARTUP CURRENT (mA) Vinhibit, INHIBIT THRESHOLD VOLTAGE (V) 1000 −25 0 25 50 75 100 125 150 825 800 775 750 725 700 675 650 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 36. Off−State Leakage Current vs. Junction Temperature Figure 37. Supply Current Device Disabled (Overload) vs. Junction Temperature http://onsemi.com 15 150 NCP1652, NCP1652A 200 tOVLD, OVERLOAD TIMER (ms) ICC2, SUPPLY CURRENT DEVICE SWITCHING (mA) 6.75 6.55 6.35 6.15 5.95 5.75 −50 −25 0 25 50 75 100 125 150 140 120 100 −50 25 50 75 100 125 Figure 39. Overload Timer vs. Junction Temperature 150 500 5.1 4.9 4.7 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 480 460 440 420 400 −50 −25 Figure 40. Overload Detect Threshold vs. Junction Temperature 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 Figure 41. Brown−Out Detect Threshold vs. Junction Temperature 180 650 640 VBO(HYS), BROWN−OUT HYSTERESIS (mV) VBO(high), BROWN−OUT EXIT THRESHOLD (mV) 0 Figure 38. Supply Current Device Switching vs. Junction Temperature 5.3 630 620 610 600 −50 −25 TJ, JUNCTION TEMPERATURE (°C) VBO(low), BROWN−OUT DETECT THRESHOLD (mV) VOVLD, OVERLOAD DETECT THRESHOLD (V) 160 TJ, JUNCTION TEMPERATURE (°C) 5.5 4.5 −50 180 −25 0 25 50 75 100 125 150 175 170 165 160 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 42. Brown−Out Exit Threshold vs. Junction Temperature Figure 43. Brown−Out Hysteresis vs. Junction Temperature http://onsemi.com 16 NCP1652, NCP1652A 7.5 VCC VLATCH(low_HYS), LATCH PULL−UP THRESHOLD (V) VLATCH(low), LATCH PULL−DOWN VOLTAGE THRESHOLD (mV) 1000 980 960 940 920 900 −50 −25 0 25 50 75 100 125 7.1 6.9 6.7 6.5 −50 150 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 44. Latch Pull−Down Voltage Threshold vs. Junction Temperature Figure 45. Latch Pull−Up Threshold vs. Junction Temperature 7.5 VLATCH(delay), LATCH PROPAGATION DELAY (ms) 7.3 7.1 6.9 6.7 6.5 −50 150 60 −25 0 25 50 75 100 125 150 58 56 54 52 50 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 46. Latch Pull−Up Voltage Threshold vs. Junction Temperature Figure 47. Latch Propagation Delay vs. Junction Temperature 55 ILATCH(clamp), LATCH CLAMP CURRENT (mA) VLATCH(lhigh), LATCH PULL−UP VOLTAGE THRESHOLD (V) 7.3 54 53 52 51 50 −50 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 Figure 48. Latch Clamp Current vs. Junction Temperature http://onsemi.com 17 150 150 NCP1652, NCP1652A 100 VLATCH(shdn), LATCH−OFF CURRENT SHUTDOWN (mA) VLATCH(clamp), LATCH CLAMP VOLTAGE (V) 3.5 3.4 3.3 3.2 3.1 3.0 −50 −25 0 25 50 75 100 125 150 98 96 94 92 90 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 49. Latch Clamp Voltage vs. Junction Temperature Figure 50. Latch−Off Current Shutdown vs. Junction Temperature http://onsemi.com 18 150 NCP1652, NCP1652A DETAILED DEVICE DESCRIPTION Introduction designer familiarity and a vast range of available components. But, because it processes the power twice, the search is always on for a more compact and power efficient solution. The NCP1652 controller offers the convenience of shrinking the front−end converter (PFC preregulator) and the dc−dc converter into a single power processing stage as shown in Figure 52. The NCP1652 is a highly integrated controller combining PFC and an isolated step down ac−dc power conversion in a single stage, resulting in a lower cost and reduced part count solution. This controller is ideal for notebook adapters, battery chargers and other off−line applications with power requirements between 75 W and 150 W with an output voltage greater than 12 V. The single stage is based on the flyback converter and it is designed to operate in CCM or DCM modes. AC Input Power Factor Correction (PFC) Introduction Power factor correction shapes the input current of off−line power supplies to maximize the real power available from the mains. Ideally, the electrical appliance should present a load that emulates a pure resistor, in which case the reactive power drawn by the device is zero. Inherent in this scenario is the freedom from input current harmonics. The current is a perfect replica of the input voltage (usually a sine wave) and is exactly in phase with it. In this case the current drawn from the mains is at a minimum for the real power required to perform the needed work, and this minimizes losses and costs associated not only with the distribution of the power, but also with the generation of the power and the capital equipment involved in the process. The freedom from harmonics also minimizes interference with other devices being powered from the same source. Another reason to employ PFC in many of today’s power supplies is to comply with regulatory requirements. Today, electrical equipment in Europe must comply with the European Norm EN61000−3−2. This requirement applies to most electrical appliances with input power of 75 W or greater, and it specifies the maximum amplitude of line−frequency harmonics up to and including the 39th harmonic. While this requirement is not yet in place in the US, power supply manufacturers attempting to sell products worldwide are designing for compliance with this requirement. PFC Preregulator DC−DC Converter with isolator Vout This approach significantly reduces the component count. The NCP1652 based solution requires only one each of MOSFET, magnetic element, output rectifier (low voltage) and output capacitor (low voltage). In contrast, the 2−stage solution requires two or more of the above−listed components. Elimination of certain high−voltage components (e.g. high voltage capacitor and high voltage PFC diode) has significant impact on the system design. The resultant cost savings and reliability improvement are often worth the effort of designing a new converter. Single PFC Stage While the single stage offers certain benefits, it is important to recognize that it is not a recommended solution for all requirements. The following three limitations apply to the single stage approach: • The output voltage ripple will have a 2x line frequency component (120 Hz for North American applications) that can not be eliminated easily. The cause of this ripple is the elimination of the energy storage element that is typically the boost output capacitor in the 2−stage solution. The only way to reduce the ripple is to increase the output filter capacitance. The required value of capacitance is inversely proportional to the output voltage – hence this approach is not recommended for low voltage outputs such as 3.3 V or 5 V. However, if there is a follow−on dc−dc converter stage or a battery after the single stage converter, the low frequency ripple should not cause any concerns. • The hold−up time will not be as good as the 2−stage approach – again due to the lack of an intermediate energy storage element. • In a single stage converter, one FET processes all the power – that is both a benefit and a limitation as the stress on that main MOSFET is relatively higher. Similarly, the magnetic component (flyback transformer/inductor) can not be optimized as well as in A typical power supply consists of a boost PFC preregulator creating an intermediate X400 V bus and an isolated dc−dc converter producing the desired output voltage as shown in Figure 51. This architecture has two power stages. Rectifier & Filter NCP1652 Based Single−Stage Flyback Converter Figure 52. Single Stage Power Converter Typical Power Supply with PFC AC Input Rectifier & Filter Vout Figure 51. Typical Two Stage Power Converter A two stage architecture allows optimization of each individual power stage. It is commonly used because of http://onsemi.com 19 NCP1652, NCP1652A the 2−stage solution. As a result, potentially higher leakage inductance induces higher voltage spikes (like the one shown in Figure 53) on the MOSFET drain. This may require a MOSFET with a higher voltage rating compared to similar dc−input flyback applications. Vin Active Clamp Vout Figure 56. Active Clamp The first two methods result in dissipation of the leakage energy in the clamping circuits – the dissipation is proportional to LI2 where L is the leakage inductance of the transformer and I is the peak of the switch current at turn−off. An RDC snubber is simple and has the lowest cost, but constantly dissipates power. A TVS provides good voltage clamping at a slightly higher cost and dissipates power only when the drain voltage exceeds the voltage rating of the TVS. The active clamp circuit provides an intriguing alternative to the other methods. It requires addition of a MOSFET and a high voltage capacitor as part of the active clamp circuit, thus adding complexity, but it results in a complete reuse of the leakage inductance energy. As a result, the transformer construction is no longer critical and one can use cheaper cost solution. Also, the active clamp circuit reduces the voltage stress on the primary switch and that can lead to usage of lower cost or lower on resistance (RDS(on)) MOSFET. Finally, the turn−on switching losses are eliminated because the active clamp circuit allows the discharge of the MOSFET COSS capacitance prior to the turn−on. The energy stored in the leakage inductance is utilized for this transition. In many applications, the added complexity of the active clamp circuit may not be justified. However, the OUTB of the NCP1652 is also usable for another purpose, synchronous rectification control. Synchronous rectification for flyback converters is an emerging requirement for flyback converters. The OUTB signal from NCP1652 is ideal for interfacing with a secondary side synchronous rectifier controller such as NCP4303 as shown in Figure 57. As shown in Figure 57, using the OUTB (coupled through pulse transformer or Y−capacitor) as a trigger for the NCP4303 allows guaranteed turn−off of the secondary side synchronous MOSFET prior to turn−on of the primary switch. In any CCM flyback converter, this is a critical requirement to prevent cross−conduction and NCP1652 and NCP4303 combination is the first such chipset that guarantees the operation without cross−conduction. Figure 53. Typical Drain Voltage Waveform of a Flyback Main Switch There are a few methods to clamp the voltage spike on the main switch, a resistor−capacitor−diode (RCD) clamp, a transient voltage suppressor (TVS) or an active clamp using a MOSFET and capacitor can be used as shown in Figures 54 to 56. RCD Clamp Vin R C Vout D Figure 54. RCD Clamp TVS Clamp Vin Vout TVS Figure 55. TVS Clamp http://onsemi.com 20 NCP1652, NCP1652A VIN VOUT DRV TRIG NCP4303 OUTB NCP1652 OUTA Figure 57. NCP1652 and NCP4302 based single stage PFC with synchronous rectification. compensation is also added to the input signal to allow CCM operation above 50% duty cycle. The NCP1652 incorporates a secondary driver, OUTB, with adjustable non overlap delay for controlling a synchronous rectifier switch in the secondary side, an active clamp switch in the primary or both. In addition, the controller features a proprietary Soft−Skip™ to reduce acoustic noise at light loads. Other features found in the NCP1652 include a high voltage startup circuit, voltage feedforward, brown out detector, internal overload timer, latch input and a high accuracy multiplier. High Voltage Startup Circuit The NCP1652 internal high voltage startup circuit eliminates the need for external startup components and provides a faster startup time compared to an external startup resistor. The startup circuit consists of a constant current source that supplies current from the HV pin to the supply capacitor on the VCC pin (CCC). The startup current (Istart) is typically 5.5 mA. The OUTA and OUTB drivers are enabled and the startup current source is disabled once the VCC voltage reaches VCC(on), typically 15.3 V. The controller is then biased by the VCC capacitor. The drivers are disabled if VCC decays to its minimum operating threshold (VCC(off)) typically 10.3 V. Upon reaching VCC(off) the gate drivers are disabled. The VCC capacitor should be sized such VCC is kept above VCC(off) while the auxiliary voltage is building up. Otherwise, the system will not start. The controller operates in double hiccup mode while in overload or VCC(off). A double hiccup fault disables the drivers, sets the controller in a low current mode and allows VCC to discharge to VCC(off). This cycle is repeated twice to minimize power dissipation in external components during a fault event. Figure 58 shows double hiccup mode operation. A soft−start sequence is initiated the second time VCC reaches VCC(on). If the controller is latched upon reaching VCC(on), the controller stays in hiccup mode. During this mode, VCC never drops below VCC(reset), the controller logic reset level. This prevents latched faults to be cleared unless power to the controller is completely removed (i.e. unplugging the supply from the AC line). NCP1652 PFC Loop The NCP1652 incorporates a modified version of average current mode control used for achieving the unity power factor. The PFC section includes a variable reference generator, a low frequency voltage regulation error amplifier (AC error AMP), ramp compensation (Ramp Comp) and current shaping network. These blocks are shown in the lower portion of the bock diagram (Figure 51). The inputs to the reference generator include feedback signal (FB), scaled AC input signal (AC_IN) and feedforward input (VFF). The output of the reference generator is a rectified version of the input sine−wave scaled by the FB and VFF values. The reference amplitude is proportional to the FB and inversely proportional to the square of the VFF. This, for higher load levels and/or lower input voltage, the signal would be higher. The function of the AC error amp is to force the average current output of the current sense amplifier to match the reference generator output. The output of the AC error amplifier is compensated to prevent response to fast events. This output (Verror) is fed into the PWM comparator through a reference buffer. The PWM comparator sums the Verror and the instantaneous current and compares it to a 4.0 V threshold to provide the desired duty cycle control. Ramp http://onsemi.com 21 NCP1652, NCP1652A VCC VCC(on) VCC(off) t OUTA t Fault Timer (internal) Overload applied t tOVLD Figure 58. VCC Double Hiccup Operation with a Fault Occurring while the Startup Circuit is Disabled typically 0.85 V. Once VCC exceeds Vinhibit, the startup current source is enabled. This behavior is illustrated in Figure 59. This slightly increases the total time to charge VCC, but it is generally not noticeable. An internal supervisory circuit monitors the VCC voltage to prevent the controller from dissipating excessive power if the VCC pin is accidentally grounded. A lower level current source (Iinhibit) charges CCC from 0 V to Vinhibit, Figure 59. Startup Current at Various VCC Levels the HV pin as shown in Figure 60. Otherwise, the HV pin follows the ac line and the startup circuit is disabled every time the ac line voltage approaches 0 V. The VCC capacitor is sized to bias the controller during power up. The rectified ac line voltage is provided to the power stage to achieve accurate PFC. Filtering the rectified ac line voltage with a large bulk capacitor distorts the PFC in a single stage PFC converter. A peak charger is needed to bias http://onsemi.com 22 NCP1652, NCP1652A Peak Charger VOUT VIN HV OUTA NCP1652 Figure 60. Peak charger Adjustable Dead Time The startup circuit is rated at a maximum voltage of 500 V. Power dissipation should be controlled to avoid exceeding the maximum power dissipation of the controller. If dissipation on the controller is excessive, a resistor can be placed in series with the HV pin. This will reduce power dissipation on the controller and transfer it to the series resistor. OUTA and OUTB have an adjustable dead time between transitions to prevent simultaneous conduction of the main and synchronous rectifier or active clamp MOSFETs. The delay is also used to optimize the turn−off transition of the active clamp switch to achieve zero−volt switching of the main switch in an active clamp topology. Figure 61 shows the timing relationship between OUTA and OUTB. Drive Outputs The NCP1652 has out off phase output drivers with an adjustable non−overlap delay (tD). The main output, OUTA, drives the primary MOSFET. The secondary output, OUTB, is designed to provide a logic signal used to control a synchronous rectification switch in the secondary side, an active clamp switch in the primary or both. The outputs are biased directly from VCC and their high state voltage is approximately VCC. OUTA has a source resistance of 13 W (typical) and a sink resistance of 8.0 W (typical) OUTB has a source resistance 22 W (typical) and a sink resistance of 10 W (typical). OUTB is a purposely sized smaller than OUTA because the gate charge of an active switch or logic used with synchronous rectification is usually less than that of the primary MOSFET. If a higher drive capability is required, an external discrete driver can be used. The drivers are enabled once VCC reaches VCC(on) and there are no faults present. They are disabled once VCC discharges to VCC(off). OUTB is always the last pulse generated when the outputs are disabled due to a fault (latch−off, VCC(off), overload, or brown−out). The last pulse terminates at the end of the clock cycle. This ensures the active clamp capacitor is reset. The high current drive capability of OUTA and OUTB may generate voltage spikes during switch transitions due to parasitic board inductance. Shortening the connection length between the drivers and their loads and using wider connections will reduce inductance−induce spikes. tdelay(lead) tdelay(trail) OUTA OUTB Figure 61. Timing relationship between OUTA and OUTB. The dead time between OUTA and OUTB is adjusted by connecting a resistor, RD, from the RD pin to ground. The overlap delay is proportional to RD. The delay time can be set between 80 ns and 1.8 ms using the formula: t delay(in ns) + 8.0 R delay(in kW) with R delay varying between 10 kW and 230 kW AC Error Amplifier and Buffer The AC error amplifier (EA) shapes the input current into a high quality sine wave by forcing the filtered input current to follow the output of the reference generator. The output of the reference generator is a full wave rectified ac signal and it is applied to the non inverting input of the EA. The filtered input current, Iin, is the current sense signal at the http://onsemi.com 23 NCP1652, NCP1652A ISpos pin multiplied by the current sense amplifier gain. It is applied to the inverting input of the AC EA. The AC EA is a transconductance amplifier. A transconductance amplifier generates an output current proportional to its differential input voltage. This amplifier has a nominal gain of 100 mS (or 0.0001 A/V). That is, an input voltage difference of 10 mV causes the output current to change by 1.0 mA. The AC EA has typical source and sink currents of 70 mA. The filtered input current is a high frequency signal. A low frequency pole forces the average input current to follow the reference generator output. A pole-zero pair is created by placing a (RCOMP) and capacitor (CCOMP) series combination at the output of the AC EA. The AC COMP pin provides access to the AC EA output. The output of the AC EA is inverted and converted into a current using a second transconductance amplifier. The output of the inverting transconductance amplifier is VACEA(buffer). Figure 62 shows the circuit schematic of the AC EA buffer. The AC EA buffer output current, IACEA(out), is given by Equation 1. VDD x4 IACEA(out) + + − 2.8V VAC_REF 21.33kW + IAVG To PWM comparator 37.33kW gm = 100mS gm + − − AC error amplifier RIAVG AC COMP RAC_COMP Figure 62. AC EA Buffer Amplifier I ACEA(out) + ǒ Ǔ 2.8 * V ACEA 37.33k @4 amplifier is a wide bandwidth amplifier with a differential input. The current sense amplifier has two outputs, PWM Output and IAVG Output. The PWM Output is the instantaneous switch current which is filtered by the internal leading edge blanking (LEB) circuitry prior to applying it to the PWM Comparator non inverting input. The second output is a filtered current signal resembling the average value of the input current. Figure 63 shows the internal architecture of the current sense amplifier. (eq. 1) The voltage at the PWN non-inverting input is determined by IACEA(out), the instantaneous switch current along and the ramp compensation current. OUTA is terminated once the voltage at the PWM non-inverting input reaches 4 V. Current Sense Amplifier A voltage proportional to the main switch current is applied to the current sense input, ISPOS. The current sense http://onsemi.com 24 NCP1652, NCP1652A Ip Ispos gm = 250mS + − RCS blanking gm Current sense amplifier IAVG Inst. current A To PWM tLEB blanking tLEB VIAVG comparator Inst. current B To PWM skip comparator To AC error amplifier RIAVG Figure 63. Current Sense Amplifier Caution should be exercised when designing a filter between the current sense resistor and the ISPOS input, due to the low impedance of this amplifier. Any series resistance due to a filter creates a voltage offset (VOS) due to its input bias current, CAIbias. The input bias current is typically 60 mA. The voltage offset is given by Equation 2. V OS + CA Ibias @ R external I CS + I IN + V ISPOS 4k (eq. 3) The PWM Output delivers current to the positive input of the PWM input where it is added to the AC EA and ramp compensation signal. The IAVG Output generates a voltage signal to a buffer amplifier. This voltage signal is the product of IAVG and an external RIAVG resistor filtered by the capacitor on the IAVG pin, CIAVG. The pole frequency, fP, set by CIAVG should be significantly below the switching frequency to remove the high frequency content. But, high enough to not to cause significant distortion to the input full wave rectified sinewave waveform. A properly filtered average current signal has twice the line frequency. Equation 4 shows the relationship between CIAVG (in nF) and fP (in kHz). (eq. 2) The offset adds a positive offset to the current sense signal. The ac error amplifier will then try to compensate for the average output current which appears never to go to zero and cause additional zero crossing distortion. A voltage proportional to the main switch current is applied to the ISPOS pin. The ISPOS pin voltage is converted into a current, i1, and internally mirrored. Two internal currents are generated, ICS and IAVG. ICS is a high frequency signal which is a replica of the instantaneous switch current. IAVG is a low frequency signal. The relationship between VISPOS and ICS and IAVG is given by Equation 3. C IAVG + http://onsemi.com 25 1 2 @ p @ R IAVG @ f P (eq. 4) NCP1652, NCP1652A Oscillator The gain of the low frequency current buffer is set by the resistor at the IAVG pin, RIAVG. RIAVG sets the scaling factor between the primary peak and primary average currents. The gain of the current sense amplifier, ACA, is given by Equation 5. A CA + RI AVG The oscillator controls the switching frequency, f, the jitter frequency and the gain of the multiplier. The oscillator ramp is generated by charging the timing capacitor on the CT Pin, CT, with a 200 mA current source. This current source is tightly controlled during manufacturing to achieve a controlled and repeatable oscillator frequency. The current source turns off and CT is immediately discharged with a pull down transistor once the oscillator ramp reaches its peak voltage, VCT(peak), typically 4.0 V. The pull down transistor turns off and the charging current source turns on once the oscillator ramp reaches its valley voltage, VCT(valley). Figure 64 shows the resulting oscillator ramp and control circuitry. (eq. 5) 4k The current sense signal is prone to leading edge spikes during the main switch turn on due to parasitic capacitance and inductance. This spike may cause incorrect operation of the PWM Comparator. Filtering the current sense signal will inevitably change the shape of the current pulse. The NCP1652 incorporates LEB circuitry to block the first 200 ns (typical) of each current pulse. This removes the leading edge spikes without altering the current signal waveform. VDD x 1.2 To PWM comparator IAVG To PWM skip − + comparator RIAVG VDD CT + CT − + 4.0 V / 0.1 V Oscillator Figure 64. Oscillator Ramp and Control Circuitry The relationship between the oscillator frequency in kHz and timing capacitor in pF is given by Equation 6. CT + 47000 f A low frequency oscillator modulates the switching frequency, reducing the controller EMI signature and allowing the use of a smaller EMI filter. The frequency modulation or jitter is typically ±5% of the oscillator frequency. (eq. 6) http://onsemi.com 26 NCP1652, NCP1652A Output Overload 260 mV. A new Soft−Skip™ period starts once the voltage on the AC−IN pin increases to 260 mV. An increase in output load current terminates a Soft−Skip™ event. A transient load detector terminates a Soft−Skip™ period once VFB voltage exceeds VSSKIP by more than 550 mV. This ensures the required output power is delivered during a load transient and the output voltage does not fall out of regulation. Figure 66 shows the relationship between Soft−Skip™ and the transient load detector. The Feedback Voltage, VFB, is directly proportional to the output power of the converter. An internal 6.7 kW resistor pulls−up the FB voltage to the internal 6.5 V reference. An external optocoupler pulls down the FB voltage to regulate the output voltage of the system. The optocoupler is off during power up and output overload conditions allowing the FB voltage to reach its maximum level. The NCP1652 monitors the FB voltage to detect an overload condition. A typical startup time of a single PFC stage converter is around 100 ms. If the converter is out of regulation (FB voltage exceeds 5.0 V) for more that 150 ms (typical) the drivers are disabled and the controller enters the double hiccup mode to reduce the average power dissipation. A new startup sequence is initiated after the double hiccup is complete. This protection feature is critical to reduce power during an output short condition. Soft−Skip™ Cycle Mode The FB voltage reduces as the output power demand of the converter reduces. Once VFB drops below the skip threshold, VSSKIP, 1.30 V (typical) the drivers are disabled. The skip comparator hysteresis is typically 180 mV. The converter output voltage starts to decay because no additional output power is delivered. As the output voltage decreases the feedback voltage increases to maintain the output voltage in regulation. This mode of operation is known as skip mode. The skip mode frequency is dependent of load loop gain and output capacitance and can create audible noise due to mechanical resonance in the transformer and snubber capacitor. A proprietary Soft−Skip™ mode reduces audible noise by slowly increasing the primary peak current until it reaches its maximum value. The minimum skip ramp period, tSSKIP, is 2.5 ms. Figure 65 shows the relationship between VFB, VSSKIP and the primary current. VSSKIP VFB Figure 66. Load transient during Soft−Skip] The output of the Soft−Skip™ Comparator is or−ed with the PWM Comparator output to control the duty ratio. The Soft−Skip™ Comparator controls the duty ratio in skip mode and the PWM Comparator controls the duty cycle during normal operation. In skip mode, the non−inverting input of the Soft−Skip™ Comparator exceeds 4 V, disabling the drivers. As the FB voltage increases, the voltage at the non−inverting input is ramp down from 4 V to 0.2 V to enable the drivers. Multiplier and Reference Generator The NCP1652 uses a multiplier to regulate the average output power of the converter. This controller uses a proprietary concept for the multiplier used within the reference generator. This innovative design allows greatly improved accuracy compared to a conventional linear analog multiplier. The multiplier uses a PWM switching circuit to create a scalable output signal, with a very well defined gain. The output of the multiplier is the ac-reference signal. The ac-reference signal is used to shape the input current. The multiplier has three inputs, the error signal from an external error amplifier (VFB), the full wave rectified ac input (AC_IN) and the feedforward input (VFF). The FB signal from an external error amplifier circuit is applied to the VFB pin via an optocoupler or other isolation circuit. The FB voltage is converted to a current with a V-I Figure 65. Soft−Skip] operation. Skip mode operation is synchronous of the ac line voltage. The NCP1652 disables Soft−Skip™ when the rectified ac line voltage drops to its valley level. This ensures the primary current always ramp up reducing audible noise. A skip event occurring as the ac line voltage is decreasing, causes the primary peak current to ramp down instead of ramp up. Once the skip period is over the primary current is only determined by the ac line voltage. A Soft−Skip™ event terminates once the AC−IN pin voltage decreases below http://onsemi.com 27 NCP1652, NCP1652A factored by the AC_IN comparator output. The resulting signal is filtered by the low pass R-C filter on the CM pin. The low pass filter removes the high frequency content. The gain of the multiplier is determined by the V-I converter, the resistor on the CM pin, and the peak and valley voltages of the oscillator sawtooth ramp. converter. There is no error in the output signal due to the series rectifier as shown in Figure 67. The scaled version of the full wave rectified input ac wave is applied to the AC_IN pin by means of a resistive voltage divider. The multiplier ramp is generated by comparing the scaled line voltage to the oscillator ramp with the AC_IN Comparator. The current signal from the V-I converter is FB Multiplier V−to−I + AC IN V − V AC_REF +k@ Oscillator CM FB @V V AC_IN FF 2 AC_REF Divide VFF2 VFF Square Figure 67. Reference Generator The third input to the reference generator is the VFF signal. The VFF signal is a dc voltage proportional to the ac line voltage. A resistive voltage divider attenuates the full wave rectified line voltage between 0.7 and 5.0 V. The full wave rectified line is then averaged with a capacitor. The ac average voltage must be constant over each half cycle of the line. Line voltage ripple (120 Hz or 100 Hz) ripple on the VFF signal adds ripple to the output of the multiplier. This will distort the ac reference signal and reduce the power factor and increase the line current distortion. Excessive filtering delays the feedforward signal reducing the line transient response. A good starting point is to set the filter time constant to one cycle of the line voltage. The user can then optimize the filter for line transient response versus power factor. The average voltage on the VFF pin is: V FF + 2 Vac Ǹ2a p V AC_REF + V FB @ V AC_IN V FF 2 @k (eq. 8) The multiplier transfer function is given by Equation 8. The output of the multiplier is the AC_REF. It connects to the AC Error Amplifier. where, k is the reference generator gain, typically 0.55. The output of the reference generator is clamped at 4.5 V to limit the maximum output power. Feedforward maintains a constant input power independent of the line voltage. That is, for a given FB voltage, if the line voltage doubles (AC_IN), the feedforward term quadruples and reduces the output of the error amplifier in half to maintain the same input power. AC Error Amplifier Compensation A pole-zero pair is created by placing a series combination of RCOMP and CCOMP at the output of the AC error amplifier (EA). The value of the compensation components is (eq. 7) Where, a is the voltage divider ratio, normally 0.01. http://onsemi.com 28 NCP1652, NCP1652A dependent of the average input current and the instantaneous switch current. The gain of the average input current or slow loop is given by Equation 9. A LF + ǒ Ǔ R IAVG 4k @ ǒgm @ R AC_COMPǓ @ (2.286) where, Vin(LL) is the low line ac input voltage, D is the duty ratio, Pout is the output power, Pin is the input power, h is the efficiency, LP is the primary inductance and ton is the on time. Typical efficiency for this topology is around 88%. The current sense resistor is selected to achieve maximum signal resolution at the input of the ac reference amplifier. The maximum voltage input of the ac reference amplifier to prevent saturation is 4.5 V. This together with the instantaneous peak current is used to calculate the current sense resistor, RCS, using Equation 16. (eq. 9) The low frequency gain is the product of the current sense averaging circuit, the transconductance amplifier and the gain of the AC error amplifier. A current proportional to the instantaneous current is generated using a 4 kW resistor in the current sense amplifier input. This proportional current is applied to a 21.33 kW at the PWM comparator input to generate a current sense voltage signal. The high frequency or fast loop gain, AHF, is calculated using Equation 10. A HF + 21.33k 4k + 5.333 R CS + 4.5 R IAVG 4k @ ǒgm @ R AC_COMPǓ @ (2.286) t Subharmonic oscillations are observed in peak current-mode controllers operating in continuous conduction mode with a duty ratio greater than 50%. Injecting a compensation ramp on the current sense signal eliminates the subharmonic oscillations. The amount of compensation is system dependent and it is determined by the inductor falling di/dt. The NCP1652 has built in ramp compensation to facilitate system design. The amount of ramp compensation is set by the user with a resistor, RRCOMP, between the Ramp Comp pin and ground. The Ramp Comp pin buffers the oscillator ramp generated on the CT pin. The current across RRCOMP is internally mirrored with a 1:1.2 ratio. The inverted ac error amplifier and the instantaneous switch current signals are added to the ramp compensation mirrored current. The resulting current signal is applied to an internal 21.33 kW between the PWM Comparator non inverting input and ground as shown in Figure 64. The maximum voltage contribution of the ramp compensation signal to the error signal, VRCOMP, is given by Equation 17. (eq. 10) 5.333 (eq. 11) 2 Equation 12 is obtained by re-arranging Equation 11 for RAC_COMP. This equation provides the maximum value for RAC_COMP. R AC_COMP t 4666 R IAVG @ gm (eq. 12) The control loop zero, fZ, is calculated using Equation 13. The control loop zero should be set at approximately at 1/10th of the oscillator frequency, fOSC. The compensation capacitor is calculated using Equation 14. fz + 1 2p @ C AC_COMP @ R AC_COMP C AC_COMP + 1 2p @ f OSC 10 (eq. 13) (eq. 14) @ R AC_COMP V RCOMP + Current Sense Resistor Ǹ2 @ P out h @ V in(LL) @ D ) V in(LL) @ t on 0.88 @ 2 @ L P (1.2) @ ǒV CT(peak)Ǔ @ (21.33k) R RCOMP (eq. 17) + 102.38k R RCOMP where, VCT(peak) is the oscillator ramp peak voltage, typically 4.0 V. For proper ramp compensation, the ramp signal should match the falling di/dt (which has been converted to a dv/dt) of the inductor at 50% duty cycle. Both the falling di/dt and output voltage need to be reflected by the transformer turns ratio to the primary side. Equations 18 through 23 assist in the derivation of equations for RCS and RCOMP. The PFC stage has two control loops. The first loop controls the average input current and the second loop controls the instantaneous current across the main switch. The current sense signal affects both loops. The current sense signal is fed into the positive input of the error amplifier to control the average input current. In addition, the current sense information together with the ramp compensation and error amplifier signal control the instantaneous primary peak current. The primary peak current, IPK, is calculated using Equation 15, I PK + (eq. 16) R IAVG @ P in @ Ǹ2 Ramp Compensation Equation 11 shows system stability requirements. That is, the low frequency gain has to be less than one half of the high frequency gain. ǒ Ǔ 4k @ ǒV in(LL) @ DǓ di dt secondary di (eq. 15) dt primary http://onsemi.com 29 + + V out LS di dt secondary + @ V out LP NS NP + @ ǒ Ǔ NP NS V out N P LP NS 2 (eq. 18) (eq. 19) NCP1652, NCP1652A di V RCOMP + NS R CS + NP dt primary @ @ T @ R CS @ A HF L P @ 102.38k T @ A HF @ V out @ R RCOMP latch is Set dominant which means that if both R and S are high the S signal will dominate and Q will be high, which will hold the power switch off. The NCP1652 uses a pulse width modulation scheme based on a fixed frequency oscillator. The oscillator generates a voltage ramp as well as a pulse in sync with the falling edge of the ramp. The pulse is an input to the PWM Logic and Driver block. While the oscillator pulse is present, the latch is reset, and the output drive is in its low state. On the falling edge of the pulse, the OUTA goes high and the power switch begins conduction. The instantaneous inductor current is summed with a current proportional to the ac error amplifier output voltage. This complex waveform is compared to the 4 V reference signal on the PWM comparator inverting input. When the signal at the non-inverting input to the PWM comparator exceeds 4 V, the output of the PWM comparator toggles to a high state which drives the Set input of the latch and turns the power switch off until the next clock cycle. (eq. 20) (eq. 21) At low line and full load, the output of the ac error amplifier output is nearly saturated in a low state. While the ac error amplifier output is saturated, IACEA is zero and does not contribute to the voltage across the internal 21.33 kW resistor on the PWM comparator non-inverting input. In this operation mode, the voltage across the 21.33 kW resistor is determined solely by the ramp compensation and the instantaneous switch current as given by Equation 22. ǒ V ref(PWM) + V RCOMP @ Ǔ)V t on T INST (eq. 22) The voltage reference of the PWM Comparator, VREF(PWM), is 4 V. For these calculations, 3.8 V is used to provide some margin. The maximum instantaneous switch current voltage contribution, VINST, is given by Equation 23. V INST + I PK @ R CS @ A HF Brown−Out The NCP1652 incorporates a brown−out detection circuit to prevent the controller operate at low ac line voltages and reduce stress in power components. A scaled version of the rectified line voltage is applied to the VFF Pin by means of a resistor divider. This voltage is used by the brown out detector. A brown−out condition exists if the feedforward voltage is below the brown−out exit threshold, VBO(high), typically 0.45 V. The brown−out detector has 180 mV hysteresis. The controller is enabled once VFF is above 0.63 V and VCC reaches VCC(on). OUTB is the last drive pulse. Figure 68 shows the relationship between the brown−out, VCC, OUTA and OUTB signals. (eq. 23) Substituting Equation 23 in Equation 22, setting VREF(PWM) at 3.8 V (provides margin) and solving for RRCOMP, Equation 24 is obtained. R RCOMP + 102.38k ǒ3.8 * 5.333 @ IPK @ R CSǓ @ t on T (eq. 24) Replacing Equation 24 in Equation 21 we obtain: R CS + ǒ 3.8 N P N S @ A @V HF L Ǔ ) 5.333 I out@ton P (eq. 25) PK PWM Logic The PWM and logic circuits are comprised of a PWM comparator, an RS flip-flop (latch) and an OR gate. The http://onsemi.com 30 NCP1652, NCP1652A VCC VCC(on) VCC(off) t OUTA t Last OUTB Pulase OUTB t VFF VBO(low) VBO(high) Brown−Out t Figure 68. Relationship Between the Brown−Out, VCC, OUTA and OUTB Vaux or VCC VDD OVP comparator + − + Vlatch(high) Ilatch(clamp) blanking tlatch(delay) Latch−Off OTP comparator − I latch(shdn) S Q + + Latch R Vlatch(low) NTC Vlatch(clamp) Reset Figure 69. Latch Input Once the controller is latched, OUTA is disabled and OUTB generates a final pulse that ends with the oscillator period. No more pulses are generated after OUTB is terminated. Figure 70 shows the relationship between the Latch−Off, VCC, OUTA and OUTB signals. The NCP1652 has a dedicated latch input to easily latch the controller during overtemperature and overvoltage faults (See Figure 69). The controller is latched if the Latch−Off pin voltage is pulled below 1 V or above 6.5 V. http://onsemi.com 31 NCP1652, NCP1652A VCC VCC(on) VCC(off) t OUTA t Last OUTB Pulase OUTB t Latch−Off Vlatch(high) Latch−Off Vlatch(low) Latch−Off t Figure 70. Relationship Between the Latch−Off, VCC, OUTA and OUTB The Latch−Off pin is clamped at 3.5 V. A 50 mA (typical) pull−up current source is always on and a 100 mA (typical) pull−down current source is enabled once the Latch−Off pin voltage reaches 3.5 V (typical). This effectively clamps the Latch−Off pin voltage at 3.5 V. A minimum pull−up or pull−down current of 50 mA is required to overcome the internal current sources and latch the controller. The Latch−Off input features a 50 ms (typical) filter to prevent latching the controller due to noise or a line surge event. The startup circuit continues to cycle VCC between VCC(on) and VCC(off) while the controller is in latch mode. The controller exits the latch mode once power to the system is removed and VCC drops below VCC(reset). APPLICATION INFORMATION The electronic design tool allows the user to easily determine most of the system parameters of a single PFC stage The tool evaluates the power stage as well as the frequency response of the system. ON Semiconductor provides an electronic design tool, facilitate design of the NCP1652 and reduce development cycle time. The design tool can be downloaded at www.onsemi.com. ORDERING INFORMATION Package Shipping† NCP1652DWR2G SO−20 WB (Pb−Free) 1000 / Tape & Reel NCP1652DR2G SO−16 (Pb−Free) 2500 / Tape & Reel NCP1652ADR2G SO−16 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. The products described herein (NCP1652), may be covered by one or more of the following U.S. patents; 6,373,734. There may be other patents pending. http://onsemi.com 32 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−20 WB CASE 751D−05 ISSUE H DATE 22 APR 2015 SCALE 1:1 A 20 q X 45 _ M E h 0.25 H NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B b 0.25 M T A S B DIM A A1 b c D E e H h L q S L A 18X e SEATING PLANE A1 c T GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 20 20X 20X 1.30 0.52 20 XXXXXXXXXXX XXXXXXXXXXX AWLYYWWG 11 1 11.00 1 XXXXX A WL YY WW G 10 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 98ASB42343B SOIC−20 WB = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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