NCP331SNT1G

NCP331 Soft-Start Controlled Load Switch with Auto Discharge The NCP331 is a low Ron N−channel MOSFET controlled by a soft−start sequence of 2 ms for mobile applications. The very low RDS(on) allows system supplying or battery charging up to DC 2A.The device is enable due to external, active high, enable pin. Due to a current consumption optimization, leakage current is drastically decreased from the battery connected to the device, allowing long battery life. http://onsemi.com MARKING DIAGRAM TSOP−6 SN SUFFIX CASE 318G Features • • • • • • • • • • • 1.8 V – 5.5 V Operating Range 33 mW N MOSFET DC Current Up to 2 A Peak Current Up to 5 A Built−in Soft−Start 2 ms Reverse Voltage Protection Output Discharge EN Logic Pin: Active High ESD Ratings: Machine Model = B Human Body Model = 2 TSOP23−6 package This is a Pb−Free Device 1 331AYWG G 1 331 A Y W G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PINOUT DIAGRAM OUT IN OUT IN EN GND Typical Applications • • • • • Mobile Phones Tablets Digital Cameras GPS Computers (Top View) ORDERING INFORMATION See detailed ordering and shipping information on page 7 of this data sheet. LS or NCP331 5 6 IN IN OUT OUT 1 2 Platform IC’n 3 4 LDO /EN GND DCDC Converter EN ENx 0 Figure 1. Typical Application Circuit © Semiconductor Components Industries, LLC, 2013 November, 2013 − Rev. 1 1 Publication Order Number: NCP331/D NCP331 PIN FUNCTION DESCRIPTION Pin Name Pin Number Type Description IN 5,6 POWER Power−switch input voltage; connect a 0.1 mF or greater ceramic capacitor from IN to GND as close as possible to the IC. GND 4 POWER Ground connection. EN 3 INPUT OUT 1,2 OUTPUT Enable input, logic high turns on power switch. Power−switch output; connect a 0.1 mF ceramic capacitor from OUT to GND as close as possible to the IC is recommended. BLOCK DIAGRAM IN OUT Gate driver and soft start control Control logic Charge Pump EN EN block GND Figure 2. Block Diagram http://onsemi.com 2 NCP331 MAXIMUM RATINGS Symbol Value Unit IN, OUT, EN, Pins: Rating VEN, VIN, VOUT −0.3 to +7.0 V From IN to OUT Pins: Input/Output VIN, VOUT −7.0 to +7.0 V TJ −40 to +125 °C Storage Temperature Range TSTG −40 to +150 °C ESD Withstand Voltage Human Body model (HBM), model = 2, Machine Model (MM) model = B, (Note 1) Vesd Moisture Sensitivity (Note 2) MSL Maximum Junction Temperature Range V 2500 200 Level 1 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. According to JEDEC standard JESD22−A108. 2. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020. OPERATING CONDITIONS Symbol Parameter VIN Operational Power Supply VEN Enable Voltage Conditions Min Typ Max Unit 1.8 5.5 V 0 5.5 TA Ambient Temperature Range −40 25 + 85 °C TJ Junction Temperature Range −40 25 + 125 °C CIN Decoupling Input Capacitor 0.1 mF COUT Decoupling Output Capacitor 0.1 mF RqJA Thermal Resistance − Junction−to−Air IOUT Maximum DC Current PD (Notes 3 and 4) 305 °C/W 2 Power Dissipation Rating (Note 7) A TA ≤ 25°C 0.37 W TA = 85°C 0.13 W Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 3. The RqJA is dependent of the PCB heat dissipation. 4. The maximum power dissipation (PD) is given by the following formula: http://onsemi.com 3 NCP331 ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for VIN between 1.8 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and VIN = 5 V. Symbol Parameter Conditions Min Typ Max Unit POWER SWITCH RDS(on) Static drain−source on−state resistance VIN = 3 V, VIN = 5 V, TSOP package TJ = 25°C 33 –40°C < TJ < 125°C 60 mW VIN = 3.3 V From EN Vih to VOUT rising. (Note 5), CLOAD = 0.1 mF, RLOAD = 10 W 60 200 ms VIN = 3.0 V From EN Vih to 10% VOUT rising. CLOAD = 1 mF, RLOAD = 25 W 278 500 ms VIN = 3.3 V CLOAD = 0.1 mF, RLOAD = 10 W (Note 5), from En to 95% VOUT 1.2 2.05 3 VIN = 3.0 V CLOAD = 1 mF, RLOAD = 25 W (Note 6), from 10% to 90% VOUT 1.00 1.65 2.36 Disable time VIN = 3.0 V From EN high to low to VOUT falling TF Output fall time VIN = 3 V CLOAD = 1 mF, RLOAD = 25 W (Note 6) 0.1 0.18 0.5 TOFF Output off time VIN = 3 V CLOAD = 1 mF, RLOAD = 25 W (Notes 6 & 7), from EN to 10% VOUT 0.3 0.5 0.8 TEN TR Tdis Gate turn on Output rise time 0.3 ms ENABLE INPUT EN VIH High−level input voltage 1.15 VIL Low−level input voltage Rpd En pull−down resistor 1.1 Rdis Output discharge resistor 200 V 0.85 V 1.5 1.8 MW 400 600 W VIN = 0 V, VOUT = 4.2 V (part disable), TA = 25°C 0.3 1.2 mA En low, Vin = 3 V 1.3 3 mA No load, En high, Vin = 3 V 11 15 mA REVERSE−LEAKAGE PROTECTION IREV Reverse−current protection QUIESCENT CURRENT Istb Iq Standby current Current consumption Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Guaranteed by correlation with 3.0 V production test. 6. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground. 7. Guaranteed by Tfall and Rdischarge tests. http://onsemi.com 4 NCP331 TIMINGS Vin EN Vout TDIS TEN TR TOFF TON Figure 3. Timings http://onsemi.com 5 TF NCP331 TYPICAL CHARACTERISTICS 60 VIN = 5.0 V VIN = 1.8 V 55 50 VIN = 3.0 V VIN = 5.5 V 45 45 RDS(on) (mW) RDS(on) (mW) 50 40 35 40 35 30 30 25 25 20 −50 −25 0 25 50 75 TEMPERATURE (°C) 100 20 125 1.5 Figure 4. RDS(on) versus Temperature 30 TA = −40°C TA = 25°C TA = 85°C 8.0 3.5 VIN (V) 4 4.5 5 5.5 20 6.0 Iq (mA) ISTB (mA) 3 TA = −40°C TA = 25°C TA = 85°C 25 7.0 5.0 4.0 15 10 3.0 2.0 5 1.0 0 1.0 2.5 Figure 5. RDS(on) versus Input Voltage, Ambient Temperature 10 9.0 2 1.5 2.0 2.5 3.0 3.5 VIN (V) 4.0 4.5 5.0 0 5.5 1.0 Figure 6. Standby Current versus Input Voltage 1.5 2.0 2.5 3.0 3.5 VIN (V) 4.0 4.5 5.0 Figure 7. Quiescent Current versus Input Voltage http://onsemi.com 6 5.5 NCP331 FUNCTIONAL DESCRIPTION Overview The NCP331 is a high side N channel MOSFET power distribution switch designed to connect external voltage directly to the system. The auto−discharge is activated when EN pin is set to low level (disable state). The discharge path (Pull down NMOS) stays activated as long as EN pin is set at low level. Enable Input Blocking Control Enable pin is an active high. The part is in disable mode when EN is tied to low. Power MOSFET is opened. Pull down resistor is placed to maintained the part off if En pin is not externally driven. The parts becomes in enable mode if EN is tied high and Power MOSFET is turned of after ten and trise times. The blocking control circuitry switches the bulk of the power NMOS. When the part is off (No Vin or EN tied to GND externally), the body diode limits the leakage current IREV from OUT to IN. In this mode, anode of the body diode is connected to IN pin and cathode is connected to OUT pin. In operating condition, anode of the body diode is connected to OUT pin and cathode is connected to IN pin preventing the discharge of the power supply. Auto Discharge NMOS FET is placed between the output pin and GND, in order to discharge the application capacitor connected on OUT pin. APPLICATION INFORMATION Power Dissipation TJ + PD The device’s junction temperature depends on different contributor factor such as board layout, ambient temperature, device environment, etc... Yet, the main contributor in term of junction temperature is the power dissipation of the power MOSFET. Assuming this, the power dissipation and the junction temperature in normal mode can be calculated with the following equations: P D + R DS(on) PD RDS(on) IOUT TJ RqJA TA R qJA ) T A = Junction temperature (°C) = Package thermal resistance (°C/W) = Ambient temperature (°C) PCB Recommendations The NCP331 integrates an up to 2A rated NMOS FET, and the PCB design rules must be respected to properly evacuate the heat out of the silicon. By increasing PCB area, the RqJA of the package can be decreased, allowing higher power dissipation. (I OUT) 2 = Power dissipation (W) = Power MOSFET on resistance (W) = Output current (A) ORDERING INFORMATION Device NCP331SNT1G Marking Package Shipping† 331 TSOP−6 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE V 1 SCALE 2:1 D H ÉÉ ÉÉ 6 E1 1 NOTE 5 5 2 L2 4 GAUGE PLANE E 3 L b SEATING PLANE C DETAIL Z e DIM A A1 b c D E E1 e L L2 M c A 0.05 M DATE 12 JUN 2012 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 2: PIN 1. EMITTER 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. BASE 2 6. COLLECTOR 2 STYLE 3: PIN 1. ENABLE 2. N/C 3. R BOOST 4. Vz 5. V in 6. V out STYLE 4: PIN 1. N/C 2. V in 3. NOT USED 4. GROUND 5. ENABLE 6. LOAD STYLE 5: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 6: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 7: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. N/C 5. COLLECTOR 6. EMITTER STYLE 8: PIN 1. Vbus 2. D(in) 3. D(in)+ 4. D(out)+ 5. D(out) 6. GND STYLE 9: PIN 1. LOW VOLTAGE GATE 2. DRAIN 3. SOURCE 4. DRAIN 5. DRAIN 6. HIGH VOLTAGE GATE STYLE 10: PIN 1. D(OUT)+ 2. GND 3. D(OUT)− 4. D(IN)− 5. VBUS 6. D(IN)+ STYLE 11: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1/GATE 2 STYLE 12: PIN 1. I/O 2. GROUND 3. I/O 4. I/O 5. VCC 6. I/O STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 STYLE 14: PIN 1. ANODE 2. SOURCE 3. GATE 4. CATHODE/DRAIN 5. CATHODE/DRAIN 6. CATHODE/DRAIN STYLE 15: PIN 1. ANODE 2. SOURCE 3. GATE 4. DRAIN 5. N/C 6. CATHODE STYLE 16: PIN 1. ANODE/CATHODE 2. BASE 3. EMITTER 4. COLLECTOR 5. ANODE 6. CATHODE STYLE 17: PIN 1. EMITTER 2. BASE 3. ANODE/CATHODE 4. ANODE 5. CATHODE 6. COLLECTOR GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 XXXAYWG G 1 6X 3.20 XXX A Y W G 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB14888C TSOP−6 1 IC 0.95 XXX MG G = Specific Device Code =Assembly Location = Year = Work Week = Pb−Free Package STANDARD XXX = Specific Device Code M = Date Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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