NCP3418B

NCP3418B MOSFET Driver with Dual Outputs for Synchronous Buck Converters The NCP3418B is a single Phase 12 V MOSFET gate driver optimized to drive the gates of both high−side and low−side power MOSFETs in a synchronous buck converter. The high−side and low−side driver is capable of driving a 3000 pF load with a 25 ns propagation delay and a 20 ns transition time. With a wide operating voltage range, high or low side MOSFET gate drive voltage can be optimized for the best efficiency. Internal adaptive nonoverlap circuitry further reduces switching losses by preventing simultaneous conduction of both MOSFETs. The floating top driver design can accommodate VBST voltages as high as 30 V, with transient voltages as high as 35 V. Both gate outputs can be driven low by applying a low logic level to the Output Disable (OD) pin. An Undervoltage Lockout function ensures that both driver outputs are low when the supply voltage is low, and a Thermal Shutdown function provides the IC with overtemperature protection. The NCP3418B is pin−to−pin compatible with Analog Devices ADP3418 with the following advantages: Features http://onsemi.com MARKING DIAGRAMS 8 8 1 SO−8 D SUFFIX CASE 751 1 3418B ALYW G DFN−10 MN SUFFIX CASE 485C A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package 3418B ALYW G • Faster Rise and Fall Times • Thermal Shutdown for System Protection • Internal Pulldown Resistor Suppresses Transient Turn On of Either • • • • • • • • • MOSFET Anti Cross−Conduction Protection Circuitry Floating Top Driver Accommodates Boost Voltages of up to 30 V One Input Signal Controls Both the Upper and Lower Gate Outputs Output Disable Control Turns Off Both MOSFETs Complies with VRM10.x and VRM11.x Specifications Undervoltage Lockout Thermal Shutdown Thermally Enhanced Package Available These are Pb−Free Devices PIN CONNECTIONS BST IN OD VCC 1 BST IN OD VCC VCC (Top View) 10 DRVH SWN PGND PGND DRVL 1 8 DRVH SWN PGND DRVL ORDERING INFORMATION Device NCP3418BDR2G Package SO−8 (Pb−Free) Shipping† 2500 Tape & Reel 3000 Tape & Reel NCP3418BMNR2G DFN−10 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2006 1 March, 2006 − Rev. 5 Publication Order Number: NCP3418B/D NCP3418B OD 3 VCC TSD UVLO IN 2 8 DRVH 1 BST FALLING EDGE DELAY FALLING EDGE DELAY START STOP NON−OVERLAP TIMERS MONITOR 7 SWN MONITOR MIN DRVL OFF TIMER 4 5 6 VCC DRVL PGND Figure 1. Block Diagram PIN DESCRIPTION SO−8 1 DFN−10 1 Symbol BST Description Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value is between 100 nF and 1.0 mF. An external diode is required with the NCP3418B. Logic−Level Input. This pin has primary control of the drive outputs. Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low. Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND. Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND. Output drive for the lower MOSFET. Power Ground. Should be closely connected to the source of the lower MOSFET. Power Ground. Should be closely connected to the source of the lower MOSFET. Switch Node. Connect to the source of the upper MOSFET. Output drive for the upper MOSFET. 2 3 4 − 5 6 − 7 8 2 3 4 5 6 7 8 9 10 IN OD VCC VCC DRVL PGND PGND SWN DRVH http://onsemi.com 2 NCP3418B MAXIMUM RATINGS Rating Operating Ambient Temperature, TA Operating Junction Temperature, TJ (Note 1) Package Thermal Resistance: SO−8 Junction−to−Case, RqJC Junction−to−Ambient, RqJA (2−Layer Board) Package Thermal Resistance: DFN−10 (Note 2) Junction−to−Case, RqJC (From die to exposed pad) Junction−to−Ambient, RqJA Storage Temperature Range, TS Lead Temperature Soldering (10 sec): Reflow (SMD styles only) JEDEC Moisture Sensitivity Level Pb−Free (Note 3) SO−8 (260 peak profile) Value 0 to 85 0 to 150 45 123 7.5 55 −65 to 150 260 peak 1 Unit °C °C °C/W °C/W °C/W °C/W °C °C − Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Internally limited by thermal shutdown, 150°C min. 2. 2 layer board, 1 in2 Cu, 1 oz thickness. 3. 60−180 seconds minimum above 237°C. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. MAXIMUM RATINGS Pin Symbol VCC BST Pin Name Main Supply Voltage Input Bootstrap Supply Voltage Input VMAX 15 V 30 V wrt/PGND 35 V v 50 ns wrt/PGND 15 V wrt/SW 30 V BST + 0.3 V 35 V v 50 ns wrt/PGND 15 V wrt/SW VCC + 0.3 V VCC + 0.3 V VCC + 0.3 V 0V VMIN −0.3 V −0.3 V wrt/SW SW DRVH Switching Node (Bootstrap Supply Return) High−Side Driver Output −1.0 V DC −10 V< 200 ns −0.3 V wrt/SW DRVL IN OD PGND NOTE: Low−Side Driver Output DRVH and DRVL Control Input Output Disable Ground −0.3 V DC −2.0 V < 200 ns −0.3 V −0.3 V 0V All voltages are with respect to PGND except where noted. http://onsemi.com 3 NCP3418B ELECTRICAL CHARACTERISTICS (Note 4) (VCC = 12 V, TA = 0°C to +85°C, TJ = 0°C to +125°C unless otherwise noted.) Characteristic Supply Supply Voltage Range Supply Current OD Input Input Voltage High Input Voltage Low Hysteresis Input Current Propagation Delay Time (Note 5) PWM Input Input Voltage High Input Voltage Low Hysteresis Input Current High−Side Driver Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times (Note 5) Propagation Delay (Notes 5 & 6) Low−Side Driver Output Resistance, Sourcing Current Output Resistance, Sinking Current Timeout Delay Transition Times Propagation Delay Undervoltage Lockout UVLO Startup UVLO Shutdown Hysteresis Thermal Shutdown Over Temperature Protection Hysteresis 4. 5. 6. 7. − (Note 7) (Note 7) 150 − 170 20 − − °C °C − − − − − − 3.7 3.2 0.3 3.9 3.5 0.4 4.4 3.9 0.7 V V V − − − trDRVL tfDRVL tpdhDRVL tpdlDRVL VCC = 12 V (Note 7) VCC − VSW = 12 V (Note 7) DRVH−SW = 0 CLOAD = 3.0 nF (See Figure 3) (See Figure 3) − − − − − − − 1.8 1.0 85 16 11 30 20 3.0 2.5 − 25 15 60 30 W W ns ns ns ns ns − − trDRVH tfDRVH tpdhDRVH tpdlDRVH VBST − VSW = 12 V (Note 7) VBST − VSW = 12 V (Note 7) VBST − VSW = 12 V, CLOAD = 3.0 nF (See Figure 3) VBST − VSW = 12 V − − − − − − 1.8 1.0 16 11 30 25 3.0 2.5 25 15 60 45 W W ns ns ns ns − − − − − − − No internal pull−up or pull−down resistors 2.0 − − −1.0 − − 500 − − 0.8 − +1.0 V V mV mA − − − − tpdlOD tpdhOD − − − No internal pull−up or pull−down resistors − 2.0 − − −1.0 30 30 − − 500 − 50 50 − 0.8 − +1.0 60 60 V V mV mA ns ns VCC ISYS − BST = 12 V, IN = 0 V 4.6 − − 2.0 13.2 6.0 V mA Symbol Condition Min Typ Max Unit All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). AC specifications are guaranteed by characterization, but not production tested. For propagation delays, “tpdh’’ refers to the specified signal going high; “tpdl’’ refers to it going low. GBD: Guaranteed by design; not tested in production. Specifications subject to change without notice. http://onsemi.com 4 NCP3418B OD tpdlOD 90% DRVH or DRVL tpdhOD 10% Figure 2. Output Disable Timing Diagram IN tpdlDRVL DRVL 90% 2V 10% tpdhDRVH trDRVH 90% DRVH−SW 10% 2V 10% tpdhDRVL SW tpdlDRVH 90% tfDRVH 10% trDRVL tfDRVL 90% Figure 3. Nonoverlap Timing Diagram APPLICATIONS INFORMATION Theory of Operation High−Side Driver The NCP3418B is a single phase MOSFET driver designed for driving two N−channel MOSFETs in a synchronous buck converter topology. The NCP3418B will operate from 5 V or 12 V, but it has been optimized for high current multi−phase buck regulators that convert 12 Volt rail directly to the core voltage required by complex logic chips. A single PWM input signal is all that is required to properly drive the high−side and the low−side MOSFETs. Each driver is capable of driving a 3.3 nF load at frequencies up to 500 kHz. Low−Side Driver The low−side driver is designed to drive a ground−referenced low RDS(on) N−Channel MOSFET. The voltage rail for the low−side driver is internally connected to the VCC supply and PGND. The high−side driver is designed to drive a floating low RDS(on) N−channel MOSFET. The gate voltage for the high side driver is developed by a bootstrap circuit referenced to Switch Node (SW) pin. The bootstrap circuit is comprised of an external diode, and an external bootstrap capacitor. When the NCP3418B is starting up, the SW pin is at ground, so the bootstrap capacitor will charge up to VCC through the bootstrap diode See Figure 4. When the PWM input goes high, the high−side driver will begin to turn on the high−side MOSFET using the stored charge of the bootstrap capacitor. As the high−side MOSFET turns on, the SW pin will rise. When the high−side MOSFET is fully on, the switch node will be at 12 volts, and the BST pin will be at 12 volts plus the charge of the bootstrap capacitor (approaching 24 volts). The bootstrap capacitor is recharged when the switch node goes low during the next cycle. http://onsemi.com 5 NCP3418B Safety Timer and Overlap Protection Circuit Input Pins It is very important that MOSFETs in a synchronous buck regulator do not both conduct at the same time. Excessive shoot−through or cross conduction can damage the MOSFETs, and even a small amount of cross conduction will cause a decrease in the power conversion efficiency. The NCP3418B prevents cross conduction by monitoring the status of the external mosfets and applying the appropriate amount of “dead−time” or the time between the turn off of one MOSFET and the turn on of the other MOSFET. When the PWM input pin goes high, DRVL will go low after a propagation delay (tpdlDRVL). The time it takes for the low−side MOSFET to turn off (tfDRVL) is dependent on the total charge on the low−side MOSFET gate. The NCP3418B monitors the gate voltage of both MOSFETs and the switchnode voltage to determine the conduction status of the MOSFETs. Once the low−side MOSFET is turned off an internal timer will delay (tpdhDRVH) the turn on of the high−side MOSFET Likewise, when the PWM input pin goes low, DRVH will go low after the propagation delay (tpdDRVH). The time to turn off the high−side MOSFET (tfDRVH) is dependent on the total gate charge of the high−side MOSFET. A timer will be triggered once the high−side mosfet has stopped conducting, to delay (tpdhDRVL) the turn on of the low−side MOSFET Power Supply Decoupling The PWM input and the Output Disable pins of the NCP3418B have internal protection for Electro Static Discharge (ESD), but in normal operation they present a relatively high input impedance. If the PWM controller does not have internal pull−down resistors, they should be added externally to ensure that the driver outputs do not go high before the controller has reached its under voltage lockout threshold. The NCP5381 controller does include a passive internal pull−down resistor on the drive−on output pin. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBST) and the internal (or an external) diode. Selection of these components can be done after the high−side MOSFET has been chosen. The bootstrap capacitor must have a voltage rating that is able to withstand twice the maximum supply voltage. A minimum 50 V rating is recommended. The capacitance is determined using the following equation: CBST + QGATE DVBST The NCP3418B can source and sink relatively large currents to the gate pins of the external MOSFETs. In order to maintain a constant and stable supply voltage (Vcc) a low ESR capacitor should be placed near the power and ground pins. A 1 mF to 4.7 mF multi layer ceramic capacitor (MLCC) is usually sufficient. where QGATE is the total gate charge of the high−side MOSFET, and DVBST is the voltage droop allowed on the high−side MOSFET drive. For example, a NTD60N03 has a total gate charge of about 30 nC. For an allowed droop of 300 mV, the required bootstrap capacitance is 100 nF. A good quality ceramic capacitor should be used. The bootstrap diode must be rated to withstand the maximum supply voltage plus any peak ringing voltages that may be present on SW. The average forward current can be estimated by: IF(AVG) + QGATE fMAX where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be checked in−circuit, since this is dependent on the source impedance of the 12 V supply and the ESR of CBST. 12 V 12 V NCP3418 4 Output Enable PWM in BST DRVH SW OD DRVL 2 IN PGND Vcc 3 1 8 7 5 6 Vout Figure 4. NCP3418 Example Circuit http://onsemi.com 6 NCP3418B PACKAGE DIMENSIONS 10 PIN DFN MN SUFFIX CASE 485C−01 ISSUE A D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS ONTO BOTTOM SURFACE OF TERMINAL b. 6. DETAILS A AND B SHOW OPTIONAL VIEWS FOR END OF TERMINAL LEAD AT EDGE OF PACKAGE. DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 2.45 2.55 3.00 BSC 1.75 1.85 0.50 BSC 0.19 TYP 0.35 0.45 0.00 0.03 EDGE OF PACKAGE E L1 DETAIL A Bottom View (Optional) PIN 1 REFERENCE 2X 2X 0.15 C 0.15 C 0.10 C 10X 0.08 C SIDE VIEW A1 C 10X L 1 e 5 A1 E2 10X K DETAIL B Side View (Optional) 10 10X 6 b BOTTOM VIEW 0.10 C A B 0.05 C NOTE 3 0.5651 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 ÉÉ ÉÉ ÉÉ ÉÉ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ DETAIL B TOP VIEW (A3) A SEATING PLANE EXPOSED Cu D2 DETAIL A MOLD CMPD A3 SOLDERING FOOTPRINT* 2.6016 2.1746 1.8508 3.3048 10X 10X 0.3008 0.5000 PITCH DIMENSIONS: MILLIMETERS NCP3418B PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 ISSUE AG −X− A 8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 B 1 4 S 0.25 (0.010) M Y M −Y− G C −Z− H D 0.25 (0.010) M SEATING PLANE K N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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