NCP5181PG

NCP5181 High Voltage High and Low Side Driver The NCP5181 is a High Voltage Power MOSFET Driver providing two outputs for direct drive of 2 N−channel power MOSFETs arranged in a half−bridge (or any other high−side + low−side) configuration. It uses the bootstrap technique to insure a proper drive of the High−side power switch. The driver works with 2 independent inputs to accommodate any topology (including half−bridge, asymmetrical half−bridge, active clamp and full−bridge…). www.onsemi.com IN_HI IN_LO DRV_HI GND BRIDGE Features • • • • • • • • • • • • • High Voltage Range: up to 600 V dV/dt Immunity ±50 V/nsec Gate Drive Supply Range from 10 V to 20 V High and Low DRV Outputs Output Source / Sink Current Capability 1.4 A / 2.2 A 3.3 V and 5 V Input Logic Compatible Up to VCC Swing on Input Pins Matched Propagation Delays between Both Channels Outputs in Phase with the Inputs Independent Logic Inputs to Accommodate All Topologies Under VCC LockOut (UVLO) for Both Channels Pin to Pin Compatible with IR2181(S) These are Pb−Free Devices Applications • High Power Energy Management • Half−bridge Power Converters • Any Complementary Drive Converters (asymmetrical half−bridge, active clamp) • Full−bridge Converters • Bridge Inverters for UPS Systems VBOOT VCC DRV_LO 8 1 SOIC−8 D SUFFIX CASE 751 PDIP−8 P SUFFIX CASE 626 MARKING DIAGRAMS 8 5181 ALYWX G NCP5181P AWL YYWWG 1 NCP5181P, 5181 = Specific Device Code A = Assembly Location L = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb−Free Package PIN ASSIGNMENT PIN FUNCTION ORDERING INFORMATION IN_HI Logic Input for High Side Driver Output In Phase IN_LO Logic Input for Low Side Driver Output In Phase GND Ground DRV_LO Low Side Gate Drive Output VCC Low Side and Main Power Supply VBOOT Bootstrap Power Supply DRV_HI High Side Gate Drive Output BRIDGE Bootstrap Return or High Side Floating Supply Return © Semiconductor Components Industries, LLC, 2016 January, 2016 − Rev. 8 Shipping† Device Package NCP5181PG PDIP−8 (Pb−Free) 50 Units/Tube NCP5181DR2G SOIC−8 (Pb−Free) 2.500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1 Publication Order Number: NCP5181/D NCP5181 Vbulk C1 VCC D4 GND 5 GND GND D1 T1 C3 SG3526 MC34025 TL594 C5 1 2 3 U1 VCC VBOOT IN_HI DRV_HI IN_LO Bridge GND DRV_LO 8 C4 L1 Out+ Q1 C3 7 Out− 6 4 D2 Q2 C6 NCP51XX GND GND U2 R1 D3 GND Figure 1. Typical Application VCC UV DETECT VCC VBOOT IN_HI PULSE TRIGGER LEVEL SHIFTER S Q R Q DRV_HI GND UV DETECT GND BRIDGE VCC DELAY IN_LO DRV_LO GND GND GND GND Figure 2. Detailed Block Diagram www.onsemi.com 2 NCP5181 MAXIMUM RATINGS Rating Symbol Value Unit VCC −0.3 to 20 V VBOOT −1 to 620 V VBRIDGE −1 to 600 V Main Power Supply Voltage VHV: High Voltage BOOT Pin VHV: High Voltage BRIDGE Pin VHV: Floating Supply Voltage VBOOT − VBRIDGE 0 to 20 V VHV: High Side Output Voltage VDRV_HI VBRIDGE−0.3 to VBOOT+0.3 V Low Side Output Voltage VDRV_LO −0.3 to VCC+0.3 V dVBRIDGE/dt 50 V/ns VIN_XX −1.0 to VCC+0.3 V 2.0 200 kV V Allowable Output Slew Rate Inputs IN_HI, IN_LO ESD Capability: Human Body Model (All Pins Except Pins 6−7−8) Machine Model (All Pins Except Pins 6−7−8) Latchup Capability per Jedec JESD78 °C/W Power Dissipation and Thermal Characteristics PDIP8: Thermal Resistance, Junction−to−Air SO−8: Thermal Resistance, Junction−to−Air Maximum Operating Junction Temperature RqJA RqJA 100 178 TJ_max +150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 3 NCP5181 ELECTRICAL CHARACTERISTICS (VCC = Vboot = 15 V, Vgnd = Vbridge, −40°C < TA < 125°C, Outputs loaded with 1 nF) Symbol Rating TA −40°C to 125°C Units OUTPUT SECTION Min Typ Max Output High Short Circuit pulsed Current VDRV = 0 V, PW ≤ 10 ms, (Note 1) IDRVhigh − 1.4 − A Output Low Short Circuit Pulsed Current VDRV = VCC, PW ≤ 10 ms, (Note 1) IDRVlow − 2.2 − A Output Resistor (Typical Value @ 25°C Only) Source ROH − 5 12 W Output Resistor (Typical Value @ 25°C Only) Sink ROL − 2 8 W Symbol Min Typ Max Units Turn−on Propagation Delay (Vbridge = 0 V) tON − 100 170 ns Turn−off Propagation Delay (Vbridge = 0 V or 50 V) (Note 2) tOFF − 100 170 ns Output Voltage Risetime (from 10% to 90% @ VCC = 15 V) with 1 nF Load tr − 40 60 ns Output Voltage Falling Edge (from 90% to 10% @ VCC = 15 V) with 1 nF Load tf − 20 40 ns Propagation Delay Matching between the High Side and the Low Side @ 25°C (Note 3) Dt − 20 35 ns tPW − − 100 ns Low Level Input Voltage Threshold VIN − − 0.8 V Input Pulldown Resistor (VIN < 0.5 V) RIN − 200 − kW High Level Input Voltage Threshold VIN 2.3 − − V VCC_stup 7.9 8.9 9.8 V VCC_shtdwn 7.3 8.2 9.0 V Hysteresis on VCC VCC_hyst 0.3 0.7 − V Vboot Startup Voltage Threshold Reference to Bridge Pin (Vboot_stup = Vboot − Vbridge) Vboot_stup 7.9 8.9 9.8 V Vboot UV Shutdown Voltage Threshold Vboot_shtdwn 7.3 8.2 9.0 V Hysteresis on Vboot Vboot_shtdwn 0.3 0.7 − V IHV_LEAK − 0.5 40 mA Consumption in Active Mode (VCC = Vboot, fsw = 100 kHz and 1 nF Load on Both Driver Outputs) ICC1 − 4.5 6.5 mA Consumption in Inhibition Mode (VCC = Vboot) ICC2 − 250 400 mA VCC Current Consumption in Inhibition Mode ICC3 − 215 − mA Vboot Current Consumption in Inhibition Mode ICC4 − 35 − mA DYNAMIC OUTPUT SECTION Rating Minimum Input Pulse Width that Changes the Output INPUT SECTION SUPPLY SECTION VCC UV Startup Voltage Threshold VCC UV Shutdown Voltage Threshold Leakage Current on High Voltage Pins to GND (VBOOT = VBRIDGE = DRV_HI = 600 V) *Note: see also characterization curves 1. Guaranteed by design. 2. Turn−off propagation delay @ Vbridge = 600 V is guaranteed by design 3. See characterization curve for Dt parameters variation on the full range temperature. 4. Timing diagram definition see Figures 4, 5 and 6. www.onsemi.com 4 NCP5181 IN_HI IN_LO DRV_HI DRV_LO Figure 3. Input/Output Timing Diagram 50% IN_HI IN_LO 50% tr ton 90% DRV_HI DRV_LO tf toff 90% 10% 10% Figure 4. Switching Time Waveform Definitions IN_LO 50% 50% IN_HI ton toff Delta_t DRV_HI 90% 10% toff Delta_t 90% ton DRV_LO 10% Figure 5. Delay Matching Waveforms Definition IN_LO & IN_HI 50% 50% ton_HI toff_HI 90% Delta_t DRV_HI 10% Delta_t ton_LO toff_LO DRV_LO 10% Figure 6. Other Delay Matching Waveforms Definition www.onsemi.com 5 90% NCP5181 TYPICAL CHARACTERISTICS 140 ton High Side 140 Ton PROPAGATION DELAY (ns) Ton PROPAGATION DELAY (ns) 160 ton High Side 120 ton Low Side 100 80 60 40 20 0 −40 0 20 40 60 80 100 ton Low Side 80 60 40 20 10 120 12 14 16 18 TEMPERATURE (°C) SUPPLY VOLTAGE; VCC = Vboot (V) Figure 7. Turn−on Propagation Delay vs. Temperature Figure 8. Turn−on Propagation Delay vs. VCC Voltage (VCC = Vboot) 20 160 160 Toff PROPAGATION DELAY (ns) Toff PROPAGATION DELAY (ns) 100 0 −20 180 toff High Side 140 120 100 toff Low Side 80 60 40 20 0 −40 140 toff High Side 120 100 toff Low Side 80 60 40 20 0 −20 0 20 40 60 80 100 120 10 12 14 16 18 TEMPERATURE (°C) SUPPLY VOLTAGE; VCC = Vboot (V) Figure 9. Turn−off Propagation Delay vs. Temperature Figure 10. Turn−off Propagation Delay vs. VCC Voltage (VCC = Vboot) 20 130 Toff PROPAGATION DELAY (ns) 130 Ton PROPAGATION DELAY (ns) 120 110 90 70 50 110 90 70 50 0 10 20 30 40 50 0 10 20 30 40 BRIDGE PIN VOLTAGE (V) BRIDGE PIN VOLTAGE (V) Figure 11. High Side Turn−on Propagation Delay vs. VBRIDGE Voltage Figure 12. High Side Turn−off Propagation Delay vs. VBRIDGE Voltage www.onsemi.com 6 50 NCP5181 40 35 35 30 TURN−ON RISE TIME (ns) TURN−ON RISE TIME (ns) TYPICAL CHARACTERISTICS 30 tr High Side 25 tr Low Side 20 15 10 5.0 0 −40 tr Low Side 25 20 tr High Side 15 10 5.0 0 −20 0 20 40 60 80 100 10 120 12 14 16 TEMPERATURE (°C) SUPPLY VOLTAGE; VCC = Vboot (V) Figure 13. Turn−on Rise Time vs. Temperature Figure 14. Turn−on Rise Time vs. VCC Voltage (VCC = Vboot) 20 20 30 18 TURN−OFF FALL TIME (ns) 25 tf Low Side 20 tf High Side 15 10 5.0 0 −40 tf Low Side 16 14 12 10 tf High Side 8.0 6.0 4.0 2.0 0 −20 0 20 40 60 80 100 120 10 12 14 16 18 TEMPERATURE (°C) SUPPLY VOLTAGE; VCC = Vboot (V) Figure 15. Turn−off Fall Time vs. Temperature Figure 16. Turn−off Fall Time vs. VCC Voltage (VCC = Vboot) PROPAGATION DELAY MATCHING (ns) TURN−OFF FALL TIME (ns) 18 40 35 30 25 20 15 10 5 0 −40 −20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 17. Propagation Delay Matching Between High Side and Low Side Driver www.onsemi.com 7 120 20 NCP5181 1.4 LOW LEVEL INPUT VOLTAGE THRESHOLD (V) LOW LEVEL INPUT VOLTAGE THRESHOLD (V) TYPICAL CHARACTERISTICS 1.2 1.0 0.8 0.6 0.4 0.2 0 −40 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 10 16 18 20 Figure 19. Low Level Input Voltage Threshold vs. VCC Voltage 2.5 HIGH LEVEL INPUT VOLTAGE THRESHOLD (V) 2.5 HIGH LEVEL INPUT VOLTAGE THRESHOLD (V) 14 SUPPLY VOLTAGE; VCC = Vboot (V) Figure 18. Low Level Input Voltage Threshold vs. Temperature 2.0 1.5 1.0 0.5 0 −40 2.0 1.5 1.0 0.5 0 −20 0 20 40 60 80 120 100 10 12 14 16 18 20 TEMPERATURE (°C) SUPPLY VOLTAGE; VCC = Vboot (V) Figure 20. High Level Input Voltage Threshold vs. Temperature Figure 21. High Level Input Voltage Threshold vs. VCC Voltage 4.0 0.40 HIGH SIDE LEAKAGE CURRENT TO GND (mA) LEAKAGE CURRENT TO GND (mA) 12 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 −40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 −20 0 20 40 60 80 TEMPERATURE (°C) 100 0 120 Figure 22. Leakage Current on High Voltage Pins (600 V) to Ground vs. Temperature 100 200 300 400 BRIDGE PIN VOLTAGE (V) 500 Figure 23. Leakage Current on High Voltage Pins to Ground vs. Vbridge Voltage (Vbridge = Vboot = VDRV_HI) www.onsemi.com 8 600 NCP5181 TYPICAL CHARACTERISTICS 100 BOOTSTRAP SUPPLY CURRENT (mA) BOOTSTRAP SUPPLY CURRENT (mA) 100 80 60 40 20 0 −40 −20 0 20 40 60 80 100 120 0 10 12 14 16 18 Figure 25. High Side Supply Current vs. Bootstrap Supply Voltage 20 500 VCC SUPPLY CURRENT (mA) VCC SUPPLY CURRENT (mA) 20 Figure 24. High Side Supply Current vs. Temperature 300 200 100 400 300 200 100 0 −20 0 20 40 60 80 100 120 10 12 14 16 20 18 TEMPERATURE (°C) VCC, SUPPLY VOLTAGE (V) Figure 26. VCC Supply Current vs. Temperature Figure 27. VCC Supply Current vs. VCC Supply Voltage 9.0 UVLO SHUTDOWN VOLTAGE th (V) 10 UVLO STARTUP VOLTAGE th (V) 40 BOOTSTRAP SUPPLY VOLTAGE (V) 400 9.8 9.6 9.4 9.2 Vboot UVLO stup th 9.0 8.8 VCC UVLO stup th 8.6 8.4 8.2 8.0 −40 60 TEMPERATURE (°C) 500 0 −40 80 −20 0 20 40 60 80 100 120 8.8 8.6 8.4 VCC UVLO shtdwn th 8.2 8.0 Vboot UVLO shtdwn th 7.8 7.6 7.4 7.2 7.0 −40 −20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 28. UVLO Start Up Voltage vs. Temperature Figure 29. UVLO Shut Down Voltage vs. Bootstrap Supply Voltage www.onsemi.com 9 120 NCP5181 TYPICAL CHARACTERISTICS 60 Cload = 1 nF / Q = 15 nC 30 ICC + Iboot CURRENT SUPPLY (mA) ICC + Iboot CURRENT SUPPLY (mA) 35 Rgate = 22 W 25 Rgate = 10 W 20 Rgate = 0 W 15 10 5.0 0 0 200 300 400 500 Rgate = 22 W 40 Rgate = 0 W 30 Rgate = 10 W 20 10 0 0 600 100 200 300 500 400 600 SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) Figure 30. ICC1 Consumption vs. Switching Frequency with 15 nC Load on Each Driver Figure 31. ICC1 Consumption vs. Switching Frequency with 33 nC Load on Each Driver 140 Cload = 3.3 nF / Q = 50 nC 70 ICC + Iboot CURRENT SUPPLY (mA) ICC + Iboot CURRENT SUPPLY (mA) 80 100 Cload = 2.2 nF / Q = 33 nC 50 Rgate = 22 W 60 Rgate = 10 W 50 Rgate = 0 W 40 30 20 10 Rgate = 22 W Cload = 6.6 nF / Q = 100 nC 120 Rgate = 10 W 100 Rgate = 0 W 80 60 40 20 0 0 0 100 200 300 400 600 500 0 100 200 300 400 500 600 SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) Figure 32. ICC1 Consumption vs. Switching Frequency with 50 nC Load on Each Driver Figure 33. ICC1 Consumption vs. Switching Frequency with 100 nC Load on Each Driver www.onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PDIP−8 CASE 626−05 ISSUE P DATE 22 APR 2015 SCALE 1:1 D A E H 8 5 E1 1 4 NOTE 8 b2 c B END VIEW TOP VIEW WITH LEADS CONSTRAINED NOTE 5 A2 A e/2 NOTE 3 L SEATING PLANE A1 C D1 M e 8X SIDE VIEW b 0.010 eB END VIEW M C A M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY. 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). DIM A A1 A2 b b2 C D D1 E E1 e eB L M INCHES MIN MAX −−−− 0.210 0.015 −−−− 0.115 0.195 0.014 0.022 0.060 TYP 0.008 0.014 0.355 0.400 0.005 −−−− 0.300 0.325 0.240 0.280 0.100 BSC −−−− 0.430 0.115 0.150 −−−− 10 ° MILLIMETERS MIN MAX −−− 5.33 0.38 −−− 2.92 4.95 0.35 0.56 1.52 TYP 0.20 0.36 9.02 10.16 0.13 −−− 7.62 8.26 6.10 7.11 2.54 BSC −−− 10.92 2.92 3.81 −−− 10 ° NOTE 6 GENERIC MARKING DIAGRAM* STYLE 1: PIN 1. AC IN 2. DC + IN 3. DC − IN 4. AC IN 5. GROUND 6. OUTPUT 7. AUXILIARY 8. VCC XXXXXXXXX AWL YYWWG XXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98ASB42420B PDIP−8 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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