NCP5220AMNR2G

NCP5220 3−in−1 PWM Dual Buck and Linear Power Controller The NCP5220 3−in−1 PWM a Dual Buck and Linear Power Controller, is a complete power solution for MCH and DDR memory. This IC combines the efficiency of PWM controllers for the VDDQ supply and the MCH core supply voltage with the simplicity of linear regulator for the VTT termination voltage. This IC contains two synchronous PWM buck controller for driving four external N−Ch FETs to form the DDR memory supply voltage (VDDQ) and the MCH regulator. The DDR memory termination regulator (VTT) is designed to track at the half of reference voltage with sourcing and sinking current. Protective features include, soft−start circuitry, undervoltage monitoring of 5VDUAL, BOOT voltage and thermal shutdown. The device is housed in a thermal enhanced space−saving DFN−20 package. Features • Pb−Free Package is Available* • Incorporates Synchronous PWM Buck Controllers for VDDQ and • • • • • • • • • • • • • VMCH Integrated Power FETs with VTT Regulator Source/Sink up to 2.0 A All External Power MOSFETs are N−Channel Adjustable VDDQ and VMCH by External Dividers VTT Tracks at Half the Reference Voltage Fixed Switching Frequency of 250 kHz for VDDQ and VMCH Doubled Switching Frequency of 500 kHz for VDDQ Controller in Standby Mode to Optimize Inductor Current Ripple and Efficiency Soft−Start Protection for All Controllers Undervoltage Monitor of Supply Voltages Overcurrent Protections for DDQ and VTT Regulators Fully Complies with ACPI Power Sequencing Specifications Short Circuit Protection Prevents Damage to Power Supply Due to Reverse DIMM Insertion Thermal Shutdown 5x6 DFN−20 Package http://onsemi.com NCP5220 AWLYYWW 1 DFN−20 MN SUFFIX CASE 505AB • DDR I and DDR II Memory and MCH Power Supply 1 NCP5220 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week PIN CONNECTIONS COMP FBDDQ SW_DDQ BG_DDQ TG_DDQ BOOT SS PGND VTT VDDQ 5VDUAL COMP_1P5 SLP_S3 TG_1P5 BG_1P5 GND_1P5 AGND FBVTT SLP_S5 FB1P5 NOTE: Pin 21 is the thermal pad on the bottom of the device. ORDERING INFORMATION Device Typical Applications MARKING DIAGRAM 20 NCP5220MNR2 NCP5220MNR2G Package Shipping† DFN−20 2500 Tape & Reel DFN−20 (Pb−Free) 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2004 November, 2004 − Rev. 4 1 Publication Order Number: NCP5220/D NCP5220 12 V SLP_S3 SLP_S3 SLP_S5 BOOT SLP_S5 13 V Zener SS 5VDUAL 5VDUAL CSS VTT VTT 1.25 V, 2.0 Apk M1 COUT2 TG_DDQ VDDQ FBVTT 2.5 V, 20 A L AGND SW_DDQ COUT1 M2 NCP5220 BG_DDQ CZM2 R5 CZM1 PGND COMP_1P5 RZM2 RZM1 CPM1 FB1P5 COMP 5VDUAL CZ1 R6 M3 VMCH CZ2 CP1 TG_1P5 RZ1 L R1 RZ2 FBDDQ 1.5 V, 10 A COUT3 M4 R2 BG_1P5 VDDQ PGND Figure 1. Application Diagram http://onsemi.com 2 NCP5220 VREF VCC VOLTAGE and CURRENT REFERENCE _VREFGD SLP_S5 THERMAL SHUTDOWN TSD 12 V BOOT 13 V ZENER SLP_S3 VCC _BOOTGD R10 5VDUAL S0 CONTROL LOGIC BOOT_ 5VDUAL S3 UVLO VREF R11 VOCP + ILIM 5VDUAL + − R12 5VDUAL_ VREF R13 VCC TG_DDQ VDDQ UVLO _5VDLGD L V1P5 VDDQ SW_DDQ PGND VCC BG_DDQ SS M2 COUT1 PGND PGND OSC M1 and PWM LOGIC CSS 5VDUAL S0 S3 COMP VREF CZ1 AMP CZ2 CP1 RZ1 A1 FBDDQ R1 RZ2 R2 5VDUAL VCC M3 TP_1P5 VMCH L2 PGND 1805 Phase Shift VCC BG_1P5 M4 COUT3 GND_1P5 PGND COMP_1P5 AMP_MCH VREF CZM1 CZM2 CPM1 RZM1 A1 FB1P5 5VDUAL S0 RM2 VDDQ R16 M2 R17 VTT Regulation Control AGND VTT VTT R18 5VDUAL COUT2 M3 R19 AGND AGND PGND FBVTT Figure 2. Internal Block Diagram http://onsemi.com 3 RM1 RZM2 NCP5220 PIN DESCRIPTION Pin Symbol 1 COMP VDDQ error amplifier compensation node. Description 2 FBDDQ DDQ regulator feedback pin. 3 SS 4 PGND 5 VTT 6 VDDQ Power input for VTT linear regulator. 7 AGND Analog ground connection and remote ground sense. 8 FBVTT VTT regulator pin for closed loop regulation. 9 SLP_S5 Active LOW control signal to activate S5 Power OFF State. 10 FB1P5 11 GND_1P5 12 BG_1P5 Gate driver output for V1P5 regulator low side N−Channel Power FET. 13 TG_1P5 Gate driver output for V1P5 regulator high side N−Channel Power FET. 14 SLP_S3 Active LOW control signal to activate S3 sleep state. 15 COMP_1P5 16 5VDUAL 17 BOOT 18 TG_DDQ Gate driver output for DDQ regulator high side N−Channel Power FET. 19 BG_DDQ Gate driver output for DDQ regulator low side N−Channel Power FET. 20 SW_DDQ DDQ regulator switch node and current limit sense input. 21 TH_PAD Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane under the IC. Soft−start pin of DDQ and MCH. Power ground. VTT regulator output. V1P5 switching regulator feedback pin. Power ground for V1P5 regulator. V1P5 error amplifier compensation node. 5.0 V dual supply input, which is monitored by undervoltage lock out circuitry. Gate driver input supply, which is monitored by undervoltage lock out circuitry, and a boost capacitor connection between SWDDQ and this pin. MAXIMUM RATINGS Rating Symbol Value Unit 5VDUAL −0.3, 6.0 V BOOT −0.3, 14 V Gate Drive (Pins 12, 13, 18, 19) to AGND (Pin 7) Vg −0.3 DC, −4.0 for t100 ns; 14 V Input / Output Pins to AGND (Pin 7) Pins 1−3, 5, 6, 8−10, 14−15, 20 VIO −0.3, 6.0 V Power Supply Voltage (Pin 16) to AGND (Pin 7) BOOT (Pin 17) to AGND (Pin 7) PGND (Pin 4), GND_1P5 (Pin 11) to AGND (Pin 7) VGND −0.3, 0.3 V Thermal Characteristics DFN−20 Plastic Package Thermal Resistance Junction−to−Air RqJA 35 °C/W Operating Junction Temperature Range TJ 0 to + 150 °C Operating Ambient Temperature Range TA 0 to + 70 °C Storage Temperature Range Tstg − 55 to +150 °C Moisture Sensitivity Level MSL 2.0 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) " 2.0 kV per JEDEC standard: JESD22–A114. Machine Model (MM) " 200 V per JEDEC standard: JESD22–A115. 2. Latchup Current Maximum Rating: " 150 mA per JEDEC standard: JESD78. http://onsemi.com 4 NCP5220 ELECTRICAL CHARACTERISTICS (5VDUAL = 5.0 V, BOOT = 12 V, TA = 0°C to 70°C, L = 1.7 mH, COUT1 = 3770 mF, COUT2 = 470 mF, COUT3 = NA, CSS = 33 nF, R1 = 2.166 kW, R2 = 2.0 kW, RZ1 = 20 kW, RZ2 = 8.0 W, CP1 = 10 nF, CZ1 = 6.8 nF, CZ2 = 100 nF, RM1 = 2.166 kW, RM2 = 2.0 kW, RZM1 = 20 kW, RZM2 = 8.0 W, CPM1 = 10 nF, CZM1 = 6.8 nF, CZM2 = 100 nf for min/max values unless otherwise noted). Duplicate component values of MCH regulator from DDQ. Characteristic Symbol Test Conditions Min Typ Max Unit 4.5 5.0 5.5 V 12.0 13.2 V SUPPLY VOLTAGE 5VDUAL Operating Voltage BOOT Operating Voltage V5VDUAL VBOOT SUPPLY CURRENT S0 Mode Supply Current from 5VDUAL I5VDL_S0 SLP_S5 = HIGH, SLP_S3 = HIGH, BOOT = 12 V, TG_1P5 and BG_1P5 Open 10 mA S3 Mode Supply Current from 5VDUAL I5VDL_S3 SLP_S5 = HIGH, SLP_S3 = LOW, TG_1P5 and BG_1P5 Open 5.0 mA S5 Mode Supply Current from 5VDUAL I5VDL_S5 SLP_S5 = LOW, BOOT = 0 V, TG_1P5 and BG_1P5 Open 1.0 mA S0 Mode Supply Current from BOOT IBOOT_S0 SLP_S5 = HIGH, SLP_S3 = HIGH, BOOT = 12 V, TG_1P5 and BG_1P5 Open 25 mA S3 Mode Supply Current from BOOT IBOOT_S3 SLP_S5 = HIGH, SLP_S3 = LOW, TG_1P5 and BG_1P5 Open 25 mA 4.4 V 550 mV 10.4 V UNDERVOLTAGE−MONITOR 5VDUAL UVLO Upper Threshold 5VDUAL UVLO Hysteresis V5VDLUV+ V5VDLhys BOOT UVLO Upper Threshold VBOOTUV+ BOOT UVLO Hysteresis VBOOThys 250 400 1.0 V THERMAL SHUTDOWN Tsd (Note 3) 145 °C Tsdhys (Note 3) 25 °C VFBQ TA = 25°C TA = 0°C to 70°C Feedback Input Current IDDQFB V(FBDDQ) = 1.3 V Oscillator Frequency in S0 Mode FDDQS0 217 Oscillator Frequency in S3 Mode FDDQS3 434 Thermal Shutdown Thermal Shutdown Hysteresis DDQ SWITCHING REGULATOR FBDDQ Feedback Voltage, Control Loop in Regulation Oscillator Ramp Amplitude dVOSC (Note 3) Current Limit Blanking Time in S0 Mode 1.178 1.166 1.190 1.202 1.214 V 1.0 mA 250 283 KHz 500 566 KHz 1.3 Vp−p TDDQbk (Note 3) 400 nS Current Limit Threshold Offset from 5VDUAL VOCP (Note 3) 0.8 V Minimum Duty Cycle Dmin 0 % Maximum Duty Cycle Dmax Soft−Start Pin Current for DDQ 100 Iss1 V(SS) = 0.5 V 4.0 % mA DDQ ERROR AMPLIFIER DC Gain GAINDDQ (Note 3) 70 dB Gain−Bandwidth Product GBWDDQ COMP PIN to GND = 220 nF, 1.0 W in Series (Note 3) 12 MHz SRDDQ COMP PIN TO GND = 10 pF 8.0 V/uS Slew Rate 3. Guaranteed by design, not tested in production. http://onsemi.com 5 NCP5220 ELECTRICAL CHARACTERISTICS (5VDUAL = 5.0 V, BOOT = 12 V, TA = 0°C to 70°C, L = 1.7 mH, COUT1 = 3770 mF, COUT2 = 470 mF, COUT3 = NA, CSS = 33 nF, R1 = 2.166 kW, R2 = 2.0 kW, RZ1 = 20 kW, RZ2 = 8.0 W, CP1 = 10 nF, CZ1 = 6.8 nF, CZ2 = 100 nF, RM1 = 2.166 kW, RM2 = 2.0 kW, RZM1 = 20 kW, RZM2 = 8.0 W, CPM1 = 10 nF, CZM1 = 6.8 nF, CZM2 = 100 nf for min/max values unless otherwise noted). Duplicate component values of MCH regulator from DDQ. Characteristic Symbol Test Conditions Min DVTTS0 IOUT= 0 to 2.0 A (sink current) IOUT= 0 to –2.0 A (source current) −30 Typ Max Unit 30 mV VTT ACTIVE TERMINATION REGULATOR VTT tracking DDQ_REF/2 at S0 mode VTT Source Current Limit ILIMVTsrc 2.0 A VTT Sink Current Limit ILIMVTsnk 2.0 A SLP_S5, SLP_S3 Input Logic HIGH Logic_H 2.0 SLP_S5, SLP_S3 Input Logic LOW Logic_L 0.8 V Ilogic 1.0 mA CONTROL SECTION SLP_S5, SLP_S3 Input Current V GATE DRIVERS TGDDQ Gate Pull−HIGH Resistance RH_TG VCC = 12 V, V(TGDDQ) = 11.9 V 3.0 W TGDDQ Gate Pull−LOW Resistance RL_TG VCC = 12 V, V(TGDDQ) = 0.1 V 2.5 W BGDDQ Gate Pull−HIGH Resistance RH_BG VCC = 12 V, V(BGDDQ) = 11.9 V 3.0 W BGDDQ Gate Pull−LOW Resistance RL_BG VCC = 12 V, V(BGDDQ) = 0.1 V 1.3 W TG1P5 Gate Pull−HIGH Resistance RH_TPG VCC = 12 V, V(TG1P5) = 11.9 V 3.0 W TG1P5 Gate Pull−LOW Resistance RL_TPG VCC = 12 V, V(TG1P5) = 0.1 V 2.5 W BG1P5 Gate Pull−HIGH Resistance RH_BPG VCC = 12 V, V(BG1P5) = 11.9 V 3.0 W BG1P5 Gate Pull−LOW Resistance RL_BPG VCC = 12 V, V(BG1P5) = 0.1 V 1.3 W VFB1P5 Feedback Voltage, Control Loo in Regulation VFB1P5 TA = 0°C to 70°C Feedback Input Current I1P5FB MCH SWITCHING REGULATOR Oscillator Frequency F1P5 Oscillator Ramp Amplitude dV1P5OSC Minimum Duty Cycle Dmin_1P5 Maximum Duty Cycle Dmax_1P5 Soft−Start Pin Current for V1P5 Regulator 0.784 217 (Note 4) 0.8 250 0.816 V 1.0 mA 283 1.3 0 % 100 ISS2 (Note 4) 4. Guaranteed by design, not tested in production. http://onsemi.com 6 KHz Vp−p 8.0 % mA NCP5220 TYPICAL OPERATING CHARACTERISTICS 550 1.195 SWITCHING FREQUENCY (kHz) VFBQ, FEEDBACK VOLTAGE (V) 1.196 1.194 1.193 1.192 1.191 1.190 1.189 1.188 1.187 500 S3 MODE 450 400 350 300 250 S0 MODE 200 0 20 40 60 80 0 Figure 3. VFBQ Feedback Voltage vs. Ambient Temperature VFB1P5, FEEDBACK VOLTAGE (V) 0.809 0.807 0.805 0.803 0.801 0.799 0.797 0.795 0 20 40 60 80 −19 2.0 A Sourcing Current with 10 ms period and 1.0 ms pulse width −21 80 31.2 2.0 A Sinking Current with 10 ms period and 1.0 ms pulse width 31 30.8 30.6 30.4 30.2 30 29.8 0 20 40 60 80 TA, AMBIENT TEMPERATURE (°C) Figure 6. VTT Sink Current Load Regulation vs. Ambient Temperature 0.03 0.02 0.01 0 −0.01 −22 Sourcing/Sinking Current with 10 ms period and 1.0 ms pulse width TA = 25°C −0.02 −23 −24 60 Figure 4. Oscillation Frequency in S0/S3 vs. Ambient Temperature Figure 5. VFB1P5 Feedback Voltage vs. Ambient Temperature DVTT, OUTPUT VOLTAGE (VDDQ/2 V) DVTT, SOURCE CURRENT LOAD REGULATION (mVp−p) TA, AMBIENT TEMPERATURE (°C) −20 40 TA, AMBIENT TEMPERATURE (°C) DVTT, SINK CURRENT LOAD REGULATION (mVp−p) TA, AMBIENT TEMPERATURE (°C) 20 −0.03 0 20 40 60 80 −0.04 −2.5 −1.5 −0.5 0.5 1.5 2.5 TA, AMBIENT TEMPERATURE (°C) IVTT, OUTPUT LOAD CURRENT (A) Figure 7. VTT Source Current Load Regulation vs. Ambient Temperature Figure 8. VTT, Output Voltage vs. Load Current http://onsemi.com 7 NCP5220 TYPICAL OPERATING WAVEFORMS Channel 1: VDDQ Output Voltage, 1.0 V/div Channel 2: VTT Output Voltage, 1.0 V/div Channel 3: V1P5 Output Voltage, 1.0V/div Time Base: 5.0 ms/div Channel 1: SLP_S3 Pin Voltage, 5.0 V/div Channel 2: VDDQ Output Voltage, AC−Coupled, 20 mV/div Channel 3: VTT Output Voltage, AC−Coupled, 100 mV/div Channel 4: V1P5 Output Voltage, 50 mV/div Time Base: 10 ms/div Figure 9. Power−Up Sequence Figure 10. S0−S3−S0 Transition 500 mA Applied to VDDQ 417 mA Applied to VTT 288 mA Applied to V1P5 Channel 1: SLP_S5 Pin Voltage, 5.0 V/div Channel 2: VDDQ Output Voltage, 1.0 V/div Channel 3: VTT Output Voltage, 1.0 V/div Channel 4: V1P5 Output Voltage, 1.0 V/div Time Base: 10 ms/div Channel 1: Current sourced out of VTT, 2.0 A/div Channel 2: VDDQ Output Voltage, AC−Coupled, 100 mV/div Channel 3: VTT Output Voltage, AC−Coupled, 20 mV/div Channel 4: V1P5 Output Voltage, AC−Coupled, 100 mV/div Time Base: 200 ms/div Figure 12. VTT Source Current Transient, 0A−2A–0A Figure 11. S0−S5−S0 Transition http://onsemi.com 8 NCP5220 TYPICAL OPERATING WAVEFORMS Channel 1: Current Sunk into VTT, 2.0 A/div Channel 2: VDDQ output Voltage, AC−Coupled, 100 mV/div Channel 3: VTT Output Voltage, AC−Coupled, 50 mV/div Channel 4: V1P5 Vutput Voltage, AC−Coupled, 100 mV/div Time Base: 200 ms/div Channel 1: Current Sourced into V1P5, 10 A/div Channel 2: VDDQ Output Voltage, AC−Coupled, 100 mV/div Channel 3: VTT Output Voltage, AC−Coupled, 100 mV/div V1P5 Output Voltage, AC−Coupled, 100 mV/div Time Base: 1.0 ms/div Figure 13. VTT Sink Current Transient, 0A−2A−0A Figure 14. VDDQ Source Current Transient, 0A–20A–0A Channel 1: Current Sourced into VDDQ, 10 A/div Channel 2: VDDQ Output Voltage, AC−Coupled, 50 mV/div Channel 3: VTT Output Voltage, AC−Coupled, 100 mV/div Channel 4: V1P5 Output Voltage, AC−Coupled, 100 mV/div Time Base: 1.0 ms/div Channel 1: Current Sourced into VDDQ, 2.0 A/div Channel 2: VDDQ Output Voltage, AC−Coupled, 50 mV/div Time Base: 200 ms/div Figure 16. S3 Mode without 12VATX, 0A–2A–0A Figure 15. V1P5 Source Current Transient, 0A–12A–0A http://onsemi.com 9 NCP5220 DETAILED OPERATION DESCRIPTIONS General S5 to S0 Mode Power−Up Sequence The NCP5220 3−in−1 PWM Dual Buck Linear DDR Power Controller contains two high efficiency PWM controllers and an integrated two−quadrant linear regulator. The VDDQ supply is produced by a PWM switching controller with two external N−Ch FETs. The VTT termination voltage is an integrated linear regulator with sourcing and sinking current capability which tracks at ½ VDDQ. The MCH core voltage is created by the secondary switching controller. The inclusion of soft−start, supply undervoltage monitors and thermal shutdown, makes this device a total power solution for the MCH and DDR memory system. This device is packaged in a DFN−20. The ACPI control logic is enabled by the assertion of _VREFGD. Once the ACPI control is activated, the power− up sequence starts by waking up the 5VDUAL voltage monitor block. If the 5VDUAL supply is within the preset levels, the BOOT undervoltage monitor block is then enabled. After 12VATX is ready and the BOOT UVLO is asserted LOW, the ACPI control triggers this device from S5 shutdown mode into S0 normal operating mode by activating the soft−start of DDQ switching regulator, providing SLP_S3 and SLP_S5 remain HIGH. Once the DDQ regulator is in regulation and the soft−start interval is completed, the _InRegDDQ signal is asserted HIGH to enable the VTT regulator as well as the V1P5 switching regulator. ACPI Control Logic The ACPI control logic is powered by the 5VDUAL supply. It accepts external control at the SLP_S3 input and internal supply voltage monitoring signals from two UVLOs to decode the operating mode in accordance with the state transition diagram in Figure 18. These UVLOs monitor the external supplies, 5VDUAL and 12VATX, through 5VDUAL and BOOT pins respectively. Two control signals, _5VDUALGD and _BOOTGD, are asserted when the supply voltages are good. When the device is powered up initially, it is in the S5 shutdown mode to minimize the power consumption. When all three supply voltages are good with SLP_S3 and SLP_S5 remaining HIGH, the device enters the S0 normal operating mode. The transition of SLP_S3 from HIGH to LOW while in the S0 mode, triggers the device into the S3 sleep mode. In S3 mode the 12VATX supply collapses. On transition of SLP_S3 from LOW to HIGH, the device returns to S0 mode. The IC can re−enter S5 mode by setting SLP_S5 LOW. A timing diagram is shown in Figure 17. Table 1 summarizes the operating states of all the regulators, as well as the conditions of the output pins. DDQ Switching Regulator In S0 mode the DDQ regulator is a switching synchronous rectification buck controller driving two external power N−Ch FETs to supply up to 20 A. It employs voltage mode fixed frequency PWM control with external compensation switching at 250kHz ± 13.2%. As shown in Figure 2, the VDDQ output voltage is divided down and fed back to the inverting input of an internal amplifier through the FBDDQ pin to close the loop at VDDQ = VFBQ × (1 + R1/R2). This amplifier compares the feedback voltage with an internal reference voltage of 1.190 V to generate an error signal for the PWM comparator. This error signal is compared with a fixed frequency RAMP waveform derived from the internal oscillator to generate a pulse−width−modulated signal. This PWM signal drives the external N−Ch FETs via the TG_DDQ and BG_DDQ pins. External inductor L and capacitor COUT1 filter the output waveform. When the IC leaves the S5 state, the VDDQ output voltage ramps up at a soft−start rate controlled by the capacitor at the SS pin. When the regulation of VDDQ is detected in S0 mode, _INREGDDQ goes HIGH to notify the control block. In S3 standby mode, the switching frequency is doubled to reduce the conduction loss in the external N−Ch FETs. Internal Bandgap Voltage Reference An internal bandgap reference is generated whenever 5VDUAL exceeds 2.7 V. Once this bandgap reference is in regulation, an internal signal _VREFGD will be asserted. Table 1. Mode, Operation and Output Pin Conditions OPERATING CONDITIONS OUTPUT PIN CONDITIONS MODE DDQ VTT MCH TG_DDQ BG_DDQ TP_1P5 BG_1P5 S0 Normal Normal Normal Normal Normal Normal Normal S3 Standby H−Z OFF Standby Standby Low Low S5 OFF H−Z OFF Low Low Low Low http://onsemi.com 10 NCP5220 pin directly, VTT voltage is designed to automatically track at the half of VDDQ. This regulator is stable with any value of output capacitor greater than 470 mF, and is insensitive to ESR ranging from 1 mW to 400 mW. For enhanced efficiency, an active synchronous switch is used to eliminate the conduction loss contributed by the forward voltage of a diode or Schottky diode rectifier. Adaptive non−overlap timing control of the complementary gate drive output signals is provided to reduce shoot−through current that degrades efficiency. Fault Protection of VTT Active Terminator To provide protection for the internal FETs, bi−directional current limit preset at 2.4 A magnitude is implemented. The VTT provides a soft−start function during start up. Tolerance of VDDQ Both the tolerance of VFBQ and the ratio of the external resistor divider R1/R2 impact the precision of VDDQ. With the control loop in regulation, VDDQ = VFBQ × (1 + R1/R2). With a worst case (for all valid operating conditions) VFBQ tolerance of ±1.5%, a worst case range of ±2% for VDDQ will be assured if the ratio R1/R2 is specified as 1.100 ±1%. MCH Switching Regulator The secondary switching regulator is identical to the DDQ regulator except the output is 10 A. No fault protection is implemented and the soft−start timing is twice as fast with respect to CSS. BOOT Pin Supply Voltage Fault Protection of VDDQ Regulator In typical application, a flying capacitor is connected between SWDDQ and BOOT pins. In S0 mode, 12VATX is tied to BOOT pin through a Schottky diode as well. A 13 V Zener clamp circuit must clamp this boot strapping voltage produced by the flying capacitor in S0 mode. In S3 mode the 12VATX is collapsed and the BOOT voltage is created by the Schottky diode between 5VDUAL and BOOT pins as well as the flying capacitor. The BOOT_UVLO works specially. The _BOOTGD goes low and the IC remains in S3 mode. In S0 mode, an internal voltage (VOCP) = 5VDUAL – 0.8 sets the current limit for the high−side switch. The voltage VOCP pin is compared to the voltage at SWDDQ pin when the high−side gate drive is turned on after a fixed period of blanking time to avoid false current limit triggering. When the voltage at SWDDQ is lower than VOCP, an overcurrent condition occurs and all regulators are latched off to protect against overcurrent. The IC will be powered up again if one of the supply voltages, 5VDUAL, SLP_S5 or 12VATX, is recycled. The main purpose is for fault protection, not for precise current limit. In S3 mode, this overcurrent protection feature is disabled. Thermal Consideration Assuming an ambient temperature of 50°C, the maximum allowed dissipated power of DFN−20 is 2.8 W, which is enough to handle the internal power dissipation in S0 mode. To take full advantage of the thermal capability of this package, the exposed pad underneath must be soldered directly onto a PCB metal substrate to allow good thermal contact. Feedback Compensation of VDDQ Regulator The compensation network is shown in Figure 2. VTT Active Terminator The VTT active terminator is a 2 quadrant linear regulator with two internal N−Ch FETs to provide current sink and source capability up to 2.0 A. It is activated only when the DDQ regulator is in regulation in S0 mode. It draws power from VDDQ with the internal gate drive power derived from 5VDUAL. While VTT output is connecting to the FBVTT Thermal Shutdown When the junction temperature of the IC exceeds 145°C, the entire IC is shutdown. When the junction temperature drops below 120°C, the chip resumes normal operation. http://onsemi.com 11 NCP5220 5VSTBY or 5VDUAL 12 V SLP_S5 Switching Frequency Doubles SLP_S3 SS Pin DDQ−S0 VTT MCH State 1 2 3 4 5 6 7 8 9 SO 10 S3 11 12 13 14 SO 15 16 17 S5 2. 5VSTBY or 5VSTB is the ultimate chip enable, SLP_S5 and SLP_S3 go HIGH. This supply has to be up first to ensure gates are in known state. 3. 12 V supply ramp. 4. DDQ will ramp with the tracking of SS pin, timing is 1.2 * CSS / 4 m (sec). 5. DDQ SS is completed, then SS pin is released from DDQ. SS pin is shorted to ground. 5. MCH ramps with the tracking of SS pin ramp, timing is 0.8 * CSS / 8 m (sec). VTT start up with current limit. 6. MCH SS is completed, then SS pin is released from MCH, SS pin is shorted to ground. S0 Mode. 7. S3 MODE −− SLP_S3 = L. 8. VTT and MCH will be turned off. 9. 12 V ramps to 0 V. 10. Standard S3 State. 11. SLP_S3 goes HIGH. 12. 12 V ramps back to regulation. 13. 12 V UVLO = L and SLP_S3 = H. MCH ramps with SS pin, timing is 0.8 * CSS / 8 m (sec). VTT rises. 14. S0 Mode. 15. S5 Mode −− SLP_S5 = L. 16. DDQ, VTT and MCH Turned OFF. 17. S5 Mode. Figure 17. NCP5220 Power−Up and Power−Down http://onsemi.com 12 NCP5220 S5 SLP_S3 = 1 AND SLP_S5 = 1 AND _BOOTGD = 1 SLP_S5 = 0 OR (SLP_S3 = 1 AND _BOOTGD = 0) SLP_S5 = 0 S0 SLP_S3 = 1 AND SLP_S5 = 1 AND _BOOTGD = 1 SLP_S3 = 0 AND SLP_S5 = 1 NOTE: 5VDUAL is assumed to be in good conditions in any mode. All possible state transitions are shown. All unspecified inputs do not cause any state change. S3 Figure 18. Transitions State Diagram of NCP5220 http://onsemi.com 13 NCP5220 APPLICATION INFORMATION Application Circuit Power MOSFET Selection Figure 20, on the following page, shows the typical application circuit for NCP5220. The NCP5220 is specifically designed as a total power solution for the MCH and DDR memory system. This diagram contains NCP5220 for driving four external N−Ch FETs to form the DDR memory supply voltage (VDDQ) and the MCH regulator. Power MOSFETs are chosen by balancing the cost with the requirements for the current load of the memory system and the efficiency of the converter provided. The selections criteria can be based on drain−source voltage, drain current, on−resistance RDS(on) and input gate capacitance. Low RDS(on) and high drain current power MOSFETs are usually preferred to achieve the high current requirement of the DDR memory system and MCH, as well as the high efficiency of the converter. The tradeoff is a corresponding increase in the input gate capacitor of the power MOSFETs. Output Inductor Selection The value of the output inductor is chosen by balancing ripple current with transient response capability. A value of 1.7 mH will yield about 3.0 A peak−peak ripple current when converting from 5.0 V to 2.5 V at 250 kHz. It is important that the rated inductor current is not exceeded during full load, and that the saturation current is not less than the expected peak current. Low ESR inductors may be required to minimize DC losses and temperature rise. PCB Layout Considerations Input capacitors for PWM power supplies are required to provide a stable, low impedance source node for the buck regulator to convert from. The usual practice is to use a combination of electrolytic capacitors and multi−layer ceramic capacitors to provide bulk capacitance and high frequency noise suppression. It is important that the capacitors are rated to handle the AC ripple current at the input of the buck regulators, as well as the input voltage. In the NCP5220 the DDQ and MCH regulators are interleaved (out of phase by 180 degrees) to reduce the peak AC input current. With careful PCB layout the NCP5220 can supply 20 A or more of current. It is very important to use wide traces or large copper shapes to carry current from the input node through the MOSFET switches, inductor and to the output filters and load. Reducing the length of high current nodes will reduce losses and reduce parasitic inductance. It is usually best to locate the input capacitors the MOSFET switches and the output inductor in close proximity to reduce DC losses, parasitic inductance losses and radiated EMI. The sensitive voltage feedback and compensation networks should be placed near the NCP5220 and away from the switch nodes and other noisy circuit elements. Placing compensation components near each other will minimize the loop area and further reduce noise susceptibility. Output Capacitor Selection Optional Boost Voltage Configuration Output capacitors are chosen by balancing the cost with the requirements for low output ripple voltage and transient voltage. Low ESR electrolytic capacitors can be effective at reducing ripple voltage at 250 kHz. Low ESR ceramic capacitors are most effective at reducing output voltage excursions caused by fast load steps of system memory and the memory controller. The charge pump circuit in Figure 19 can be used instead of boost voltage scheme of Figure 20. The advantage in Figure 19 is the elimination of the requirement for the Zener clamp. Input Capacitor Selection 12VATX TP2 5VDUAL TP2 D2 BAT54HT1 D1 BAT54HT1 D2 NCP5220 SW_DDQ 20 BG_DDQ 19 TG_DDQ 18 BOOT 17 5VDUAL 16 15 COMP_1P5 SLP_S3 14 TG_1P5 13 12 BG_1P5 11 BAT54HT1 5VDUAL 4 R2 4.7 1 Q2 3 NTD40N03 C4 100 nF L R3 1k R4 4.7 TP5 VDDQ 1 4 DPAK Q2 NTD40N03 3 C6 4.7 mF GND_1P5 Figure 19. Charge Pump Circuit at BOOT Pin http://onsemi.com 14 + C7 2200 mF + C25 2200 mF R15 2.5 VDDQ 1k VTT 1.25 VTT TP7 R16 1k VDDQ C12 4.7 mF R5 2.2 k + C8 10 nF C13 470 mF + C24 470 mF SGND R8 2k + C1 33 nF C10 R7 6.8 nF 20 k SGND R6 C9 8 100 nF R18 51 k http://onsemi.com 15 11 12 SGND 4 DPAK Q2 85N02R 3 1 1 D1 BAT54HT1 C18 R13 100 nF 8 R14 2k C6 4.7 mF VDDQ L3 1.8 mH R6 2.2 k C3 3300 mF SGND C17 R12 6.8 nF 20 k + Filtered 5VDUAL C22 10 mF D2 + + C25 2200 mF VCMH + C26 C14 + 2200 4.7 mF mF C7 2200 mF C15 2200 mF R15 1k C5 470 mF 12VATX TP2 ZENER BAT54HT1 MMSZ13T1 AGND to PGND L2 1.8 mH C4 22 nF 4 DPAK Q5 C16 40N03R 10 nF 3 DPAK Q4 3 40N03R 4 + C21 100 mF COMP_1P5 R10 4.7 R9 4.7 C11 220 nF R4 1 1 VREF = 800 mV AGND to PGND GND_1P5 BG_1P5 TG_1P5 13 COMP_1P5 15 SLP_S3 14 R3 1k DPAK Q1 3 85N02R 4 C23 10 mF Filtered 5VDUAL R2 2.2 1 + C2 3300 mF BOOT 17 5VDUAL 5VDUAL 16 TG_DDQ 18 BG_DDQ 19 SW_DDQ 20 L1 1 mF Figure 20. NCP5220 Typical Application Circuit 7 AGND SGND 8 FBVTT C20 9 SLP_S5 470 10 FB1P5 mF VDDQ 4 PGND 5 VTT 6 VDDQ 1 COMP VREF = 1.20 V 2 FBDDQ 3 SS U1 NCP5220 5VDUAL 5VDUAL TP2 R17 1k GND TP16 1.5 VMCH TP8 2.5 VDDQ TP5 NCP5220 NCP5220 Table 2. Bill of Material of NCP5220 Application Circuit Reference Design Description Value Qty Part Number Manufactur Q1, Q2 Power MOSFET N−Channel 24 V, 4.8 mW, 85 A 2 NTD85N02R ON Semiconductor Q3, Q4 Power MOSFET N−Channel 25 V, 12.6 mW, 40 A 2 NTD40N03R ON Semiconductor D1, D2 Rectifier Schottky Diode 30 V 2 BAT54HT1 ON Semiconductor 3−in−1 PWM Dual Buck and Linear Power Controller 1 NCP5220 ON Semiconductor Zener Diode 13 V, 0.5 W 1 MMSZ13T1 ON Semiconductor U1 Zener Controller L1 Toroidal Choke 1.0 mH, 25 A 1 T60−26(6T) L2, L3 Toroidal Choke 1.8 mH, 25 A 2 T50−26B(6T) C2, C3 Aluminum Electrolytic Capacitor 3300 mF, 6.3 V 2 EEUFJ0J332U Panasonic C5 Aluminum Electrolytic Capacitor 470 mF, 35 V 1 EEUFC1V471 Panasonic C21 Aluminum Electrolytic Capacitor 100 mF, 50 V 1 EEUFC1H101 Panasonic C20 Aluminum Electrolytic Capacitor 470 mF, 16 V 1 EEUFC1C471 Panasonic C13, C24 Aluminum Electrolytic Capacitor 470 mF, 10 V 2 EEUFC1A471 Panasonic C7, C25, C15, C26 Aluminum Electrolytic Capacitor 2200 mF, 6.3 V 4 EEUFC0J222S(H) Panasonic C11 Ceramic Capacitor 220 nF, 10 V 1 ECJ1VB1A224K Panasonic C6, C12, C14 Ceramic Capacitor 4.7 mF, 6.3 V 3 ECJHVB0J475M Panasonic C22, C23 Ceramic Capacitor 10 mF, 25 V 2 ECJ4YB1E106M Panasonic C4 Ceramic Capacitor 22 nF, 25 V 1 ECJ1VB1E223K Panasonic C10, C17 Ceramic Capacitor 6.8 nF, 50 V 2 ECJ1VB1H682K Panasonic C9, C18 Ceramic Capacitor 100 nF, 16 V 2 ECJ1VB1C104K Panasonic C8, C16 Ceramic Capacitor 10 nF, 50 V 2 ECJ1VB1H103K Panasonic C1 Ceramic Capacitor 33 nF, 25 V 1 ECJ1VB1E333K Panasonic R2 Resistor 2.2 W 1 R4 Resistor 1.0 W 1 R9, R10 Resistor 4.7 W 2 R3, R15, R16, R17 Resistor 1.0 kW 4 R7, R12 Resistor 20 kW 2 R6, R13 Resistor 8.2 W 2 R8, R14 Resistor 2.0 kW 2 R5, R11 Resistor 2.2 kW 2 R18 Resistor 51 kW 1 http://onsemi.com 16 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN20, 6x5, 0.5P CASE 505AB ISSUE C 20 DATE 23 MAY 2012 1 SCALE 2:1 A D NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINALS AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. FOR DEVICE OPN CONTAINING W OPTION, DETAIL B ALTERNATE CONSTRUCTION IS NOT APPLICABLE. B PIN 1 LOCATION E 2X 0.15 C 2X DIM A A1 A2 A3 b D D2 E E2 e K L TOP VIEW 0.15 C 0.10 C A2 A 0.08 C A1 SIDE VIEW (A3) C SEATING PLANE D2 20X GENERIC MARKING DIAGRAM* e L 20X MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.65 0.75 0.20 REF 0.20 0.30 6.00 BSC 3.98 4.28 5.00 BSC 2.98 3.28 0.50 BSC 0.20 −−− 0.50 0.60 1 10 XXXXXXXXXX XXXXXXXXXX AWLYYWWG G E2 K 20 11 20X XXXXX A WL YY WW G b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW RECOMMENDED SOLDERING FOOTPRINT* (Note: Microdot may be in either location) 20X *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 0.78 4.24 3.24 PACKAGE OUTLINE = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package 5.30 1 20X 0.50 PITCH 0.35 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON13117D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 20 PIN DFN, 6X5 MM, 0.5 MM PITCH PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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