NCP5380AMNR2G

NCP5380, NCP5380A 7-Bit, Programmable, Single-Phase, Synchronous Buck Switching Regulator Controller http://onsemi.com General Description MARKING DIAGRAM 1 1 NCP5380 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb Free Package (Note: Microdot may be in either location) PIN CONFIGURATION Features • Single−chip Solution • Fully Compatible with the Intel VR11 CPU Chipset Voltage Regulator Specifications • Integrated MOSFET Drivers • ±8 mV Worst−case Differentially Sensed Core Voltage Error over Temperature PWRGD IMON N/C FBRTN FB COMP GND ILIM • • • • • • • • Applications 1 VCC BST DRVH SW PVCC DRVL PGND GND NCP5380 (Top View) IREF RPM RT RAMP LLINE CSREF CSFB CSCOMP • Automatic Power−saving Modes Maximize Efficiency During Light Load Operation Soft Transient Control Reduces Inrush Current and Audio Noise Independent Current Limit and Load Line Setting Inputs for Additional Design Flexibility Built−in Power−good Masking Supports Voltage Identification (VID) OTF Transients 7−bit, Digitally Programmable DAC Short−circuit Protection with Programmable Latchoff Delay Current Monitor Output Signal 32−lead QFN This is a Pb−Free Device NCP5380 AWLYYWWG G 32 QFN32, 5x5 CASE 488AM MN SUFFIX EN VID1 VID2 VID3 VID4 VID5 VID6 VID7 The NCP5380/A is a highly efficient, single−phase, synchronous buck switching regulator controller. With its integrated drivers, the NCP5380/A is optimized for converting the silver box voltage to the supply voltage required by high performance Intel chipsets. An internal 7−bit DAC is used to read a VID code directly from the chipset. The NCP5380/A uses a multimode architecture. It provides programmable switching frequency that can be optimized for efficiency depending on the output current requirement. In addition, the NCP5380/A includes a programmable load line slope function to adjust the output voltage as a function of the load current so that the core voltage is always optimally positioned for a load transient. The NCP5380/A also provides accurate and reliable current overload protection and a delayed power−good output. The IC supports On−The−Fly (OTF) output voltage changes requested by the chipset. The NCP5380 is specified over the temperature range of 0°C to 85°C, while the NCP5380A extends the temperature range to −40°C to 100°C. The NCP5380/A is available in a 32−lead QFN. ORDERING INFORMATION Device Package Shipping† NCP5380MNR2G QFN−32 (Pb−Free) 5000 / Tape & Reel NCP5380AMNR2G QFN−32 (Pb−Free) 5000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. • Desktop Power Supplies for Next−generation Intel Chipsets © Semiconductor Components Industries, LLC, 2011 April, 2011 − Rev. 3 1 Publication Order Number: NCP5380/D NCP5380, NCP5380A VID6 VID5 VID4 VID3 VID2 VID1 VID0 VR_ON PWRGD R2 10 V5S C6 1m Q1 4 Q1 32 1 VDC 10 mF x 7 + C30 220mF 2.5V 10 mF x 7 +C22 + C23 220m 220m 2.5V 2.5V C41 VOUT C33 C1 C2 C3 C4 10m 10m 10m 10m 25V 25V 25V 25V 100 kW RTH1 8% NTC L1 560 nH/0.8 mOhm DNL CSNB RSNB DNL 5 6 7 8 5 6 7 8 4.7m C8 4 32 1 4 32 1 5 6 7 8 5 6 7 8 4 32 1 Q4 RPH Q3 RCS1 RCS2 100k C39 C47 Figure 1. Application Schematic IMON RMON 4.53k 10 54.9k 88.7k 24 VCC CBST 0 1m 23 22 RBST 21 20 19 18 17 AGND 33 AGND CCS2 CCS1 PWRGD BST IMON DRVH NC SW FBRTN U1 PVCC FB NCP5380 DRVL COMP PGND AGND RT 390k R55 2.2n R24 DNL C26 1n 2.7n 0 R23 2 VSSSense RA 20.0k RRAMP 604k RREF RRPM 80.6k 200k RLIM 10k 1 C28 CMON CA3 R22 2 R19 1n 20 0.01m 866 3 0.1m 4 1.00k 5 6 CA RB VCCSense 7 CFB 470p CB DNL 8 22p ILIM JP1 SHORTPIN Connect Power Ground to Controller Ground under the controller VDC 1.00k R12 C27 1n http://onsemi.com 32 31 30 29 28 27 26 25 EN VID1 VID2 VID3 VID4 VID5 VID6 VID7 IREF RPM RT RAMP LLINE CSREF CSFB CSCOMP 9 10 11 12 13 14 15 16 NCP5380, NCP5380A GND EN VCC RPM REF + LLINE + S + DAC + 200 mV CSREF DAC − 300 mV CSREF _ 1.55V OCP Shutdown Delay − + Current Limit Circuit PWRGD Start Up Delay IMON + CSREF − CSFB CSCOMP Soft Transient Delay ILIM Delay Disable Precision Reference REF IREF VID1 VID3 VID2 VID4 DAC VID5 GND Soft Start and Soft Transient Control VID DAC VID7 VID6 DRVL OVP Current Monitor N/C FBRTN SW PGND − + PWRGD Open Drain PWRGD DRVH MOSFET Driver VEA − + S Oscillator − + FB RAMP BST UVLO Shutdown and Bias COMP RT Figure 2. Functional Block Diagram ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = 112.5 mV, VVID = 1.25 V, TA = 0°C to 85°C (NCP5380), TA = −40°C to 100°C (NCP5380A), unless otherwise noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. Parameter Symbol Conditions Min Typ Max Unit VOLTAGE CONTROL VOLTAGE ERROR AMPLIFIER (VEAMP) FB, LLINE Voltage Range (Note 2) VFB, VLLINE Relative to CSREF = VDAC −200 +200 mV FB, LLINE Offset Voltage (Note 2) VOSVEA Relative to CSREF = VDAC −0.5 +0.5 mV IFB −1.0 +1.0 mA LLINE Bias Current ILLINE −10 +10 nA LLINE Positioning Accuracy VFB − VDAC Measured on FB relative to nominal VDAC −10°C to 100°C −40°C to 100°C −78 −77 COMP Voltage Range VCOMP Voltage range of interest 0.85 FB −80 −80 1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2. Guaranteed by design or bench characterization, not production tested. http://onsemi.com 3 −82 −83 4.0 mV V NCP5380, NCP5380A ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = 112.5 mV, VVID = 1.25 V, TA = 0°C to 85°C (NCP5380), TA = −40°C to 100°C (NCP5380A), unless otherwise noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. Parameter Symbol Conditions Min Typ Max Unit VOLTAGE CONTROL VOLTAGE ERROR AMPLIFIER (VEAMP) COMP Current COMP Slew Rate Gain Bandwidth (Note 2) ICOMP SRCOMP GBW COMP = 2.0 V, CSREF = VDAC FB forced 200 mV below CSREF FB forced 200 mV above CSREF −600 2.0 CCOMP = 10 pF, CSREF = VDAC, Open loop configuration FB forced 200 mV below CSREF FB forced 200 mV above CSREF mA mA V/ms 15 −20 Non−inverting unit gain configuration, RFB = 1 kW 20 MHz VID DAC VOLTAGE REFERENCE VDAC Voltage Range (Note 2) VDAC Accuracy See VID table VFB − VDAC 0 Measured on FB (includes offset), relative to nominal VDAC VDAC = 0.3 V to 1.2 V, −10°C to 100°C VDAC = 0.3 V to 1.2 V, −40°C to 100°C VDAC = 1.2125 V to 1.5 V, −40°C to 100°C VDAC Differential Nonlinearity (Note 2) VDAC Line Regulation ΔVFB VDAC Slew Rate FBRTN Current 1.6 V mV −7.0 −9.0 −9.0 +7.0 +9.0 +9.0 −1 +1 VCC = 4.75 V to 5.25 V Soft−start Arbitrary VID step LSB 0.05 % 0.0625 1 LSB/ ms IFBRTN 70 Boot Voltage Vboot 1.1 Boot Voltage Timer tboot 200 mA BOOT VOLTAGE 50 V 70 100 ms 0.5 0.3 V VID DAC INPUTS Input Low Voltage VIL VID(x) Input High Voltage VIH VID(x) Input Current IIN(VID) VID Transition Delay Time (Note 2) 0.7 Sink current VID Code Change to FB Change 400 RIREF = 80 kW to Set IREF = 20 mA 1.55 0.5 V 1 mA ns REFERENCE CURRENT IREF Voltage VIREF 1.6 1.65 mA 3 MHz OSCILLATOR Frequency Range (Note 2) Oscillator Frequency fOSC FOSC 0.3 TA = +25°C, VVID = 1.20 V, Clocked PWM Mode kHz RT = 60 kW 900 1200 1500 RT = 120 kW 465 600 725 RT = 180 kW 300 400 500 VRT VVID = 1.6 V 1.08 1.2 1.35 RPM Output Current IRPM VVID = 1.250 V, RT = 500 kW RAMP Input Voltage VRAMP 0.9 1.0 RAMP Input Current Range IRAMP RT Output Voltage RAMP Input Current in Shutdown EN = high EN = low or in UVLO, RAMP = 19 V −5 4 mA 1.1 V 1 100 mA −0.5 +0.5 mA 1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2. Guaranteed by design or bench characterization, not production tested. http://onsemi.com V NCP5380, NCP5380A ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = 112.5 mV, VVID = 1.25 V, TA = 0°C to 85°C (NCP5380), TA = −40°C to 100°C (NCP5380A), unless otherwise noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. Parameter Symbol Conditions Min Typ Max Unit −1.4 +1.4 mV −50 +50 nA CURRENT SENSE AMPLIFIER Offset Voltage VOS(CSA CSFB − CSREF ) Input Bias Current IBIAS(CS FB) Gain Bandwidth Product (Note 2) GBW(CS 20 MHz 10 V/ms A) Slew Rate (Note 2) CCSCOMP = 10 pF Input Common−Mode Range (Note 2) CSFB and CSREF Output Voltage Range VCSCOM 0 2 V 0.05 2 V P Output Current ICSCOMP Source current Sink current −650 mA 1 mA SWITCH AMPLIFIER Common−Mode Range (Note 2) Input Resistance Zero Current Switching Threshold VSW −400 RSW 0.8 VZCS(SW 1.5 +200 mV 2.0 kW DCM Mode −6 mV SW falling 700 ns ) DCM Minimum Off Time Masking tOFFMAS K CURRENT LIMIT COMPARATOR ILIM Voltage VILIM− VCSCOM RILIMIT = 5 kW, VCSREF − VCSCOMP = 100 mV −70 −100 −130 mV RILIMIT = 5 kW, VCSREF − VCSCOMP = 0 mV −1 0 1 mV P VILIM− VCSCOM P Current Limit Latch Off Delay From OCP Event to PWRGD De−assertion 8 ms From FB = 0V to FB = Vboot 1.4 ms From EN POS Edge to FB = 50 mV 200 ms SOFT−START Soft−Start Time tss Soft−Start Delay SOFT TRANSIENT CONTROL Output Voltage Positive Slew Rate 10 12.5 15 mV⁄ms Output Voltage Negative Slew Rate −10 −12.5 −15 mV⁄ms Extended PWRGD Masking Comparator Threshold VTH(ST) |ST − VVID|, ST falling 150 mV SYSTEM LOGIC INPUTS Input Voltage VEN Refers to driving signal level Logic low, Isink = 1 mA Logic high, Isource = −5 mA Input Current IEN 0.3 0.7 V V VEN,VID[1:7] = 0 V 10 nA 0.2 V < VEN,VID[1:7] ≤ VCC 1 mA 1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2. Guaranteed by design or bench characterization, not production tested. http://onsemi.com 5 NCP5380, NCP5380A ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = 112.5 mV, VVID = 1.25 V, TA = 0°C to 85°C (NCP5380), TA = −40°C to 100°C (NCP5380A), unless otherwise noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. Parameter Symbol Conditions Min Typ Max Unit −360 −300 −240 mV 150 200 250 mV 1.5 1.55 1.6 V −350 −300 POWER GOOD CSREF Undervoltage Threshold VUV(CSR For VID = 1.2 V EF) CSREF Overvoltage Threshold VOV(CSR EF) CSREF Crowbar (Overvoltage Protection) Threshold VCB(CSR FBRTN = 112.5 mV CSREF Reverse Voltage Detection Threshold VRVP(CS CSREF falling REF) CSREF rising −75 −5 mV PWRGD Output Low Voltage VOL(PWR ISINK(PWRGD) = 4 mA 75 100 mV 0.5 mA EF) mV GD) PWRGD Output Leakage Current VPWRDG = 3.3 V PWRGD Masking Time PWRGD delay Time 100 tPWRGD ms 6 10 11 ms 11 mA CURRENT MONITOR IMON Output Current IIMON VCSREF − VCSCOMP = 100 mV 9 10 IMON Output Current IIMON VCSREF − VCSCOMP = 10 mV 0.9 1 IMON Clamp VIMON 1.0 1.1 mA 1.15 V HIGH−SIDE MOSFET DRIVER Output Resistance, Sourcing Current BST − SW = 4.6 V 1.6 3.3 W Output Resistance, Sinking Current BST − SW = 4.6 V 1.3 2.8 W Transition Times Dead Delay Times trDRVH, BST − SW = 4.6 V, CL = 3 nF 15 35 ns tfDRVH BST − SW = 4.6 V, CL = 3 nF 13 31 ns BST − SW = 4.6 V 20 45 ns 5 15 mA tpdhDRV H BST Quiescent Current EN = low, shutdown EN = high, no switching 200 mA LOW−SIDE MOSFET DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times Propagation Delay Times 1.4 3.0 W 1 2.7 W trDRVL CL = 3 nF 15 35 ns tfDRVL CL = 3 nF 14 35 ns tpdhDRV CL = 3 nF 24 40 ns 250 450 ns L SW Transition Timeout Zero−Crossing Threshold PVCC Quiescent Current tTO(SW) BST − SW = 4.6 V 150 VZC 1.5 EN = low, shutdown 14 EN = high, no switching 450 V 50 mA mA BOOTSTRAP RECTIFIER Output Resistance 4.0 8.0 11 W SOFT STOP CSREF Resistance to GND EN = low or latch off 70 1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2. Guaranteed by design or bench characterization, not production tested. http://onsemi.com 6 W NCP5380, NCP5380A ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = 112.5 mV, VVID = 1.25 V, TA = 0°C to 85°C (NCP5380), TA = −40°C to 100°C (NCP5380A), unless otherwise noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. Parameter Symbol Conditions Min Typ Max Unit 4.5 5.5 4.2 10 mA SUPPLY Supply Voltage Range (Note 2) VCC Normal mode Supply Current V EN = 0 V 60 200 mA VCC OK Threshold Voltage VCCOK VCC rising 4.4 4.5 V VCC UVLO Threshold Voltage VCCUVL VCC falling 4.0 4.2 V 250 mV O UVLO Hysteresis (Note 2) 1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2. Guaranteed by design or bench characterization, not production tested. http://onsemi.com 7 NCP5380, NCP5380A Timing Diagram Timing is referenced to the 90% and 10% points, unless otherwise noted. IN tpdlDRVL tfDRVL trDRVL tpdlDRVH DRVL tpdhDRVH trDRVH VTH DRVH (WITH RESPECT TO SW) tfDRVH VTH tpdhDRVL SW Figure 3. Timing Diagram ABSOLUTE MAXIMUM RATING Parameter Rating VCC −0.3 V to +6.0 V FBRTN, PGND −0.3 V to +0.3 V BST DC −0.3 V to +28 V t < 200 ns −0.3 V to +33 V BST to SW DRVH, SW −0.3 V to +6.0 V DC −5.0 V to +21 V t < 200 ns −10 V to +26 V DRVH to SW DRVL to PGND RAMP (in Shutdown) −0.3 V to +6.0 V DC −0.3 V to +6.0 V t < 200 ns −5.0 V to +6.0 V DC −0.3 V to +21 V t < 200 ns −0.3 V to +26 V All Other Inputs and Outputs −0.3 V to +6.0 V Storage Temperature −65°C to +150°C Operating Ambient Temperature Range −40°C to 100°C Operating Junction Temperature 125°C Thermal Impedance (θJA) 2−Layer Board Lead Temperature 32.6°C/W Soldering (10 sec) 300°C Infrared (15 sec) 260°C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 8 NCP5380, NCP5380A Pin Function Descriptions Pin No. Mnemonic 1 PWRGD Description 2 IMON 3 N/C 4 FBRTN 5 FB 6 COMP 7 GND Analog and digital signal ground. 8 ILIM Current Limit Set pin. Connect a resistor between ILIM and CSCOMP to the current limit threshold. 9 IREF This pin sets the internal bias currents. A 100 kW is connected from IREF to ground. 10 RPM RPM Mode Timing Control Input. A resistor is connected from RPM to ground sets the RPM mode turn−on threshold voltage. 11 RT PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM oscillator frequency. 12 RAMP PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin sets the slope of the internal PWM stabilizing ramp. 13 LLINE Load Line Programming Input. The center point of a resistor divider connected between CSREF and CSCOMP tied to this pin sets the load line slope. 14 CSREF Current Sense Reference Input. This pin must be connected to the opposite side of the output inductor. 15 CSFB Noninverting Input of the Current Sense Amplifier. The combination of a resistor from the switch node to this pin and the feedback network from this pin to the CSCOMP pin sets the gain of the current sense amplifier. 16 CSCOMP 17 GND 18 PGND Low−Side Driver Power Ground. This pin should be connected close to the source of the lower MOSFET(s). 19 DRVL Low−Side Gate Drive Output. 20 PVCC Power Supply Input/Output of Low−Side Gate Driver. 21 SW 22 DRVH 23 BST High−Side Bootstrap Supply. A capacitor from this pin to SW holds the bootstrapped voltage while the high−side MOSFET is on. 24 VCC Power Supply Input/Output of the Controller. 25 to 31 VID7 to VID1 32 EN Flag PGND Power−Good Output. Open−drain output. A low logic state means that the output voltage is outside of the VID DAC defined range. Current Monitor Output. This pin sources current proportional to the output load current. A resistor connected to VSS Sense sets the current monitor gain. Feedback Return Input/Output. This pin remotely senses the output voltage. It is also used as the ground return for the VID DAC and the voltage error amplifier blocks. It is also used to adjust the no−load offset. Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier. Voltage Error Amplifier Output and Frequency Compensation Point. Current Sense Amplifier Output. Analog and Digital Signal Ground. Current Return For High−Side Gate Drive. High−Side Gate Drive Output. Voltage Identification DAC Inputs. A 7−bit word (the VID code) programs the DAC output voltage, the reference voltage of the voltage error amplifier without a load (see the VID code table, Table 4). In normal operation mode, the VID DAC output programs the output voltage to a value within the 0 V to 1.6 V range (with FBRTN = 112.5 mV). The input is actively pulled down. Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, and pulls PWRGD low. High current power supply return via metal pad (flag) underneath package. Connect to pin 7. http://onsemi.com 9 NCP5380, NCP5380A Typical Performance Characteristics VVID = 1.5 V, TA = 20°C to 100°C, unless otherwise noted. Output Voltage Output Voltage Switch Node Switch Node Inductor Current Inductor Current Low Side Gate Drive Low Side Gate Drive Figure 4. DCM Waveforms, 1 A Load Current Figure 5. CCM Waveforms, 10 A Load Current Output Voltage Output Voltage Switch Node Switch Node Load Current Load Current Figure 6. Load Transient, 2 A to 10 A, VIN = 19 V Figure 7. Load Transient, 2 A to 10 A, VIN = 19 V OUTPUT VOLTAGE Output Voltage VID 0 Figure 8. VID on the Fly, 1.25 V to 0.825 V Figure 9. Output Ripple, 15 A Load, CX = 470 mF, CZ = 44 mF http://onsemi.com 10 NCP5380, NCP5380A Theory of Operation Operation Modes The NCP5380/A is a ramp−pulse−modulated (RPM) controller for synchronous buck power supply. The internal 7−bit VID DAC conforms to the Intel VR11 specifications. The NCP5380/A is a stable, high performance architecture that includes • High speed response at the lowest possible switching frequency and minimal count of output decoupling capacitors • Minimized thermal switching losses due to lower frequency operation • High accuracy load line regulation • High power conversion efficiency with a light load by automatically switching to DCM operation VRMP IR = AR X IRAMP Flip−Flop + S + 5.0 V Q VCC Gate Driver RD BST BST DRVH CR 1.0 V The NCP5380/A runs in RPM mode for the purpose of fast transient response and high light load efficiency. During the following transients, the NCP5380/A runs in PWM mode: • Soft−Start • Soft transient: the period of 100 ms following any VID change • Current overload 400 ns Q S RI DRVH IN SW DCM DRVL Flip−Flop DRVL Q Q LOAD RD R2 + 30 mV − S + COMP + RA CFB CA VDC + VCS FB R1 + + + − L SW FBRTN R2 1.0 V − S R1 CSREF + - + LLINE CSFB CSCOMP RCS CB CCS RFB Figure 10. RPM Mode Operation http://onsemi.com 11 RPH NCP5380, NCP5380A 5.0 V VCC Gate Driver IR = AR X IRAMP BST DRVH Flip−Flop Clock Oscillator S IN SW DRVL + - CR Q RD BST RI DRVH L SW DRVL LOAD VCC AD + + − 0.2 V S + - Ramp COMP + FBRTN CA CFB VDC + VCS FB RA CSREF − S + - + LLINE CSFB CSCOMP RCS CB RPH CCS RFB Figure 11. PWM Mode Operation Setting Switch Frequency Master Clock Frequency in PWM Mode mode, the combination of the VID DAC and error amplifier maintain the output voltage for a worst−case scenario within ±8 mV of the full operating output voltage and temperature range. The output voltage is sensed between the FB and FBRTN pins. FB should be connected through a resistor to the positive regulation point. FBRTN should be connected directly to the negative remote sensing point. The internal VID DAC and precision voltage reference are referenced to FBRTN thus allowing no load offset to be set using this pin. When the NCP5380/A runs in PWM, the clock frequency is set by an external resistor connected from the RT pin to GND. The frequency varies with the VID voltage: the lower the VID voltage, the lower the clock frequency. The variation of clock frequency with VID voltage maintains constant output ripple and improves power conversion efficiency at lower VID voltages. Switching Frequency in RPM Mode When the NCP5380/A operates in RPM mode, its switching frequency is controlled by the ripple voltage on the COMP pin. Each time the COMP pin voltage exceeds the RPM pin voltage threshold level determined by the VID voltage and the external resistor connected between RPM and ground, an internal ramp signal is started and DRVH is driven high. The slew rate of the internal ramp is programmed by the current entering the RAMP pin. One−third of the RAMP current charges an internal ramp capacitor (5 pF typical) and creates a ramp. When the internal ramp signal intercepts the COMP voltage, the DRVH pin is reset low. In continuous current mode, the switching frequency of RPM operation is almost constant. While in discontinuous current conduction mode, the switching frequency is reduced as a function of the load current. Output Current Sensing The NCP5380/A includes a dedicated current sense amplifier (CSA) to monitor the total output current of the converter for proper voltage positioning vs. load current and for overcurrent detection. Sensing the current delivered to the load is an inherently more accurate method than detecting peak current or sampling the current across a sense element, such as the low−side MOSFET. The current sense amplifier can be configured several ways, depending on system optimization objectives, and the current information can be obtained by • Output inductor ESR sensing without the use of a thermistor for the lowest cost • Output inductor ESR sensing with the use of a thermistor that tracks inductor temperature to improve accuracy • Discrete resistor sensing for the highest accuracy At the positive input of the CSA, the CSREF pin is connected to the output voltage. At the negative input (that Differential Sensing of Output Voltage The NCP5380/A combines differential sensing with a high accuracy VID DAC, referenced by a precision band gap source and a low offset error amplifier, In steady−state http://onsemi.com 12 NCP5380, NCP5380A is, the CSFB pin of the CSA), signals from the sensing element (in the case of inductor DCR sensing, signals from the switch node side of the output inductors) are connected with a resistor. The feedback resistor between the CSCOMP and CSFB pins sets the gain of the current sense amplifier, and a filter capacitor is placed in parallel with this resistor. The current information is then given as the voltage difference between the CSCOMP and CSREF pins. This signal is used internally as a differential input for the current limit comparator. An additional resistor divider connected between the CSCOMP and CSREF pins with the midpoint connected to the LLINE pin can be used to set the load line. The current information to set the load line is then given as the voltage difference between the LLINE and CSREF pins. This configuration allows the load line slope to be set independent from the current limit threshold. If the current limit threshold and load line do not have to be set independently, the resistor divider between the CSCOMP and CSREF pins can be omitted and the CSCOMP pin can be connected directly to LLINE. To disable voltage positioning entirely (that is, to set no load line), LLINE should be tied to CSREF. To provide the best accuracy for current sensing, the CSA has a low offset input voltage and the sensing gain is set by an external resistor ratio. output that can be pulled up through an external resistor to a voltage rail − not necessarily the same VCC voltage rail that is running the controller. A logic high level indicates that the output voltage is within the voltage limits defined by a range around the VID voltage setting. PWRGD goes low when the output voltage is outside of this range. Following the CPU specification, the PWRGD range is defined to be 300 mV less than and 200 mV greater than the actual VID DAC output voltage. To prevent a false alarm, the power−good circuit is masked during any VID change and during soft−start. The duration of the PWRGD mask is set to approximately 100 ms by an internal timer. In addition, for a VID change from high to low, there is an additional period of PWRGD masking before the internal DAC voltage drops within 200 mV of the new lower VID DAC output voltage, as shown in Figure 12. Active Impedance Control Mode Power−Up Sequence and Soft−Start VID SIGNAL CHANGE Internal DAC VOLTAGE 200mV PWRGD MASK 100 ms 100 μs 100 ms 100μs Figure 12. PWRGD Masking for VID Change To control the dynamic output voltage droop as a function of the output current, the signal that is proportional to the total output current, converted from the voltage difference between LLINE and CSREF, can be scaled to be equal to the required droop voltage. This droop voltage is calculated by multiplying the droop impedance of the regulator by the output current. This value is used as the control voltage of the PWM regulator. The droop voltage is subtracted from the DAC reference output voltage, and the resulting voltage is used as the voltage positioning setpoint. The arrangement results in an enhanced feedforward response. The power−on ramp−up time of the output voltage is set internally. The power−up sequence is illustrated in Figure 13. VCC = 5.0 V EN VBOOT = 1.0 V DAC AND VCORE tBOOT Voltage Control Mode Figure 13. Power−Up Sequence for CPU A high−gain bandwidth error amplifier is used for the voltage mode control loop. The noninverting input voltage is set via the 7−bit VID DAC. The noninverting input voltage is offset by the droop voltage as a function of current, commonly known as active voltage positioning. The output of the error amplifier is the COMP pin, which sets the termination voltage of the internal PWM ramps. At the negative input, the FB pin is tied to the output sense location using RB, a resistor for sensing and controlling the output voltage at the remote sensing point. The main loop compensation is incorporated in the feedback network connected between the FB and COMP pins. VID Change and Soft Transient When a VID input changes, the NCP5380/A detects the change but ignores new code for a minimum of 400 ns. This delay is required to prevent the device from reacting to digital signal skew while the 7−bit VID input code is in transition. Additionally, the VID change triggers a PWRGD masking timer to prevent a PWRGD failure. Each VID change resets and retriggers the internal PWRGD masking timer. The NCP5380/A provides a soft transient function to reduce inrush current during VID transitions. Reducing the inrush current helps decrease the acoustic noise generated by the MLCC input capacitors and inductors. The soft transient feature is implemented internally. When a new VID code is detected, the NCP5380/A steps Power−Good Monitoring The power−good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open−drain http://onsemi.com 13 NCP5380, NCP5380A Light Load RPM DCM Operation sequentially through each VID voltage to the final VID voltage. The NCP5380/A operates in RPM mode. With higher loads, the NCP5380/A operates in continuous conduction mode (CCM), and the upper and lower MOSFETs run synchronously and in complementary phase. See Figure 15 for the typical waveforms of the NCP5380/A running in CCM with a 7 A load current. Current Limit, Short−Circuit, and Latchoff Protection The NCP5380/A has an adjustable current limit set by the RCLIM resistor. The NCP5380/A compares a programmable current−limit set point to the voltage from the output of the current−sense amplifier. The level of current limit is set with the resistor from the ILIM pin to CSCOMP. During operation, the voltage on ILIM is equal to the voltage on CSREF. The current through the external resistor connected between ILIM and CSCOMP is then compared to the internal current limit current Icl. If the current generated through this resistor into the ILIM pin(Ilim) exceeds the internal current−limit threshold current (Icl), the internal current−limit amplifier controls the internal COMP voltage to maintain the average output current at the limit. Normally, the NCP5380/A operates in RPM mode. During a current overload, the NCP5380/A switches to PWM mode. With low impedance loads, the NCP5380/A operates in a constant current mode to ensure that the external MOSFETs and inductor function properly and to protect the CPU. With a low constant impedance load, the output voltage decreases to supply only the set current limit. If the output voltage drops below the power−good limit, the PWRGD signal transitions. After the PWRGD single transitions, internal waits 7 ms before latching off the NCP5380/A. Figure 14 shows how the NCP5380/A reacts to a current overload. OUTPUT VOLTAGE 20mV/DIV 4 INDUCTOR CURRENT 5A/DIV 2 SWITCH NODE 5V/DIV 3 LOW−SIDE GATE DRIVE 5V/DIV 1 1ms/DIV Figure 15. Single−Phase Waveforms in CCM With lighter loads, the NCP5380/A enters discontinuous conduction mode (DCM). Figure 16 shows a typical single-phase buck with one upper FET, one lower FET, an output inductor, an output capacitor, and a load resistor. Figure 17 shows the path of the inductor current with the upper FET on and the lower FET off. In Figure 18 the high-side FET is off and the low-side FET is on. In CCM, if one FET is on, its complementary FET must be off; however, in DCM, both high- and low-side FETs are off and no current flows into the inductor (see Figure 19). Figure 20 shows the inductor current and switch node voltage in DCM. In DCM with a light load, the NCP5380/A monitors the switch node voltage to determine when to turn off the low-side FET. Figure 20 shows a typical waveform in DCM with a 1 A load current. Between t1 and t2, the inductor current ramps down. The current flows through the source drain of the low-side FET and creates a voltage drop across the FET with a slightly negative switch node. As the inductor current ramps down to 0 A, the switch voltage approaches 0 V, as seen just before t2. When the switch voltage is approximately −6 mV, the low-side FET is turned off. Figure 20 shows a small, dampened ringing at t2. This is caused by the LC created from capacitance on the switch node, including the CDS of the FETs and the output inductor. This ringing is normal. The NCP5380/A automatically goes into DCM with a light load. Figure 21 shows the typical DCM waveform of the NCP5380/A with a 1 A load current. As the load increases, the NCP5380/A enters into CCM. In DCM, frequency decreases with load current, and switching frequency is a function of the inductor, load current, input voltage, and output voltage. Figure 14. Current Overload The latchoff function can be reset either by removing and reapplying VCC or by briefly pulling the EN pin low. During startup, when the output voltage is below 200 mV, a secondary current limit is active. This is necessary because the voltage swing of CSCOMP cannot extend below ground. This secondary current limit clamp controls the minimum internal COMP voltage to the PWM comparators to 1.5 V. This limits the voltage drop across the low−side MOSFETs through the current balance circuitry. http://onsemi.com 14 NCP5380, NCP5380A Q1 DRVH SWITCH NODE OUTPUT VOLTAGE L Inductor Current Q2 + INPUT − VOLTAGE C DRVL LOAD Figure 16. Buck Topology Switch Node Voltage ON L + − OFF C LOAD t0 t1 t2 t3 t4 Figure 20. Inductor Current and Switch Node in DCM Figure 17. Buck Topology Inductor Current During t0 and t1 OUTPUT VOLTAGE 4 20mV/DIV OFF SWITCH NODE 5V/DIV L + − 2 ON C LOAD INDUCTOR CURRENT 3 Figure 18. Buck Topology Inductor Current During t1 and t2 OFF LOW−SIDE GATE DRIVE 5V/DIV 2ms/DIV Figure 21. Single−Phase Waveforms in DCM with 1 A Load Current L Output Crowbar + − OFF 5A/DIV 1 C To protect the load and output components of the supply, the DRVL output is driven high (turning the low−side MOSFETs on) and DRVH is driven low (turning the high−side MOSFETs off) when the output voltage exceeds the CPU OVP threshold. Turning on the low−side MOSFETs forces the output capacitor to discharge and the current to reverse due to current build up in the inductors. If the output overvoltage is due to a drain−source short of the high−side MOSFET, turning on the low−side MOSFET results in a crowbar across the input voltage rail. The crowbar action blows the fuse of the input rail, breaking the circuit and thus protecting the CPU chipset from destruction. When the OVP feature is triggered, the NCP5380 is latched off. The latchoff function can be reset by removing and reapplying VCC to the NCP5380/A or by briefly pulling the EN pin low. LOAD Figure 19. Buck Topology Inductor Current During t2 and t3 http://onsemi.com 15 NCP5380, NCP5380A Reverse Voltage Protection voltage is less than the VCCUVLO threshold or the EN pin is logic low, the NCP5380/A shuts off. In shutdown mode, the controller holds DRVH and DRVL low, shorts the capacitors of the SS and PGDELAY pins to ground, and drives PWRGD to low. The user must adhere to proper power−supply sequencing during startup and shutdown of the NCP5380/A. All input pins must be at ground prior to removing or applying VCC, and all output pins should be left in high impedance state while VCC is off. Very large reverse current in inductors can cause negative output voltage, which is harmful to the chipset and other output components. The NCP5380/A provides a reverse voltage protection (RVP) function without additional system cost. The output voltage is monitored through the CSREF pin. When the CSREF pin voltage drops to less than −190 mV, the NCP5380/A triggers the RVP function by setting both DRVH and DRVL low, thus turning off all MOSFETs. The reverse inductor currents can be quickly reset to 0 by discharging the built−up energy in the inductor into the input dc voltage source via the forward−biased body diode of the high−side MOSFETs. The RVP function is terminated when the CSREF pin voltage returns to greater than −150 mV. Sometimes the crowbar feature inadvertently results in negative voltage because turning on the low−side MOSFETs results in a very large reverse inductor current. To prevent damage to the chipset caused from negative voltage, the NCP5380/A maintains its RVP monitoring function even after OVP latchoff. During OVP latchoff, if the CSREF pin voltage drops to less than −190 mV, the low−side MOSFETs is turned off by setting DRVL low. DRVL will be set high again when the CSREF voltage recovers to greater than +50 mV. Figure 22 shows the reverse voltage protection function of the NCP5380/A. The CSREF pin is disconnected from the output voltage and pulled negative. As the CSREF pin drops to less than −190 mV, the low−side and high−side FETs turn off. Output Current Monitor The NCP5380/A includes an output current monitor function. The IMON pin outputs an accurate current that is directly proportional to the output current. This current is then run through a parallel RC connected from the IMON pin to the FBRTN pin to generate an accurately scaled and filtered voltage. The maximum voltage on IMON is internally clamoed by the NCP5380/A at 1.15 V. Output Voltage No-load Offset Adjustment The NCP5380/A output voltage can be offset from the nominal VID settings by adjusting one resistor value. The following figure shows the components used for setting the no-load output offset voltage. VCC (pin 24) Rofs FBRTN (pin 4) 0.1 mF −Vout Return 3 CSREF Figure 23. Setting the Output Offset Voltage The nominal VID table for the NCP5380/A is based on the voltage at FBRTN being 112.5 mV (Rofs nominal of 866 ohms). If it is desired to adjust the no-load output voltage to be above or below VID, then the value of Rofs can be changed. If we define the no-load offset from VID as Vnlofs, then the following can be used to determine the value for Rofs (given VCC = 5 V); PWRGD 2 DRVH 4 1 20 DRVL Figure 22. NCP5380 RVP Function R ofs + Output Enable and UVLO For the NCP5380/A to begin switching, the VCC supply voltage to the controller must be greater than the VCCOK threshold and the EN pin must be driven high. If the VCC ǒ Ǔ 5 *1 0.1125 ) V nlofs 20 NOTE: The 20 ohm resistor and 0.1 mF capacitor nominal values are fixed based on the design of the NCP5380/A so only Rofs should be adjusted for changing the no−load offset. http://onsemi.com 16 NCP5380, NCP5380A VID Codes (FBRTN = 112.5 mV) VID7 VID6 VID5 VID4 VID3 VID2 VID1 Output 0 0 0 0 0 0 1 1.6000 0 0 0 0 0 1 0 1.5875 0 0 0 0 0 1 1 1.5750 0 0 0 0 1 0 0 1.5625 0 0 0 0 1 0 1 1.5500 0 0 0 0 1 1 0 1.5375 0 0 0 0 1 1 1 1.5250 0 0 0 1 0 0 0 1.5125 0 0 0 1 0 0 1 1.5000 0 0 0 1 0 1 0 1.4875 0 0 0 1 0 1 1 1.4750 0 0 0 1 1 0 0 1.4625 0 0 0 1 1 0 1 1.4500 0 0 0 1 1 1 0 1.4375 0 0 0 1 1 1 1 1.4250 0 0 1 0 0 0 0 1.4125 0 0 1 0 0 0 1 1.4000 0 0 1 0 0 1 0 1.3875 0 0 1 0 0 1 1 1.3750 0 0 1 0 1 0 0 1.3625 0 0 1 0 1 0 1 1.3500 0 0 1 0 1 1 0 1.3375 0 0 1 0 1 1 1 1.3250 0 0 1 1 0 0 0 1.3125 0 0 1 1 0 0 1 1.3000 0 0 1 1 0 1 0 1.2875 0 0 1 1 0 1 1 1.2750 0 0 1 1 1 0 0 1.2625 0 0 1 1 1 0 1 1.2500 0 0 1 1 1 1 0 1.2375 0 0 1 1 1 1 1 1.2250 0 1 0 0 0 0 0 1.2125 0 1 0 0 0 0 1 1.2000 0 1 0 0 0 1 0 1.1875 0 1 0 0 0 1 1 1.1750 0 1 0 0 1 0 0 1.1625 0 1 0 0 1 0 1 1.1500 0 1 0 0 1 1 0 1.1375 0 1 0 0 1 1 1 1.1250 0 1 0 1 0 0 0 1.1125 0 1 0 1 0 0 1 1.1000 0 1 0 1 0 1 0 1.0875 0 1 0 1 0 1 1 1.0750 0 1 0 1 1 0 0 1.0625 0 1 0 1 1 0 1 1.0500 http://onsemi.com 17 NCP5380, NCP5380A VID Codes (FBRTN = 112.5 mV) VID7 VID6 VID5 VID4 VID3 VID2 VID1 Output 0 1 0 1 1 1 0 1.0375 0 1 0 1 1 1 1 1.0250 0 1 1 0 0 0 0 1.0125 0 1 1 0 0 0 1 1.0000 0 1 1 0 0 1 0 0.9875 0 1 1 0 0 1 1 0.9750 0 1 1 0 1 0 0 0.9625 0 1 1 0 1 0 1 0.9500 0 1 1 0 1 1 0 0.9375 0 1 1 0 1 1 1 0.9250 0 1 1 1 0 0 0 0.9125 0 1 1 1 0 0 1 0.9000 0 1 1 1 0 1 0 0.8875 0 1 1 1 0 1 1 0.8750 0 1 1 1 1 0 0 0.8625 0 1 1 1 1 0 1 0.8500 0 1 1 1 1 1 0 0.8375 0 1 1 1 1 1 1 0.8250 1 0 0 0 0 0 0 0.8125 1 0 0 0 0 0 1 0.8000 1 0 0 0 0 1 0 0.7875 1 0 0 0 0 1 1 0.7750 1 0 0 0 1 0 0 0.7625 1 0 0 0 1 0 1 0.7500 1 0 0 0 1 1 0 0.7375 1 0 0 0 1 1 1 0.7250 1 0 0 1 0 0 0 0.7125 1 0 0 1 0 0 1 0.7000 1 0 0 1 0 1 0 0.6875 1 0 0 1 0 1 1 0.6750 1 0 0 1 1 0 0 0.6625 1 0 0 1 1 0 1 0.6500 1 0 0 1 1 1 0 0.6375 1 0 0 1 1 1 1 0.6250 1 0 1 0 0 0 0 0.6125 1 0 1 0 0 0 1 0.6000 1 0 1 0 0 1 0 0.5875 1 0 1 0 0 1 1 0.5750 1 0 1 0 1 0 0 0.5625 1 0 1 0 1 0 1 0.5500 1 0 1 0 1 1 0 0.5375 1 0 1 0 1 1 1 0.5250 1 0 1 1 0 0 0 0.5125 1 0 1 1 0 0 1 0.5000 1 1 1 1 1 1 1 OFF http://onsemi.com 18 NCP5380, NCP5380A APPLICATION INFORMATION The design parameters for a typical VR11−compliant CPU core VR application are as follows: • Maximum Input Voltage (VINMAX) = 19 V • Minimum Input Voltage (VINMIN) = 8.0 V • Output Voltage by VID Setting (VVID) = 1.2375 V • Maximum Output Current (IO) = 14 A • Droop Resistance (RO) = 6.9 mW • Nominal Output Voltage at 15 A Load (VOFL) = 1.1409 V • Static output voltage drop from no load to full load (DV) = VONL − VOFL = 1.2375 V − 1.1409 V = 96.6 mV • Maximum Output Current Step (DIO) = 11 A • Number of Phases (n) = 1 • Switching Frequency (fSW) = 390 kHz • Duty Cycle at Maximum Input Voltage (DMAX) = 0.15 V • Duty Cycle at Minimum Input Voltage (DMIN) = 0.065 RR + RR + 2 f sw 9 pF * 16 kW R DS AD 0.5 3 VR + VR + The NCP5380/A operates in fixed frequency PWM mode during startup, for 100 ms after a VID change, and in current limit. In PWM operation, the NCP5380/A uses a fixed−frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency determines the switching frequency, which relates directly to the switching losses and the sizes of the inductors and input and output capacitors. For example, a clock frequency of 300 kHz sets the switching frequency to 300 kHz. This selection represents the trade−off between the switching losses and the minimum sizes of the output filter components. To achieve a 300 kHz oscillator frequency at a VID voltage of 1.2 V, RT must be 391 kW. Alternatively, the value for RT can be calculated by using the following equation: V VID ) 1.0 V 3 L 5 (eq. 2) CR 360 nH 5.2 mW 5 pF Where: AR is the internal ramp amplifier gain. AD is the current balancing amplifier gain. RDS is the total low−side MOSFET ON−resistance, CR is the internal ramp capacitor value. Another consideration in the selection of RR is the size of the internal ramp voltage (see Equation 3). For stability and noise immunity, keep this ramp size larger than 0.5 V. Taking this into consideration, the value of RR is selected as 280 kW. The internal ramp voltage magnitude can be calculated using: SETTING THE CLOCK FREQUENCY FOR PWM RT + AR 0.5 (1 * D ) AR RR CR (1 * 0.065) 462 kW 5 pF V VID f sw 1.2375 V 280 kHz (eq. 3) + 0.89 V The size of the internal ramp can be made larger or smaller. If it is made larger, then stability and transient response improves, but thermal balance degrades. Likewise, if the ramp is made smaller, then thermal balance improves at the sacrifice of transient response and stability. The factor of three in the denominator of Equation 2 sets a minimum ramp size that gives an optimal balance for good stability, transient response, and thermal balance. COMP PIN RAMP In addition to the internal ramp, there is a ramp signal on the COMP pin due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input: (eq. 1) V RT + Where: 9 pF and 16 kW are internal IC component values. VVID is the VID voltage in volts. fSW is the switching frequency in hertz. For good initial accuracy and frequency stability, it is recommended to use a 1% resistor. VR 1* 2 (1*D) f Cx R (eq. 4) O Where CX is the total bulk capacitance, and RO is the droop resistance of the regulator. For this example, the overall ramp signal is 0.23 V. SETTING THE SWITCHING FREQUENCY FOR RPM OPERATION RAMP RESISTOR SELECTION During the RPM operation, the NCP5380/A runs in pseudoconstant frequency if the load current is high enough for continuous current mode. While in DCM, the switching frequency is reduced with the load current in a linear manner. To save power with light loads, lower switching The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. Use this equation to determine a starting value: http://onsemi.com 19 NCP5380, NCP5380A frequency is usually preferred during RPM operation. However, the VCC ripple specification of VR11 sets a limitation for the lowest switching frequency. Therefore, depending on the inductor and output capacitors, the switching frequency in RPM can be equal to, greater than, or less than its counterpart in PWM. A resistor from RPM to GND sets the pseudo constant frequency as following: R RPM + 2 RT (1 * D ) AR RR V VID ) 1.0 V CR V VID f sw If the resultant ripple voltage is less than the initially selected value, the inductor can be changed to a smaller value until the ripple value is met. This iteration allows optimal transient response and minimum output decoupling. In this example, the iteration showed that a 560 nH inductor was sufficient to achieve a good ripple. The smallest possible inductor should be used to minimize the number of output capacitors. Choosing a 560 nH inductor is a good choice for a starting point, and it provides a calculated ripple current of 6.6 A. The inductor should not saturate at the peak current of 18.3 A, and it should be able to handle the sum of the power dissipation caused by the winding’s average current (15 A) plus the ac core loss. Another important factor in the inductor design is the DCR, which is used for measuring the inductor current. Too large of a DCR causes excessive power losses, whereas too small of a value leads to increased measurement error. For this example, an inductor with a DCR of 1.3 mW is used. (eq. 5) * 0.5 kW Where: AR is the internal ramp amplifier gain. CR is the internal ramp capacitor value. RR is an external resistor on the RAMPADJ pin to set the internal ramp magnitude. Because RR = 280 kW, the following resistance sets up 300 kHz switching frequency in RPM operation. R RPM + 2 Selecting a Standard Inductor 280 kW After the inductance and DCR are known, select a standard inductor that best meets the overall design goals. It is also important to specify the inductance and DCR tolerance to maintain the accuracy of the system. Using 20% tolerance for the inductance and 15% for the DCR at room temperature are reasonable values that most manufacturers can meet. 1.2375 V ) 1.0 V (1 * 0.065) 0.5 462 kW 5 pF 1.2375 V 300 kHz * 500 W + 208 kW INDUCTOR SELECTION Power Inductor Manufacturers The choice of inductance determines the ripple current of the inductor. Less inductance results in more ripple current, which increases the output ripple voltage and the conduction losses in the MOSFETs. However, this allows the use of smaller−size inductors, and for a specified peak−to−peak transient deviation, it allows less total output capacitance. Conversely, a higher inductance results in lower ripple current and reduced conduction losses, but it requires larger−size inductors and more output capacitance for the same peak−to−peak transient deviation. For a buck converter, the practical value for peak−to−peak inductor ripple current is less than 50% of the maximum dc current of that inductor. Equation 6 shows the relationship between the inductance, oscillator frequency, and peak−to−peak ripple current. Equation 7 can be used to determine the minimum inductance based on a given output ripple voltage. IR + Lw ǒ1 * D MINǓ V VID RO f sw Output Droop Resistance The design requires that the regulator output voltage measured at the chipset pins decreases when the output current increases. The specified voltage drop corresponds to the droop resistance (RO). The output current is measured by low−pass filtering the voltage across the inductor or current sense resistor. The filter is implemented by the CS amplifier that is configured with RPH, RCS, and CCS. The output resistance of the regulator is set by the following equations: (eq. 6) V RIPPLE f sw V VID The following companies provide surface−mount power inductors optimized for high power applications upon request. • Vishay Dale Electronics, Inc. (605) 665−9301 • Panasonic (714) 373−7334 • Sumida Electric Company (847) 545−6700 • NEC Tokin Corporation (510) 324−4110 ǒ1 * D MINǓ (eq. 7) V RIPPLE In this example, RO is assumed to be the ESR of the output capacitance, which results in an optimal transient response. Solving Equation 7 for a 16 mV peak−to−peak output ripple voltage yields: Lw 1.2375 V 6.9 mW 390 kHz (1 * 0.065) 16 mV RO + (eq. 8) C CS + + 1.3 mH http://onsemi.com 20 R CS R PH R SENSE L R SENSE R CS (eq. 9) (eq. 10) NCP5380, NCP5380A RTH(50°C)/RTH(25°C)) and B (B is RTH(90°C)/RTH(25°C)). Note that the relative value of the NTC is always 1 at 25°C. 3. Find the relative value of RCS required for each of the two temperatures. The relative value of RCS is based on the percentage of change needed, which is initially assumed to be 0.39%/°C in this example. The relative values are called r1 (r1 is 1/(1+ TC x (T1 − 25))) and r2 (r2 is 1/(1 + TC x (T2 − 25))), where TC is 0.0039, T1 is 50°C, and T2 is 90°C. 4. Compute the relative values for rCS1, rCS2, and rTH by using the following equations: Where RSENSE is the DCR of the output inductors. Either RCS or RPH can be chosen for added flexibility. Due to the current drive ability of the CSCOMP pin, the RCS resistance should be greater than 100 kW. For example, initially select RCS to be equal to 200 kW, and then use Equation 10 to solve for CCS: C CS + 560 nH 1.3 mW 200 kW + 2.2 nF If CCS is not a standard capacitance, RCS can be tuned. In this case, the required CCS is a standard value and no tuning is required. For best accuracy, CCS should be a 5% NPO capacitor. Next, solve for RPH by rearranging Equation 9 as follows: R PH w 1.3 mW 5.1 mW r cs + 200 kW + 51.0 kW ǒA * BǓ A r1 ǒ1 * BǓ Inductor DCR Temperature Correction Place as close as possible to nearest inductor RTH RTH RC51 NCP5380 16 − + 15 To Switch Node CC51 RC52 ǒ1 * AǓ r1 r 2 * ǒA * BǓ (1 * A) 1 1*r CS2 If the DCR of the inductor is used as a sense element and copper wire is the source of the DCR, the temperature changes associated with the inductor’s winding must be compensated for. Fortunately, copper has a well−known temperature coefficient (TC) of 0.39%/°C. If RCS is designed to have an opposite but equal percentage of change in resistance, it cancels the temperature variation of the inductor’s DCR. Due to the nonlinear nature of NTC thermistors, series resistors RCS1 and RCS2 (see Figure 24) are needed to linearize the NTC and produce the desired temperature coefficient tracking. r2 ) B ǒ1 * AǓ r1 * B r CS1 + The standard 1% resistor for RPH is 51.1 kW. ǒ1 * BǓ r2 * A r TH + *r A *r 1 CS2 (1) 1 1*r CS2 *r 1 CS2 5. Calculate RTH = rTH x RCS , and then select a thermistor of the closest value available. In addition, compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: k+ R TH(ACTUAL) (eq. 11) R TH(CALCULATED) 6. Calculate values for RCS1 and RCS2 by using the following equations: To VOUT Sense R CS1 + R CS Keep this path as short as possible and well away from the Switch Node Lines R CS2 + R CS k (eq. 12) r CS1 ǒ(1 * k) ) ǒk Ǔ r CS2Ǔ For example, if a thermistor value of 100 kW is selected in Step 1, an available 0603−size thermistor with a value close to RCS is the Vishay NTHS0603N04 NTC thermistor, which has resistance values of A = 0.3359 and B = 0.0771. Using the equations in Step 4, rCS1 is 0.359, rCS2 is 0.729, and rTH is 1.094. Solving for rTH yields 219 kW, so a thermistor of 220 kW would be a reasonable selection, making k equal to 1.005. Finally, RCS1 and RCS2 are found to be 72.2 kW and 146 kW. Choosing the closest 1% resistor values yields a choice of 71.5 kW and 147 kW. 14 Figure 24. Temperature−Compensation Circuit Values The following procedure and expressions yield values for RCS1, RCS2, and RTH (the thermistor value at 25°C) for a given RCS value. 1. Select an NTC to be used based on its type and value. Because the value needed is not yet determined, start with a thermistor with a value close to RCS and an NTC with an initial tolerance of better than 5%. 2. Find the relative resistance value of the NTC at two temperatures. The appropriate temperatures will depend on the type of NTC, but 50°C and 90°C have been shown to work well for most types of NTCs. The resistance values are called A (A is Cout SELECTION The required output decoupling for processors and platforms is typically recommended by Intel. For systems containing both bulk and ceramic capacitors, however, the following guidelines can be a helpful supplement. Select the number of ceramics and determine the total ceramic capacitance (CZ). This is based on the number and type of capacitors used. Keep in mind that the best location to place ceramic capacitors is inside the socket; however, the http://onsemi.com 21 NCP5380, NCP5380A Ensure that the ESL of the bulk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using: physical limit is twenty 0805−size pieces inside the socket. Additional ceramic capacitors can be placed along the outer edge of the socket. A combined ceramic capacitor value of 40 mF to 50 mF is recommended and is usually composed of multiple 10 mF or 22 mF capacitors. Ensure that the total amount of bulk capacitance (CX) is within its limits. The upper limit is dependent on the VID OTF output voltage stepping (voltage step, VV, in time, tV, with error of VERR); the lower limit is based on meeting the critical capacitance for load release at a given maximum load step, DIO. The current version of the VR11 specification allows a maximum VCC overshoot (VOSMAX) of 10 mV more than the VID voltage for a step−off load current. ȡ wȧ ȢǒR C x(MIN) C x(MAX) v L O) Ǹ ȡ ȧ Ȣ DI V VID O ǒ 1 ) tv V VID k VV L For typical 15 A applications, the N−channel power MOSFETs are selected for one high−side switch and two low−side switch. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). Because the voltage of the gate driver is 5.0 V, logic−level threshold MOSFETs must be used. The maximum output current, IO, determines the RDS(ON) requirement for the low−side (synchronous) MOSFETs. With conduction losses being dominant, the following expression shows the total power that is dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and the average total output current (IO): (eq. 14) Ǔ ȣȧ RO 2 * 1 * CZ Ȥ ǒ Ǔ Where k + − ln V ERR VV To meet the conditions of these expressions and the transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance, RO. If the CX(MIN) is greater than CX(MAX), the system does not meet the VID OTF specifications and may require less inductance. In addition, the switching frequency may have to be increased to maintain the output ripple. For example, if two pieces of 22 mF, 0805−size MLC capacitors (CZ = 44 mF) are used during a VID voltage change, the VCC change is 220 mV in 22 ms with a setting error of 10 mV. If k = 3.1, solving for the bulk capacitance yields: C X(MIN) w ǒ 560 nH ǒ5.1 mWǓ ) 10 mV 8A 8A P SF + (1 * D) Ǔ * 44 mF 1.174 V C X(MAX) v ǒǸ 1) 3.1 2 ǒ 22 ms 1.174 V 220 mV 3.1 5.1 mW Ǔ ǒ Ǔƫ 2 IR ) 1 12 h SF 2 R DSǒSFǓ (eq. 16) (1 * D) L V OUT f sw Knowing the maximum output current and the maximum allowed power dissipation, the user can calculate the required RDS(ON) for the MOSFET. For an 8−lead SOIC or 8−lead SOIC−compatible MOSFET, the junction−to−ambient (PCB) thermal impedance is 50°C/W. In the worst case, the PCB temperature is 70°C to 80°C during heavy load operation of the notebook, and a safe limit for PSF is about 0.8 W to 1.0 W at 120°C junction temperature. Therefore, for this example (15 A maximum), the RDS(SF) per MOSFET is less than 18.8 mW for the 1.174 V 560 nH Ǔ h SF IR + 220 mV (5.1 mW) 2 ƪǒ IO where: D is the duty cycle and is approximately the output voltage divided by the input voltage. IR is the inductor peak−to−peak ripple current and is approximately: + 246 mF 560 nH 2 + 2.3 nH POWER MOSFETS V VID RO 2 (eq. 15) Where: Q is limited to the square root of 2 to ensure a critically damped system. LX is about 450 pH for the two SP capacitors, which is low enough to avoid ringing during a load change. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased to prevent excessive ringing. For this multimode control technique, an all ceramic capacitor design can be used if the conditions of Equations 13, 14, and 15 are satisfied. (eq. 13) z OSMAX Q2 (5.1 mW) 2 L X v 44 mF VV L k2 V ȣ *C ȧ Ǔ Ȥ DI O RO 2 LX v CZ Ǔ * 1 * 44 mF + 992 mF Using two 220 mF Panasonic SP capacitors with a typical ESR of 7 mW each yields CX = 440 mF and RX = 3.5 mW. http://onsemi.com 22 NCP5380, NCP5380A low−side MOSFET. This RDS(SF) is also at a junction temperature of about 120°C; therefore, the RDS(SF) per MOSFET should be less than 13.3 mW at room temperature, or 18.8 mW at high temperature. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input must be small (less than 10% is recommended) to prevent accidentally turning on the synchronous MOSFETs when the switch node goes high. The high−side (main) MOSFET must be able to handle two main power dissipation components: conduction losses and switching losses. Switching loss is related to the time for the main MOSFET to turn on and off and to the current and voltage that are being switched. Basing the switching speed on the rise and fall times of the gate driver impedance and MOSFET input capacitance, the following expression provides an approximate value for the switching loss per main MOSFET: P S(MF) + 2 IO V DS f SW h MF RG h MF P DRV + P C(MF) + D ƪǒ Ǔ h MF 2 1 ) 12 ǒ Ǔƫ IR h MF 2 f sw n ǒnMF Q QFM ) n SF ƫ Q GSFǓ ) I CC (eq. 19) V CC where QGMF is the total gate charge for each main MOSFET, and QGSF is the total gate charge for each synchronous MOSFET. The previous equation also shows the standby dissipation (ICC times the VCC) of the driver. Current Limit Setpoint To select the current−limit set point, we need to find the resistor value for RLIM. The current−limit threshold for the NCP5380/A is set when the current in RLIM is equal to the internal reference current of 20 mA. The current in RLIM is equal to the inductor current times RO. RLIM can be found using the following equation: R LIM + C ISS (eq. 17) I LIM RO (eq. 20) 20 mA Where: RLIM is the current limit resistor. RLIM is connected from the ILIM pin to the CSCOMP pin. RO is the output load line resistance. ILIM is the current limit set point. This is the peak inductor current that will trip current limit. Where: nMF is the total number of main MOSFETs. RG is the total gate resistance. CISS is the input capacitance of the main MOSFET. The most effective way to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by the following equation: IO ƪ In this example, if choosing 20 A for ILIM, RLIM is 6.9 kW, which is close to a standard 1% resistance of 6.98 kW. The per−phase current limit described earlier has its limit determined by the following: 2 R DS(MF) I PHLIM ^ (eq. 18) V COMP(MAX) * V R * V BIAS AD R DS(MAX) ) IR 2 (eq. 21) For the NCP5380/A, the maximum COMP voltage (VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.0 V, and the current balancing amplifier gain (AD) is 5. Using a VR of 0.55 V, and a RDS(MAX) of 3.8 mW (low−side on−resistance at 150°C) results in a per−phase limit of 85 A. Although this number seems high, this current level can only be reached with a absolute short at the output and the current−limit latchoff function shutting down the regulator before overheating occurs. This limit can be adjusted by changing the ramp voltage VR. However, users should not set the per−phase limit lower than the average per−phase current (ILIM/n). There is also a per−phase initial duty−cycle limit at maximum input voltage: Where RDS(MF) is the on resistance of the MOSFET. Typically, a user wants the highest speed (low CISS) device for a main MOSFET, but such a device usually has higher on resistance. Therefore, the user must select a device that meets the total power dissipation (about 0.8 W to 1.0 W for an 8−lead SOIC) when combining the switching and conduction losses. For example, an NTMFS4821N device can be selected as the main MOSFET (one in total; that is, nMF = 1), with approximately CISS = 1400 pF (maximum) and RDS(MF) = 8.6 mW (maximum at TJ = 120°C), and an NTMFS4846N device can be selected as the synchronous MOSFET (two in total; that is, nSF = 2), with RDS(SF) = 3.8 mW (maximum at TJ = 120°C). Solving for the power dissipation per MOSFET at IO = 15 A and IR = 5.0 A yields 178 mW for each synchronous MOSFET and 446 mW for each main MOSFET. A third synchronous MOSFET is an option to further increase the conversion efficiency and reduce thermal stress. Finally, consider the power dissipation in the driver. This is best described in terms of the QG for the MOSFETs and is given by the following equation: D LIM + D MIN V COMP(MAX) * V BIAS VR (eq. 22) Current Monitor The NCP5380/A has an output current monitor. The IMON pin sources a current proportional to the total inductor current. A resistor, RMON, from IMON to FBRTN http://onsemi.com 23 NCP5380, NCP5380A VOLTAGE ERROR AMPLIFIER sets the gain of the output current monitor. A 0.1 mF is placed in parallel with RMON to filter the inductor current ripple and high frequency load transients. Since the IMON pin is connected directly to the CPU, it is clamped to prevent it from going above 1.15 V. The IMON pin current is equal to the RLIMtimes a fixed gain of 10. RMON can be found using the following equation: R MON + 1.15 V 10 RO R LIM I FS REFERENCE VOLTAGE + − COMP FB NCP5380 CA RA OUTPUT VOLTAGE CFB (eq. 23) CB Where: RMON is the current monitor resistor. RMON is connected from IMON pin to FBRTN. RLIM is the current limit resistor. RO is the output load line resistance. IFS is the output current when the voltage on IMON is at full scale. RFB Figure 25. Voltage Error Amplifier GAIN −20dB/DEC −20dB/DEC Feedback Loop Compensation Design Optimized compensation of the NCP5380/A allows the best possible response of the regulator’s output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and that is equal to the droop resistance (RO). With the resistive output impedance, the output voltage droops in proportion with the load current at any load current slew rate, ensuring the optimal position and allowing the minimization of the output decoupling. With the multimode feedback structure of the NCP5380/A, it is necessary to set the feedback compensation so that the converter’s output impedance works in parallel with the output decoupling. In addition, it is necessary to compensate for the several poles and zeros created by the output inductor and decoupling capacitors (output filter). A Type III compensator on the voltage feedback is adequate for proper compensation of the output filter. Figure 25 shows the Type III amplifier used in the NCP5380/A. Figure 26 shows the locations of the two poles and two zeros created by this amplifier. 0dB fZ2 fZ1 fP1 fP2 FREQUENCY Figure 26. Poles and Zeros of Voltage Error The following equations give the locations of the poles and zeros shown in Figure 26: 1 f Z1 + 2p CA f Z2 + 2p C FB f P1 + f P2 + (eq. 24) RA 1 (eq. 25) R FB 1 2pǒC A ) C BǓ R FB 1 2p RA CB CA (eq. 26) (eq. 27) The expressions that follow compute the time constants for the poles and zeros in the system and are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see the Tuning Procedure for NCP5380/A section): RE + RO ) AD ) TA + CX 2 L R DS ) CX RO ǒRO * RȀǓ ) 24 V RT V VID (1 * (n T B + ǒR X ) RȀ * R O Ǔ http://onsemi.com RL D)) (eq. 28) V RT V VID LX R O * RȀ RO RX CX (eq. 29) (eq. 30) NCP5380, NCP5380A V RT TC + TD + ǒ L* A V VID CX CX D R 2 Ǔ (eq. 31) RE C ST + RO 2 CZ change is controlled by the ST pin capacitance. The ST pin capacitance is set to satisfy the slew rate for a fast exit as follows: DS f ǒRO * RȀǓ ) CZ (eq. 32) RO RA + CB + RO TA RE RB Set−Up and Test the Circuit 1. Build a circuit based on the compensation values computed from the design spreadsheet. 2. Connect a dc load to the circuit. 3. Turn on the NCP5380/A and verify that it operates properly. 4. Check for jitter with no load and full load conditions. (eq. 34) CA Set the DC Load Line TB 1. Measure the output voltage with no load (VNL) and verify that this voltage is within the specified tolerance range. 2. Measure the output voltage with a full load when the device is cold (VFLCOLD). Allow the board to run for ~10 minutes with a full load and then measure the output when the device is hot (VFLHOT). If the difference between the two measured voltages is more than a few millivolts, adjust RCS2 using Equation 39. (eq. 35) RB C FB + TUNING PROCEDURE FOR NCP5380 (eq. 33) TC TD (eq. 36) RA The standard values for these components are subject to the tuning procedure described in the Tuning Procedure for NCP5380/A section. CIN Selection and Input Current di/dt Reduction In continuous inductor−current mode, the source current of the high−side MOSFET is approximately a square wave with a duty ratio equal to VOUT /VIN . To prevent large voltage transients, use a low ESR input capacitor sized for the maximum rms current. The maximum rms capacitor current occurs at the lowest input voltage and is given by I CRMS + D 1O I CRMS + 0.15 (eq. 38) SLEWRATE Where: 7.5 mA is the source/sink current of the ST pin. SLEWRATE is the voltage slew rate after a change in VID voltage and is defined as 10 mV/mA in the VR11 specification. CST is 750 pF, and the closest standard capacitance is 680 pF. Where: R’ is the PCB resistance from the bulk capacitors to the ceramics and is approximately 0.4 mW (assuming an 8−layer motherboard). RDS is the total low−side MOSFET for on resistance. AD is 5. VRT is 1.25 V. LX is the ESL of the bulk capacitors (450 pH for the two Panasonic SP capacitors). The compensation values can be calculated as follows: CA + 7.5 mA Ǹ1 * 1 15 A 5.36 V NL * V FLCOLD V NL * V FLHOT (eq. 39) 3. Repeat Step 2 until no adjustment of RCS2 is needed. 4. Compare the output voltage with no load to that with a full load using 5 A steps. Compute the load line slope for each change and then find the average to determine the overall load line slope (ROMEAS). 5. If the difference between ROMEAS and RO is more than 0.05 mW, use the following equation to adjust the RPH values: (eq. 37) D 1 Ǹ0.15 *1 R CS2(NEW) + R CS2(OLD) A Where IO is the output current. In a typical notebook system, the battery rail decoupling is achieved by using MLC capacitors or a mixture of MLC capacitors and bulk capacitors. In this example, the input capacitor bank is formed by four pieces of 10 mF, 25 V MLC capacitors, with a ripple current rating of about 1.5 A each. R PH(NEW) + R PH(OLD) R OMEAS RO (eq. 40) 6. Repeat Steps 4 and 5 until no adjustment of RPH is needed. Once this is achieved, do not change RPH, RCS1, RCS2, or RTH for the rest of the procedure. 7. Measure the output ripple with no load and with a full load with scope, making sure both are within the specifications. SOFT TRANSIENT SETTING As described in the Theory of Operation section, during the soft transient, the slew rate of the VCC reference voltage http://onsemi.com 25 NCP5380, NCP5380A Set the AC Load Line Set the Initial Transient 1. Remove the dc load from the circuit and connect a dynamic load. 2. Connect the scope to the output voltage and set it to dc coupling mode with a time scale of 100 ms/div. 3. Set the dynamic load for a transient step of about 40 A at 1 kHz with 50% duty cycle. 4. Measure the output waveform (note that use of a dc offset on the scope may be necessary to see the waveform). Try to use a vertical scale of 100 mV/div or finer. 5. Do not measure the undershoot or overshoot that occurs immediately after the step. Figure 28. Transient Setting Waveform, Load Step 1. With the dynamic load set at its maximum step size, expand the scope time scale to 2 ms/div to 5 ms/div. This results in a waveform that may have two overshoots and one minor undershoot before achieving the final desired value after VDROOP (see Figure 28). 2. If both overshoots are larger than desired, try the following adjustments in the order shown. a. Increase the resistance of the ramp resistor (RRAMP) by 25%. b. For VTRAN1, increase CB or increase the switching frequency. c. For VTRAN2, increase RA by 25% and decrease CA by 25%. If these adjustments do not change the response, it is because the system is limited by the output decoupling. Check the output response and the switching nodes each time a change is made to ensure that the output decoupling is stable. 3. For load release (see Figure 29), if VTRANREL is larger than the value specified by VR11, a greater percentage of output capacitance is needed. Either increase the capacitance directly or decrease the inductor values. (If inductors are changed, however, it will be necessary to redesign the circuit using the information from the spreadsheet and to repeat all tuning guide procedures). Figure 27. AC Load Line Waveform 6. If the difference between VACDRP and VDCDRP is more than a couple of millivolts, use Equation 42 to adjust CCS. It may be necessary to try several parallel values to obtain an adequate one because there are limited standard capacitor values available (it is a good idea to have locations for two capacitors in the layout for this reason). C CS(NEW) + C CS(OLD) V ACDRP V DCDRP (eq. 41) 7. Repeat Steps 5 and 6 until no adjustment of CCS is needed. Once this is achieved, do not change CCS for the rest of the procedure. 8. Set the dynamic load step to its maximum step size (but do not use a step size that is larger than needed) and verify that the output waveform is square, meaning VACDRP and VDCDRP are equal. 9. Ensure that the load step slew rate and the power−up slew rate are set to ~150 A/ms to 250 A/ms (for example, a load step of 50 A should take 200 ns to 300 ns) with no overshoot. Some dynamic loads have an excessive overshoot at power−up if a minimum current is incorrectly set (this is an issue if a VTT tool is in use). Figure 29. Transient Setting Waveform, Load Release http://onsemi.com 26 NCP5380, NCP5380A LAYOUT AND COMPONENT PLACEMENT problems for the entire PC system as well as noise−related operational problems in the power−converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. The use of short, wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. 2. When a power−dissipating component (for example, a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer heat to the surrounding air. To achieve optimal thermal dissipation, mirror the pad configurations used to heat sink the MOSFETs on the opposite side of the PCB. In addition, improvements in thermal performance can be obtained using the largest possible pad area. 3. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. 4. For best EMI containment, a solid power ground plane should be used as one of the inner layers and extended under all power components. The following guidelines are recommended for optimal performance of a switching regulator in a PC system. General Recommendations 1. For best results, use a PCB of four or more layers. This should provide the needed versatility for control circuitry interconnections with optimal placement; power planes for ground, input, and output; and wide interconnection traces in the rest of the power delivery current paths. Keep in mind that each square unit of 1 oz copper trace has a resistance of ~0.53 mW at room temperature. 2. When high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. 3. If critical signal lines (including the output voltage sense lines of the NCP5380/A) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of increasing signal ground noise. 4. An analog ground plane should be used around and under the NCP5380/A for referencing the components associated with the controller. This plane should be tied to the nearest ground of the output decoupling capacitor, but should not be tied to any other power circuitry to prevent power currents from flowing into the plane. 5. The components around the NCP5380/A should be located close to the controller with short traces. The most important traces to keep short and away from other traces are those to the FB and CSFB pins. Refer to Figure 24 for more details on the layout for the CSFB node. 6. The output capacitors should be connected as close as possible to the load (or connector) that receives the power (for example, a microprocessor core). If the load is distributed, the capacitors should also be distributed and generally placed in greater proportion where the load is more dynamic. 7. Avoid crossing signal lines over the switching power path loop, as described in the Power Circuitry section. Signal Circuitry 1. The output voltage is sensed and regulated between the FB and FBRTN pins, and the traces of these pins should be connected to the signal ground of the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be as small as possible. Therefore, the FB and FBRTN traces should be routed adjacent to each other, atop the power ground plane, and back to the controller. 2. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be Kelvin connected to the center point of the copper bar, which is the VCC common node for the inductor. 3. On the back of the NCP5380/A package, there is a metal pad that can be used to heat sink the device. Therefore, running vias under the NCP5380/A is not recommended because the metal pad may cause shorting between vias. Power Circuitry 1. The switching power path on the PCB should be routed to encompass the shortest possible length to minimize radiated switching noise energy (that is, EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI Intel is a registered trademark of Intel Corporation. http://onsemi.com 27 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN32 5x5, 0.5P CASE 488AM ISSUE A 1 32 SCALE 2:1 A D PIN ONE LOCATION ÉÉ ÉÉ NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L B DATE 23 OCT 2013 L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E DIM A A1 A3 b D D2 E E2 e K L L1 0.15 C 0.15 C EXPOSED Cu A DETAIL B 0.10 C (A3) A1 0.08 C DETAIL A 9 32X L ALTERNATE CONSTRUCTION GENERIC MARKING DIAGRAM* K D2 1 XXXXXXXX XXXXXXXX AWLYYWWG G 17 8 MOLD CMPD DETAIL B SEATING PLANE C SIDE VIEW NOTE 4 ÉÉ ÉÉ ÇÇ TOP VIEW MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.18 0.30 5.00 BSC 2.95 3.25 5.00 BSC 2.95 3.25 0.50 BSC 0.20 −−− 0.30 0.50 −−− 0.15 E2 1 32 25 e e/2 32X b 0.10 M C A B 0.05 M C BOTTOM VIEW XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 5.30 32X 0.63 3.35 3.35 5.30 0.50 PITCH 32X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON20032D QFN32 5x5 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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