NCP5386A

NCP5386, NCP5386A, NCP5386B 1/2 Phase Controller for CPU and Chipset Applications The NCP5386 is a one− or two−phase buck controller which combines differential voltage and current sensing, and adaptive voltage positioning to power both AMD and Intel processors and chipsets. Dual−edge pulse−width modulation (PWM) combined with inductor current sensing reduces system cost by providing the fastest initial response to transient load events. Dual−edge multi−phase modulation reduces total bulk and ceramic output capacitance required to satisfy transient load−line regulation. A high performance operational error amplifier is provided, which allows easy compensation of the system. The proprietary method of Dynamic Reference Injection (Patented) makes the error amplifier compensation virtually independent of the system response to VID changes, eliminating tradeoffs between overshoot and dynamic VID performance. Features http://onsemi.com MARKING DIAGRAMS 1 1 32 NCP5386x AWLYYWWG QFN32, 5 x 5* MN SUFFIX CASE 485AF *Pin 33 is the thermal pad on the bottom of the device. NCP5386 = Specific Device Code x = Blank, A or B A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package • Meets Intel’s VR 10.0 and 11.0, and AMD Specifications • No load Intel VR Offset of −19 mV (NCP5386), +20 mV • • • • • • • • • • • • • • • • • (NCP5386A), and 0 mV (NCP5386B) Dual−Edge PWM for Fastest Initial Response to Transient Loading High Performance Operational Error Amplifier Supports both VR11 and Legacy Soft−Start Modes Dynamic Reference Injection (Patent# 7057381) DAC Range from 0.5 V to 1.6 V "0.5% System Voltage Accuracy from 1.0 V to 1.6 V True Differential Remote Voltage Sensing Amplifier Phase−to−Phase Current Balancing “Lossless” Differential Inductor Current Sensing Differential Current Sense Amplifiers for each Phase Adaptive Voltage Positioning (AVP) Frequency Range: 100 kHz – 1.0 MHz OVP with Resettable, 8 Event Delayed Latch Threshold Sensitive Enable Pin for VTT Sensing Power Good Output with Internal Delays Programmable Soft−Start Time This is a Pb−Free Device* ORDERING INFORMATION Device NCP5386MNR2G* NCP5386AMNR2G* NCP5386BMNR2G* Package QFN32 (Pb−Free) QFN32 (Pb−Free) QFN32 (Pb−Free) Shipping† 2500 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel *Temperature Range: 0°C to 85°C †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Applications • Desktop Processors and Chipsets • Server Processors and Chipsets • DDR *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2008 May, 2008 − Rev. 1 1 Publication Order Number: NCP5386/D NCP5386, NCP5386A, NCP5386B 32 31 30 29 28 27 26 12VMON 25 G2 NTC VR_FAN VID0 1 2 3 4 5 6 7 8 VR_RDY VCC EN VID1 VID2 VID3 VID4 VID5 VID6 VID7 DACMODE G1 DRVON CS2 24 23 22 21 20 19 18 17 NCP5386/A/B 1/2−Phase Buck Controller (QFN32) AGND Down−Bonded to Exposed Flag DIFFOUT COMP ROSC ILIM VS− VS+ NC CS2N CS1 CS1N VDRP VFB 9 SS 10 11 12 13 14 15 Figure 1. Pin Connections (Top View) http://onsemi.com 2 16 NCP5386, NCP5386A, NCP5386B +5 V VTT 680 W PULLUPS RVCC +5 V CVCC1 RNTC1 U1 VCC VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VID_SEL VR_EN VR_RDY VR_FAN VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 DACMODE EN VR_RDY VR_FAN VS− VS+ RISO1 RISO2 CS2 CS2N NCP3418 VCC OD RT2 BST DRVH SW DRVL IN CFB1 RFB VFB RDRP VDRP CD1 RD1 COMP ILIM ROSC SS DRVON RFB1 DIFFOUT CS2 PGND RS2 G1 CS1 CS1N G2 GND 12VMON NTC RT1 RNTC2 NCP3418B VCC OD IN BST DRVH SW DRVL PGND RS1 C4 12 V_FILTER 12 V_FILTER CS1 12 V_FILTER 12 V_FILTER NCP5386/A/B CF RF CH RVFB RLIM1 CSS RLIM2 RT2 LOCATED NEAR OUTPUT INDUCTORS VCCP + VSSP CPU/MCH GND Figure 2. 2−Phase Application Schematic http://onsemi.com 3 NCP5386, NCP5386A, NCP5386B +5 V VTT 680 W PULLUPS RVCC +5 V CVCC1 RNTC1 U1 VCC VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VID_SEL VR_EN VR_RDY VR_FAN VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 DACMODE EN VR_RDY VR_FAN VS− VS+ RISO1 RISO2 CS2 CS2N G1 CS1 CS1N DGND 12VMON NTC RNTC2 NCP3418B VCC OD IN RT1 BST DRVH SW DRVL PGND RS1 12 V_FILTER 12 V_FILTER CS1 RT2 NCP5386/A/B CFB1 RFB RFB1 DIFFOUT VFB RDRP VDRP DRVON CD1 RD1 COMP CF RF ILIM ROSC SS CH RVFB RLIM1 CSS RLIM2 RT2 LOCATED NEAR OUTPUT INDUCTORS VCCP + VSSP CPU/MCH GND Figure 3. 1−Phase Application Schematic http://onsemi.com 4 NCP5386, NCP5386A, NCP5386B DACMODE VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 SS NCP5386/A/B VR10/11/AMD DAC + DAC NTC VR_FAN NTC VS− VS+ DIFFOUT + Diff Amp Fault 1.3 V + Error Amp Droop Amplifier 1.3 V +− VFB COMP VDRP GND CS1 CS1N CS2 CS2N + Gain = 6 + - ENB G1 + Gain = 6 + - ENB G2 OVER Oscillator ROSC DIFFOUT Fault + ILIM EN VCC ILimit + VCC UVLO + 12VMON UVLO Fault Logic 3 Phase Detect and Monitor Circuits DRVON VR_RDY 12VMON Figure 4. Simplified Block Diagram http://onsemi.com 5 NCP5386, NCP5386A, NCP5386B PIN DESCRIPTIONS QFN32 Pin No. 32, 1 – 7 8 9 10 Symbol VID0–VID7 DACMODE SS ROSC Voltage ID DAC inputs VRM select bit A capacitor from this pin to ground programs the soft−start time. A resistance from this pin to ground programs the oscillator frequency. Also, this pin supplies an output voltage of 2 V which may be used to form a voltage divider to the ILIM pin to set the over−current shutdown threshold as shown in the Applications Schematics. Overcurrent shutdown threshold. To program the shutdown threshold, connect this pin to the ROSC pin via a resistor divider as shown in the Applications Schematics. To disable the over−current feature, connect this pin directly to the ROSC pin. To guarantee correct operation, this pin should only be connected to the voltage generated by the ROSC pin; do not connect this pin to any externally generated voltages. Do not connect anything to this pin. Non−inverting input to the internal differential remote sense amplifier Inverting input to the internal differential remote sense amplifier Output of the differential remote sense amplifier Output of the error amplifier, and the non−inverting input of the PWM comparators Error amplifier inverting input. Connect a resistor from this pin to DIFFOUT. The value of this resistor and the amount of current from the droop resistor (RDRP) will set the amount of output voltage droop (AVP) during load. Current signal output for Adaptive Voltage Positioning (AVP). The voltage of this pin above the 1.3 V internal offset voltage is proportional to the output current. Connect a resistor from this pin to VFB to set the amount of AVP current into the feedback resistor (RFB) to produce an output voltage droop. Leave this pin open for no AVP. Inverting input to current sense amplifier. Non−inverting input to current sense amplifier. Output to enable Gate Drivers PWM output pulses to gate drivers Second UVLO monitor for monitoring the power stage supply rail Power for the internal control circuits. Voltage Regulator Ready (Power Good) output. Open drain output that indicates the output is regulating. Remote temperature sense connection. Connect an NTC thermistor from this pin to GND and a resistor from this pin to VREF. As the NTC’s temperature increases, the voltage on this pin will decrease. Open drain output that will be low impedance when the voltage at the NTC pin is above the specified threshold. This pin will transition to a high impedance state when the voltage at the NTC pin decreases below the specified threshold. This pin requires an external pull−up resistor. Pull this pin high to enable controller. Pull this pin low to disable controller. Either an open−collector output (with a pull−up resistor) or a logic gate (CMOS or totem−pole output) may be used to drive this pin. A Low−to−High transition on this pin will initiate a soft start. Connect this pin directly to VREF if the Enable function is not required. 20 MHz filtering at this pin is required. Power supply return (QFN Flag) Description 11 ILIM 12 13 14 15 16 17 NC VS+ VS− DIFFOUT COMP VFB 18 VDRP 19, 21 20, 22 23 24, 25 26 27 28 29 30 CS1N, CS2N CS1, CS2 DRVON G1, G2 12VMON VCC VR_RDY NTC VR_FAN 31 EN 33 GND http://onsemi.com 6 NCP5386, NCP5386A, NCP5386B MAXIMUM RATINGS Electrical Information Pin Symbol COMP VDRP VS+ VS− DIFFOUT VR_RDY, VR_FAN VCC ROSC DACMODE, EN All Other Pins *All signals reference to GND unless otherwise noted. Thermal Information Rating Thermal Characteristic, QFN Package (Note 1) Symbol RqJA TJ TA TSTG MSL Value 56 0 to 125 0 to 85 −55 to +150 1 Unit °C/W °C °C °C VMAX (V) 5.5 5.5 2.0 2.0 5.5 5.5 7.0 5.5 3.5 5.5 VMIN (V) −0.3 −0.3 GND − 300 mV GND − 300 mV −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 ISOURCE (mA) 10 5 1 1 20 N/A N/A 1 0 − ISINK (mA) 10 5 1 1 20 20 20 N/A 0 − Operating Junction Temperature Range (Note 2) Operating Ambient Temperature Range Maximum Storage Temperature Range Moisture Sensitivity Level, QFN Package Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *The maximum package power dissipation must be observed. 1. JESD 51−5 (1S2P Direct−Attach Method) with 0 Airflow. 2. JESD 51−7 (1S2P Direct−Attach Method) with 0 Airflow. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Error Amplifier Input Bias Current Input Offset Voltage (Note 3) Open Loop DC Gain (Note 3) Open Loop Unity Gain Bandwidth (Note 3) Open Loop Phase Margin (Note 3) Slew Rate (Note 3) CL = 60 pF to GND, RL = 10 kW to GND CL = 60 pF to GND, RL = 10 kW to GND CL = 60 pF to GND, RL = 10 kW to GND DVIN = 100 mV, G = −10 V/V, 1.5 V < COMP < 2.5 V, CL = 60 pF, DC Load = ±125 mA 10 mV of Overdrive ISOURCE = 2.0 mA 10 mV of Overdrive ISINK = 2.0 mA −200 −1.0 − − − − − − 100 15 70 5 200 1.0 − − − − nA mV dB MHz ° V/ms Test Conditions Min Typ Max Units Maximum Output Voltage Minimum Output Voltage 2.20 − VCC − 20 mV 0.01 − 0.5 V V 3. Guaranteed by design. Not tested in production. http://onsemi.com 7 NCP5386, NCP5386A, NCP5386B ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Error Amplifier Output Source Current (Note 3) Output Sink Current (Note 3) Differential Summing Amplifier VS+ Input Resistance VS+ Input Bias Voltage VS− Bias Current VS+ Input Voltage Range VS− Input Voltage Range DC Gain VS+ to DIFFOUT DAC Accuracy (measured at VS+) DRVON = Low DRVON = High DRVON = Low DRVON = High VS− = 0 V 0.95 v DDIFFOUT / DVS− v 1.05 0.5 V v DIFFOUT v 2.0 V 0.95 v DDIFFOUT / DVS− v 1.05 0.5 V v DIFFOUT v 2.0 V 0 V v DAC − VS+ v 0.3 V Closed loop measurement including error amplifier. (See Figure 20) 1.0 v DAC v 1.6 0.8 v DAC v 1.0 0.5 v DAC v 0.8 CL = 80 pF to GND, RL = 10 kW to GND DVIN = 100 mV, DIFFOUT = 1.3 V to 1.2 V VS+ − DAC = 1.0 V ISOURCE = 2.0 mA VS+ − DAC = −0.8 V ISINK = 2.0 mA VS+ − DAC = 1.0 V DIFFOUT = 1.0 V VS+ − DAC = −0.8 V DIFFOUT = 1.0 V − − − − − −0.3 −0.3 0.99 1.5 17 0.05 0.65 33 − − − − − − − − 2.0 0.3 1.01 kW V mA V V V/V 10 mV Input Overdrive COMP = 2.0 V 10 mV Input Overdrive COMP = 1.0 V 2.0 2.0 − − − − mA mA Test Conditions Min Typ Max Units −0.5 −5 −8 − − 2.0 − 2.0 2.0 − − − 10 5.0 3.0 0.01 − − 0.5 5 8 − − − 0.5 − − % mV mV MHz V/ms V V mA mA −3dB Bandwidth (Note 3) Slew Rate (Note 3) Maximum Output Voltage Minimum Output Voltage Output Source Current (Note 3) Output Sink Current Internal Offset Voltage VDRP pin offset voltage AND Error Amp input voltage − 1.30 V VDRP Adaptive Voltage−Positioning Amplifier Current Sense Input to VDRP Gain Current Sense Input to VDRP −3dB Bandwidth (Note 3) VDRP Output Slew Rate (Note 3) −60 mV < (CSx−CSxN) < +60 mV (Each CS Input Independently) CL = 30 pF to GND, RL = 10 kW to GND DVIN = 25 mV 1.3 V < VDRP < 1.9 V, CL = 330 pF to GND, RL = 1 kW to 10 kW connected to 1.3 V CSx= CSxN = 1.3 V CSx − CSxN = 0.1 V (all phases), ISOURCE = 1.0 mA 5.64 − 2.5 5.79 4 − 5.95 − − V/V MHz V/ms VDRP Output Voltage Offset from Internal Offset Voltage Maximum VDRP Output Voltage −15 2.6 − 3.0 +15 − mV V 3. Guaranteed by design. Not tested in production. http://onsemi.com 8 NCP5386, NCP5386A, NCP5386B ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter VDRP Adaptive Voltage−Positioning Amplifier Minimum VDRP Output Voltage Output Source Current (Note 3) Output Sink Current (Note 3) Current Sense Amplifiers Input Bias Current Common Mode Input Voltage Range Differential Mode Input Voltage Range (Note 3) Input Referred Offset Voltage (Note 3) Current Sense Input to PWM Gain Oscillator Switching Frequency Range (Note 3) Switching Frequency Accuracy ROSC = 50 kW 25 kW 10 kW 100 196 380 803 − − 1.950 − − − − 5 10 2.010 1000 226 420 981 − − 2.065 kHz kHz CSx = CSxN = 1.0 V 0 V < (CSx − CSxN) < 0.1 V CSx = CSxN = 1.4 V −200 −0.3 −120 −1.0 − − − − − 6.0 200 2.0 120 1.0 − nA V mV mV V/V CSx − CSxN = −0.033 V (all phases), ISINK = 1.0 mA VDRP = 2.0 V VDRP = 1.0 V − − − 0.1 1.3 25 0.5 − − V mA mA Test Conditions Min Typ Max Units Switching Frequency Tolerance (Note 3) ROSC Output Voltage Modulators (PWM Comparators) Minimum Pulse Width (Note 3) Propagation Delay (Note 3) Magnitude of the PWM Ramp 0% Duty Cycle 100% Duty Cycle PWM Linear Duty Cycle (Note 3) PWM Phase Angle Error VR_RDY (Power Good) Output VR_RDY Saturation Voltage VR_RDY Rise Time 200 kHz < FSW < 600 kHz 100 kHz < FSW