Operational Amplifier,
Zero-Drift, 10 mV Offset,
0.07 mV/5C
NCS333A, NCV333A,
NCS2333, NCV2333,
NCS4333, NCV4333,
NCS333
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The NCS333/2333/4333 family of zero−drift op amps feature offset
voltage as low as 10 mV over the 1.8 V to 5.5 V supply voltage range.
The zero−drift architecture reduces the offset drift to as low as
0.07 mV/°C and enables high precision measurements over both time
and temperature. This family has low power consumption over a wide
dynamic range and is available in space saving packages. These
features make it well suited for signal conditioning circuits in portable,
industrial, automotive, medical and consumer markets.
5
5
1
1
SC70−5
SQ SUFFIX
CASE 419A
SOT23−5
SN SUFFIX
CASE 483
1
UDFN8
MU SUFFIX
CASE 517AW
Features
• Gain−Bandwidth Product:
270 kHz (NCx2333)
350 kHz (NCx333, NCx333A, NCx4333)
Low Supply Current: 17 mA (typ at 3.3 V)
Low Offset Voltage:
♦ 10 mV max for NCS333, NCS333A
♦ 30 mV max for NCV333A, NCx2333 and NCx4333
Low Offset Drift: 0.07 mV/°C max for NCS333/A
Wide Supply Range: 1.8 V to 5.5 V
Wide Temperature Range: −40°C to +125°C
Rail−to−Rail Input and Output
Available in Single, Dual and Quad Packages
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
MSOP−8
DM SUFFIX
CASE 846A−02
♦
•
•
•
•
•
•
•
•
♦
April, 2021 − Rev. 20
1
1
SOIC−8
D SUFFIX
CASE 751
SOIC−14
D SUFFIX
CASE 751A
14
1
TSSOP−14 WB
DT SUFFIX
CASE 948G
See general marking information in the device marking
section on page 2 of this data sheet.
Automotive
Battery Powered/ Portable Application
Sensor Signal Conditioning
Low Voltage Current Sensing
Filter Circuits
Bridge Circuits
Medical Instrumentation
© Semiconductor Components Industries, LLC, 2017
14
DEVICE MARKING INFORMATION
Applications
•
•
•
•
•
•
•
8
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
1
Publication Order Number:
NCS333/D
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
DEVICE MARKING INFORMATION
Single Channel Configuration
NCS333, NCS333A, NCV333A
33XAYWG
G
33XMG
G
TSOP−5/SOT23−5
CASE 483
SC70−5
CASE 419A
Dual Channel Configuration
NCS2333, NCV2333
8
1
8
2333
AYWG
G
33A
YM
1
1
UDFN8, 2x2, 0.5P
CASE 517AW
Micro8/MSOP8
CASE 846A−02
SOIC−8
CASE 751
Quad Channel Configuration
NCS4333, NCV4333
14
14
NCS4333G
AWLYWW
4333
ALYWG
G
1
1
SOIC−14
CASE 751A
TSSOP−14
CASE 948G
X
A
Y
W
M
G or G
= Specific Device Code
= E = NCS333 (SOT23−5)
= H = NCS333 (SC70−5)
= G = NCS333A (SOT23−5)
= K = NCS333A (SC70−5)
= M = NCV333A (SOT23−5)
= N = NCV333A (SC70−5)
= Assembly Location
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
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2
N2333
ALYW
G
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
PIN CONNECTIONS
Single Channel Configuration
NCS333, NCS333A, NCV333A
OUT
1
VSS
2
IN+
3
IN+
1
VSS
2
IN−
3
5 VDD
4
IN−
Dual Channel Configuration
NCS2333, NCV2333
1
IN− 1
2
−
IN+ 1
3
+
VSS
4
4 OUT
SC70−5 / SC−88−5 / SOT−353−5
SOT23−5 / TSOP−5
OUT 1
5 VDD
Quad Channel Configuration
NCS4333, NCV4333
OUT 1
1
OUT 2
IN− 1
2
−
−
13 IN− 4
6
IN− 2
IN+ 1
3
+
+
12 IN+ 4
5
IN+ 2
VDD
4
IN+ 2
5
+
+
10 IN+ 3
IN− 2
6
−
−
9 IN− 3
OUT 2
7
8
VDD
7
−
+
UDFN8* / Micro8 / SOIC−8
*The exposed pad of the UDFN8 package
can be floated or connected to VSS.
14 OUT 4
11 VSS
8 OUT 3
SOIC−14 / TSSOP−14
ORDERING INFORMATION
Channels
Device
Package
Shipping †
Single
NCS333SN2T1G
SOT23−5 / TSOP−5
3000 / Tape & Reel
NCS333ASN2T1G
3000 / Tape & Reel
SC70−5 / SC−88−5 / SOT−353−5
NCS333SQ3T2G
NCS333ASQ3T2G
Dual
3000 / Tape & Reel
3000 / Tape & Reel
NCS2333MUTBG
UDFN8
3000 / Tape & Reel
NCS2333DR2G
SOIC−8
3000 / Tape & Reel
NCS2333DMR2G
MICRO−8
4000 / Tape & Reel
NCS4333DR2G
SOIC−14
2500 / Tape & Reel
NCS4333DTBR2G
TSSOP−14
2500 / Tape & Reel
Channels
Device
Package
Shipping †
Single
NCV333ASN2T1G
SOT23−5 / TSOP−5
3000 / Tape & Reel
NCV333ASQ3T2G
SC70−5 / SC−88−5 / SOT−353−5
3000 / Tape & Reel
NCV2333DR2G
SOIC−8
3000 / Tape & Reel
NCV2333DMR2G
MICRO−8
4000 / Tape & Reel
NCV4333DR2G
SOIC−14
2500 / Tape & Reel
NCV4333DTBR2G
TSSOP−14
2500 / Tape & Reel
Quad
Automotive Qualified
Dual
Quad
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
ABSOLUTE MAXIMUM RATINGS
Over operating free−air temperature, unless otherwise stated.
Parameter
Supply Voltage
Rating
Unit
7
V
INPUT AND OUTPUT PINS
Input Voltage (Note 1)
(VSS) − 0.3 to (VDD) + 0.3
V
Input Current (Note 1)
±10
mA
Output Short Circuit Current (Note 2)
Continuous
TEMPERATURE
Operating Temperature Range
−40 to +125
°C
Storage Temperature Range
−65 to +150
°C
+150
°C
Human Body Model (HBM)
±4000
V
Machine Model (MM)
±200
V
Charged Device Model (CDM)
±2000
V
100
mA
Junction Temperature
ESD RATINGS (Note 3)
OTHER RATINGS
Latch−up Current (Note 4)
MSL
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Input terminals are diode−clamped to the power−supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10 mA or less
2. Short−circuit to ground.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JEDEC standard JS−001 (AEC−Q100−002)
ESD Machine Model tested per JEDEC standard JESD22−A115 (AEC−Q100−003)
ESD Charged Device Model tested per JEDEC standard JESD22−C101 (AEC−Q100−011)
4. Latch−up Current tested per JEDEC standard: JESD78.
THERMAL INFORMATION (Note 5)
Parameter
Thermal Resistance,
Junction to Ambient
Symbol
qJA
Package
Value
Unit
°C/W
SOT23−5 / TSOP5
290
SC70−5 / SC−88−5 / SOT−353−5
425
Micro8 / MSOP8
298
SOIC−8
250
UDFN8
228
SOIC−14
216
TSSOP−14
155
5. As mounted on an 80x80x1.5 mm FR4 PCB with 650 mm2 and 2 oz (0.07 mm) thick copper heat spreader. Following JEDEC JESD/EIA 51.1,
51.2, 51.3 test guidelines
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Supply Voltage (VDD − VSS)
Specified Operating Temperature Range
NCS333
Unit
VS
1.8 to 5.5
V
TA
−40 to 105
°C
NCx333A, NCx2333, NCx4333
Input Common Mode Voltage Range
Range
−40 to 125
VCM
VSS−0.1 to VDD+0.1
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
ELECTRICAL CHARACTERISTICS: VS = 1.8 V to 5.5 V
At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
Boldface limits apply over the specified operating temperature range, guaranteed by characterization and/or design.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
NCS333, NCS333A
3.5
10
mV
NCV333A,
NCx2333, NCx4333
6.0
30
NCS333, NCS333A
0.03
0.07
NCV333A, VS = 5 V
0.03
0.14
NCx2333, VS = 5 V
0.04
0.07
NCx4333, VS = 5 V
0.095
0.19
INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Drift vs Temp
Offset Voltage Drift vs Supply
VOS
DVOS/DT
DVOS/DVS
VS = +5 V
NCS333, NCS333A
Full temperature range
0.32
5
NCV333A
TA = +25°C
0.40
5
Full temperature range
NCx2333, NCx4333
IIB
TA = +25°C
TA = +25°C
0.32
5
NCS333, NCx333A
±60
±200
NCx2333, NCx4333
±60
±400
12.6
Full temperature range
Input Offset Current
(Note 6)
Common Mode Rejection Ratio
(Note 7)
IOS
TA = +25°C
CMRR
Input Resistance
Input Capacitance
RIN
CIN
NCS333, NCx333A
±50
±400
NCx2333, NCx4333
±50
±800
111
VS = 3.3 V
118
NCS333, NCS333A,
NCx2333, NCx4333
106
123
NCV333A
103
123
VS = 5.5 V
127
Differential
180
Common Mode
90
NCS333
NCx2333, NCx4333,
NCx333A
pA
+400
VS = 1.8 V
VS = 5.0 V
mV/V
8
Full temperature range
Input Bias Current
(Note 6)
mV/°C
Differential
2.3
Common Mode
4.6
Differential
4.1
Common Mode
7.9
pA
dB
GW
pF
OUTPUT CHARACTERISTICS
AVOL
VSS + 100 mV < VO < VDD − 100 mV
Zout−OL
Output Voltage High,
Referenced to VDD
VOH
Output Voltage Low,
Referenced to VSS
VOL
Open Loop Voltage Gain
(Note 6)
Open Loop Output Impedance
145
dB
f = UGBW, IO = 0 mA
300
W
TA = +25°C
10
106
Full temperature range
TA = +25°C
Full temperature range
6. Guaranteed by characterization and/or design
7. Specified over the full common mode range: VSS − 0.1 < VCM < VDD + 0.1
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5
50
mV
70
10
50
70
mV
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
ELECTRICAL CHARACTERISTICS: VS = 1.8 V to 5.5 V
At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
Boldface limits apply over the specified operating temperature range, guaranteed by characterization and/or design.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
OUTPUT CHARACTERISTICS
Output Current Capability
IO
Sinking Current
NCS333
25
NCx333A,
NCx2333, NCx4333
11
Sourcing Current
Capacitive Load Drive
mA
5.0
CL
See Figure 13
NOISE PERFORMANCE
Voltage Noise Density
Voltage Noise
Current Noise Density
eN
fIN = 1 kHz
62
nV / √Hz
eP−P
fIN = 0.1 Hz to 10 Hz
1.1
mVPP
fIN = 0.01 Hz to 1 Hz
0.5
fIN = 10 Hz
350
fA / √Hz
NCx2333, NCx4333
135
dB
NCS333, NCx333A,
NCx4333
350
kHz
NCx2333
270
iN
Channel Separation
DYNAMIC PERFORMANCE
Gain Bandwidth Product
GBWP
CL = 100 pF
Gain Margin
AM
CL = 100 pF
18
dB
Phase Margin
fM
CL = 100 pF
55
°
Slew Rate
SR
G = +1
0.15
V/ms
dB
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
Turn−on Time
tON
Quiescent Current
(Note 8)
IQ
NCS333, NCS333A
Full temperature
range
106
130
NCx2333, NCx4333,
NCV333A
TA = +25°C
106
130
Full temperature range
98
VS = 5 V
NCS333, NCS333A,
NCx2333, NCx4333
1.8 V ≤ VS ≤ 3.3 V
100
17
ms
25
mA
27
3.3 V < VS ≤ 5.5 V
21
33
35
NCV333A
1.8 V ≤ VS ≤ 3.3 V
20
30
35
3.3 V < VS ≤ 5.5 V
28
40
45
8. No load, per channel
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
TYPICAL CHARACTERISTICS
120
100
105
GAIN (dB)
60
90
75
Gain
40
60
20
45
CL = 100 pF
RL = 10 kW
TA = 25°C
0
−20
−40
10
100
30
100
PHASE MARGIN (°)
Phase Margin
80
120
110
CMRR (dB)
120
1k
10k
100k
FREQUENCY (Hz)
1M
70
60
50
40
30
20
10
0
15
0
TA = 25°C
90
80
10
100
Figure 1. Open Loop Gain and Phase Margin
vs. Frequency
100k
1M
Figure 2. CMRR vs. Frequency
120
3
TA = 25°C
VS = 5.5 V, VOH
2
80
OUTPUT SWING (V)
100
PSRR (dB)
1k
10k
FREQUENCY (Hz)
+PSRR
60
−PSRR
40
0
VS = 1.8 V, VOL
−1
−2
0
−3
100
1k
10k
FREQUENCY (Hz)
100k
1M
VS = 1.8 V, VOH
1
20
10
TA = 25°C
VS = 5.5 V, VOL
0
Figure 3. PSRR vs. Frequency
1
2
3
4
5
6
7
OUTPUT CURRENT (mA)
8
9
Figure 4. Output Voltage Swing vs. Output
Current
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7
10
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
TYPICAL CHARACTERISTICS
200
150
100
50
IIB+
0
IIB−
−50
−100
−150
−200
−0.2 0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
1.6 1.8
100
IIB+
50
IIB−
0
−50
TA = 25°C
VS = 5 V
−100
−150
−200
−40
2.0
−20
40
60
80
100
Figure 5. Input Bias Current vs. Common
Mode Voltage
Figure 6. Input Bias Current vs. Temperature
3
2
VS = 3.3 V
1
VS = 1.8 V
10
4
Input
0
1
−1
0
VS = 5.0 V
AV = +1
RL = 10 kW
−3
Per Channel
−20
0
20
40
60
80
−4
−100
100
2
Output
−2
5
3
0
100
−1
−2
200
300
400
TEMPERATURE (°C)
TIME (ms)
Figure 7. Quiescent Current vs. Temperature
Figure 8. Large Signal Step Response
0.20
1.0
0.15
0.5
Input
0
0.05
VS = 5.0 V
AV = −1
RL = 10 kW
0
−0.05
INPUT (V)
0.10
3.0
2.5
Input
−0.5
−1.0
−1.5
−3
Output
2.0
VS = 5.0 V
AV = −10
RL = 10 kW
OUTPUT (V)
15
VS = 5.0 V
INPUT (V)
20
5
4
25
INPUT AND OUTPUT (V)
20
TEMPERATURE (°C)
VS = 5.5 V
0
−40
0
COMMON MODE VOLTAGE (V)
30
IQ (mA)
150
OUTPUT (V)
TA = 25°C
VS = 1.8 V
INPUT BIAS CURRENT (pA)
INPUT BIAS CURRENT (pA)
200
1.5
1.0
0.5
−2.0
0
−0.10
−2.5
−0.5
−0.15
−10
−3.0
−1.0
Output
0
10
20
30
TIME (ms)
TIME (50 ms/div)
Figure 9. Small Signal Step Response
Figure 10. Positive Overvoltage Recovery
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8
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
TYPICAL CHARACTERISTICS
1.0
2.5
0.5
Output
INPUT (V)
2.0
0
1.5
500
400
−0.5
VS = 5.0 V
AV = −10
RL = 10 kW
1.0
0.5
Input
0
−2.0
−3.0
100
0
1
10
100
TIME (50 ms/div)
GAIN (V/V)
Figure 11. Negative Overvoltage Recovery
Figure 12. Setting Time to 0.1% vs.
Closed−Loop Gain
2000
VCM = VS/2
RL = 10 kW
TA = 25°C
1500
TA = 25°C
VOLTAGE (nV)
1000
500
0
−500
−1000
−1500
10
100
−2000
1000
1
2
3
4
5
6
7
8
TIME (s)
Figure 13. Small−Signal Overshoot vs. Load
Capacitance
Figure 14. 0.1 Hz to 10 Hz Noise
1000
TA = 25°C
100
1
0
LOAD CAPACITANCE (pF)
CURRENT NOISE DENSITY (fA/√Hz)
OVERSHOOT (%)
−1.0
VOLTAGE NOISE DENSITY (nV/√Hz)
200
−1.5
−2.5
10
300
−1.0
−0.5
65
60
55
50
45
40
35
30
25
20
15
10
5
0
TA = 25°C
RL = 10 kW
OUTPUT (V)
SETTLING TIME (ms)
3.0
10
100
1000
10,000
10
1000
TA = 25°C
100
10
1
10
100
1000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15. Voltage Noise Density vs.
Frequency
Figure 16. Current Noise Density vs.
Frequency
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9
9
10,000
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
APPLICATIONS INFORMATION
OVERVIEW
The NCS333, NCS333A, NCS2333, and NCS4333
precision op amps provide low offset voltage and zero drift
over temperature. The input common mode voltage range
extends 100 mV beyond the supply rails to allow for sensing
near ground or VDD. These features make the NCS333
series well−suited for applications where precision is
required, such as current sensing and interfacing with
sensors.
NCS333 series of precision op amps uses a
chopper−stabilized architecture, which provides the
advantage of minimizing offset voltage drift over
temperature and time. The simplified block diagram is
shown in Figure 17. Unlike the classical chopper
architecture, the chopper stabilized architecture has two
signal paths.
Main amp
IN+
+
IN−
− +
+
−
Chopper
−
O
−
+
Chopper
RC notch filter
RC notch filter
Figure 17. Simplified NCS333 Block Diagram
cascaded, symmetrical, RC notch filters tuned to the
chopper frequency and its fifth harmonic to reduce aliasing
effects.
The chopper−stabilized architecture also benefits from
the feed−forward path, which is shown as the upper signal
path of the block diagram in Figure 17. This is the high speed
signal path that extends the gain bandwidth up to 350 kHz.
Not only does this help retain high frequency components of
the input signal, but it also improves the loop gain at low
frequencies. This is especially useful for low−side current
sensing and sensor interface applications where the signal is
low frequency and the differential voltage is relatively
small.
In Figure 17, the lower signal path is where the chopper
samples the input offset voltage, which is then used to
correct the offset at the output. The offset correction occurs
at a frequency of 125 kHz. The chopper−stabilized
architecture is optimized for best performance at
frequencies up to the related Nyquist frequency (1/2 of the
offset correction frequency). As the signal frequency
exceeds the Nyquist frequency, 62.5 kHz, aliasing may
occur at the output. This is an inherent limitation of all
chopper
and
chopper−stabilized
architectures.
Nevertheless, the NCS333 op amps have minimal aliasing
up to 125 kHz and low aliasing up to 190 kHz when
compared to competitor parts from other manufacturers.
ON Semiconductor’s patented approach utilizes two
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10
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
APPLICATION CIRCUITS
sense resistor is less than 100 mW to reduce power loss
across the resistor. The op amp amplifies the voltage drop
across the sense resistor with a gain set by external resistors
R1, R2, R3, and R4 (where R1 = R2, R3 = R4). Precision
resistors are required for high accuracy, and the gain is set
to utilize the full scale of the ADC for the highest resolution.
Low−Side Current Sensing
Low−side current sensing is used to monitor the current
through a load. This method can be used to detect
over−current conditions and is often used in feedback
control, as shown in Figure 18. A sense resistor is placed in
series with the load to ground. Typically, the value of the
R3
VLOAD
VDD
VDD
Load
R1
VDD
Microcontroller
+
ADC
RSENSE
control
−
R2
R4
Figure 18. Low−Side Current Sensing
Differential Amplifier for Bridged Circuits
produced is relatively small and needs to be amplified before
going into an ADC. Precision amplifiers are recommended
in these types of applications due to their high gain, low
noise, and low offset voltage.
Sensors to measure strain, pressure, and temperature are
often configured in a Wheatstone bridge circuit as shown in
Figure 19. In the measurement, the voltage change that is
VDD
VDD
−
+
Figure 19. Bridge Circuit Amplification
EMI Susceptibility and Input Filtering
General Layout Guidelines
Op amps have varying amounts of EMI susceptibility.
Semiconductor junctions can pick up and rectify EMI
signals, creating an EMI−induced voltage offset at the
output, adding another component to the total error. Input
pins are the most sensitive to EMI. The NCS333 op amp
family integrates low−pass filters to decrease sensitivity to
EMI.
To ensure optimum device performance, it is important to
follow good PCB design practices. Place 0.1 mF decoupling
capacitors as close as possible to the supply pins. Keep traces
short, utilize a ground plane, choose surface−mount
components, and place components as close as possible to
the device pins. These techniques will reduce susceptibility
to electromagnetic interference (EMI). Thermoelectric
effects can create an additional temperature dependent
offset voltage at the input pins. To reduce these effects, use
metals with low thermoelectric−coefficients and prevent
temperature gradients from heat sources or cooling fans.
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11
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
UDFN8 Package Guidelines
center pad can be electrically connected to VSS or it may be
left floating. When connected to VSS, the center pad acts as
a heat sink, improving the thermal resistance of the part.
The UDFN8 package has an exposed leadframe die pad on
the underside of the package. This pad should be soldered to
the PCB, as shown in the recommended soldering footprint
in the Package Dimensions section of this datasheet. The
www.onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
SCALE 2:1
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DATE 17 JAN 2013
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
B
M
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
J
GENERIC MARKING
DIAGRAM*
C
K
H
XXXMG
G
SOLDER FOOTPRINT
0.50
0.0197
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
mm Ǔ
ǒinches
STYLE 1:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 2:
PIN 1. ANODE
2. EMITTER
3. BASE
4. COLLECTOR
5. CATHODE
STYLE 3:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. CATHODE 1
STYLE 4:
PIN 1. SOURCE 1
2. DRAIN 1/2
3. SOURCE 1
4. GATE 1
5. GATE 2
STYLE 6:
PIN 1. EMITTER 2
2. BASE 2
3. EMITTER 1
4. COLLECTOR
5. COLLECTOR 2/BASE 1
STYLE 7:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 8:
PIN 1. CATHODE
2. COLLECTOR
3. N/C
4. BASE
5. EMITTER
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42984B
STYLE 5:
PIN 1. CATHODE
2. COMMON ANODE
3. CATHODE 2
4. CATHODE 3
5. CATHODE 4
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SC−88A (SC−70−5/SOT−353)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
NOTE 5
2X
DATE 12 AUG 2020
0.20 C A B
0.10 T
M
2X
0.20 T
5
B
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
C
SIDE VIEW
SEATING
PLANE
END VIEW
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
1.9
0.074
5
5
XXXAYWG
G
1
1
Analog
2.4
0.094
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1.0
0.039
XXX MG
G
Discrete/Logic
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN8, 2x2
CASE 517AW
ISSUE A
1
SCALE 2:1
ÇÇ
ÇÇ
E
DETAIL A
ALTERNATE
CONSTRUCTIONS
0.10 C
2X
L
L
L1
PIN ONE
REFERENCE
2X
B
A
D
DATE 13 NOV 2015
0.10 C
TOP VIEW
DETAIL B
A
0.10 C
A3
A1
0.08 C
A1
SIDE VIEW
NOTE 4
C
D2
DETAIL A
1
8X
4
SEATING
PLANE
5
e
e/2
A3
ALTERNATE
CONSTRUCTION
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.18
0.30
2.00 BSC
1.50
1.70
2.00 BSC
0.80
1.00
0.50 BSC
0.20
0.45
−−−
0.15
GENERIC
MARKING DIAGRAM*
8X
1
b
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
1.73
PACKAGE
OUTLINE
DETAIL B
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
L
E2
8
ÇÇ
ÇÇ
ÉÉ
MOLD CMPD
EXPOSED Cu
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINALS AND IS MEASURED BETWEEN 0.15
AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. FOR DEVICE OPN CONTAINING W OPTION,
DETAIL B ALTERNATE CONSTRUCTION IS
NOT APPLICABLE.
8X
0.50
XX MG
G
XX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
2.30
1.00
1
8X
0.50
PITCH
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34462E
UDFN8, 2X2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
8
XXXX
AYWG
G
1
XXXX
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14087C
MICRO8
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
N-SOURCE
N-GATE
P-SOURCE
P-GATE
P-DRAIN
P-DRAIN
N-DRAIN
N-DRAIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
G
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
98ASH70246A
DESCRIPTION:
TSSOP−14 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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