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NCS2211, NCV2211
Low Distortion Audio Power
Amplifier with Differential
Output and Shutdown Mode
Product Description
http://onsemi.com
The NCS2211 is a high performance, low distortion Class A/B
audio amplifier. It is capable of delivering 1 W of output power into an
8 W speaker bridge−tied load (BTL). The NCS2211 will operate over a
wide temperature range, and it is specified for single−supply voltage
operation for portable applications.
It features low distortion performance, 0.2% typical THD + N @
1 W and incorporates a shutdown/enable feature to extend battery life.
The shutdown/enable feature will reduce the quiescent current to 1 mA
maximum.
The NCS2211 is designed to operate over the −40°C to +85°C
temperature range, and is available in an 8−lead SOIC package and a
3 X 3 mm DFN8 package. The SOIC package is pin compatible with
equivalent function and comparable performance to competitive
devices as is the DFN8 package. The DFN8 has a low thermal
resistance of only 70°C/W plus has an exposed metal pad to facilitate
heat conduction to copper PCB material.
Low distortion, high power, low quiescent current, and small
packaging makes the NCS2211 suitable for applications including
notebook and desktop computers, PDA’s, and speaker phones.
MARKING
DIAGRAMS
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
N2211
ALYWG
G
1
DFN8
MN SUFFIX
CASE 506BJ
1
8
N2211
ALYWG
G
N2211 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
Features
•
•
•
•
•
•
•
•
•
•
•
•
Differential Output
1.0 W into an 8 W Speaker
1.5 W into a 4 W Speaker
Single Supply Operation: 2.7 V to 5.5 V
THD+N: 0.2% @ 1 W Output
Low Quiescent Current: 20 mA Max
Shutdown Current < 1.0 mA
Excellent Power Supply Rejection
Two Package Options: SOIC−8 Package and DFN8
Pin Compatible with Competitive Devices
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
PIN ASSIGNMENT
PIN
NAME
DESCRIPTION
1
Enable
Enable (LOW)/Shutdown (HIGH)
2
Bias
Bias Output at (VCC−VEE)/2;
Bypass with Capacitor to
Reduce Noise
3
IN+
Non−Inverting Input
4
IN−
Inverting Input
5
OUT+
6
VCC
Positive Supply (Bypass with
10 mF in parallel with 0.1 mF)
7
VEE
Negative Supply (Connect to GND
for Single−Supply Operation)
8
OUT−
Output+
Output−
Applications
•
•
•
•
•
ORDERING INFORMATION
Desktop Computers
Notebook Computers
PDA’s
Speaker Phones
Games
© Semiconductor Components Industries, LLC, 2014
May, 2014 − Rev. 3
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
1
Publication Order Number:
NCS2211/D
NCS2211, NCV2211
PIN CONNECTIONS for SOIC−8 and DFN8
Enable
1
8 OUT−
Bias
2
7 VEE
IN+
3
6 VCC
IN−
4
5 OUT+
(Top View)
VCC 6
R2
R
C1
R1
4
−
+
(−) Input
5
3
R
Bias
Filtering
R
Output (+)
(+) Input
RL
−
+
8
Output (−)
2
R
C2
1 Enable
7
VEE
Figure 1. Block Diagram
Enable (Note 1)
High
Low
Shutdown
Enabled
1. Enable (pin 1) must be actively driven for proper operation and cannot be left floating. See ENABLE/SHUTDOWN CONTROL in the specification table for proper logic threshold levels.
MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
VCC
5.5
Vdc
Output Current
IO
500
mA
Maximum Junction Temperature (Note 2)
TJ
150
°C
Operating Ambient Temperature
TA
−40 to +85
°C
Storage Temperature Range
Tstg
−60 to +150
°C
Power Dissipation
PD
(See Graph)
mW
Thermal Resistance, Junction−to−Air − SOIC−8
Thermal Resistance, Junction−to−Air − DFN8 (Note 4)
qJA
117
70
°C/W
Power Supply Voltages
Moisture Sensitivity (Note 3)
Level 1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded.
3. For additional information, see Application Note AND8003/D
4. As mounted on an 80x80x1.5 mm FR4 PCB with 650 mm2 and 2 oz (0.034 mm) thick copper heat spreader. Following JEDEC JESD/EIA
51.1, 51.2, 51.3 test guidelines.
http://onsemi.com
2
NCS2211, NCV2211
DC ELECTRICAL CHARACTERISTICS (VCC = +5 V, AVD = 2, RL = 8 W, C2 = 0.1 mF, TA = 25°C, unless otherwise specified)
Symbol
Characteristics
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
VCC
Operating Voltage
Range
2.7
IS, ON
Power Supply Current
− Enabled
VCC = 2.7 V to 5.5 V
TA = −40°C to +85°C (Note 5)
IS, OFF
Power Supply Current
− Shutdown
VCC = 2.7 V to 5.5 V
PSRR
Power Supply
Rejection Ratio
VCC = 2.7 V to 5.5 V
TA = −40°C to +85°C
V
5.5
20
mA
mA
1.0
dB
75
ENABLE/SHUTDOWN CONTROL
VIH
Enable Input High
Device Shutdown
VCC = 2.7 V to 5.5 V
90% X VCC
VCC
VIL
Enable Input Low
Device Enabled
VCC = 2.7 V to 5.5 V
GND
10% x VCC
V
V
OUTPUT CHARACTERISTICS
VOH
Output High Voltage
From Either Output to GND
RL = 8 W
VCC − 0.400
VOL
Output Low Voltage
From Either Output to GND
RL = 8 W
0.400
Vout −off
IO
Differential Output
Offset Voltage
V
V
VCC = 2.7 V to 5.5 V (Note 5)
TA = −40°C to +85°C
Output Current
Output to Output
$50
350
mV
mA
AC ELECTRICAL CHARACTERISTICS (VCC = +5 V, AVD = 2, RL = 8 W, C2 = 0.1 mF, TA = 25°C, unless otherwise specified)
Symbol
Characteristics
Conditions
Min
Typ
Max
Unit
FREQUENCY DOMAIN PERFORMANCE
GBW
Gain Bandwidth Product
12
MHz
AVD = +2, RL = 8 W, VCC = 5 V
80
°
VCC = 5 V, f = 1 kHz, P = 1.0 W into 8 W
VCC = 5 V, f = 1 kHz, P = 0.5 W into 8 W
VCC = 3.3 V, f = 1 kHz, P = 0.35 W into 8 W
VCC = 2.7 V, f = 1 kHz, P = 0.25 W into 8 W
0.2
0.15
0.1
0.1
%
Phase Margin
THD+N
Total Harmonic Distortion
TIME DOMAIN RESPONSE
tON
Turn on delay
VCC = 5 V
1
ms
tOFF
Turn off delay
VCC = 5 V
4
ms
5. Guaranteed by design and/or characterization.
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3
NCS2211, NCV2211
TYPICAL PERFORMANCE CHARACTERISTICS
1
TA = 25°C
VCC = 5.0 V
AVD = 2 (BTL)
RL = 8 W
TA = 25°C
VCC = 5.0 V
AVD = 2 (BTL)
RL = 8 W
THD + N (%)
THD + N (%)
1
C2 = 0.1 mF
0.1
C2 = 1.0 mF
0.01
C2 = 0.1 mF
0.1
C2 = 1.0 mF
0.01
20
100
1k
10 k
20
FREQUENCY (Hz)
Figure 2. THD + N vs. Frequency
(PL = 500 mW)
Figure 3. THD + N vs. Frequency
(PL = 1 W)
10 k
10
TA = 25°C
VCC = 5.0 V
AVD = 10 (BTL)
RL = 8 W
THD + N (%)
TA = 25°C
VCC = 5.0 V
AVD = 10 (BTL)
RL = 8 W
THD + N (%)
1k
FREQUENCY (Hz)
10
1
100
C2 = 0.1 mF
C2 = 0.1 mF
1
C2 = 1.0 mF
0.1
C2 = 1.0 mF
0.1
20
100
1k
10 k
20
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 4. THD + N vs. Frequency
(PL = 500 mW)
Figure 5. THD + N vs. Frequency
(PL = 1 W)
10
10 k
10
TA = 25°C
VCC = 5.0 V
AVD = 20 (BTL)
RL = 8 W
C2 = 0.1 mF
THD + N (%)
THD + N (%)
100
C2 = 0.1 mF
1
TA = 25°C
VCC = 5.0 V
AVD = 20 (BTL)
RL = 8 W
1
C2 = 1.0 mF
C2 = 1.0 mF
0.1
0.1
20
100
1k
10 k
20
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6. THD + N vs. Frequency
(PL = 500 mW)
Figure 7. THD + N vs. Frequency
(PL = 1 W)
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4
10 k
NCS2211, NCV2211
TYPICAL PERFORMANCE CHARACTERISTICS
1
TA = 25°C
VCC = 3.3 V
AVD = 2 (BTL)
RL = 8 W
TA = 25°C
VCC = 2.7 V
AVD = 2 (BTL)
RL = 8 W
THD + N (%)
THD + N (%)
1
C2 = 0.1 mF
0.1
C2 = 0.1 mF
0.1
C2 = 1.0 mF
C2 = 1.0 mF
0.01
0.01
20
100
1k
10 k
20
FREQUENCY (Hz)
Figure 8. THD + N vs. Frequency
(PL = 350 mW)
Figure 9. THD + N vs. Frequency
(PL = 250 mW)
THD + N (%)
THD + N (%)
C2 = 0.1 mF
TA = 25°C
VCC = 2.7 V
AVD = 10 (BTL)
RL = 8 W
1
C2 = 0.1 mF
0.1
C2 = 1.0 mF
C2 = 1.0 mF
0.01
0.01
20
100
1k
10 k
20
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 10. THD + N vs. Frequency
(PL = 350 mW)
Figure 11. THD + N vs. Frequency
(PL = 250 mW)
10
10 k
10
C2 = 0.1 mF
TA = 25°C
VCC = 3.3 V
AVD = 20 (BTL)
RL = 8 W
C2 = 0.1 mF
1
THD + N (%)
THD + N (%)
10 k
10
TA = 25°C
VCC = 3.3 V
AVD = 10 (BTL)
RL = 8 W
0.1
0.1
1k
FREQUENCY (Hz)
10
1
100
C2 = 1.0 mF
0.1
1
TA = 25°C
VCC = 2.7 V
AVD = 20 (BTL)
RL = 8 W
0.1 C2 = 1.0 mF
0.01
20
100
1k
10 k
20
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 12. THD + N vs. Frequency
(PL = 350 mW)
Figure 13. THD + N vs. Frequency
(PL = 250 mW)
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5
10 k
NCS2211, NCV2211
TYPICAL PERFORMANCE CHARACTERISTICS
1.50
THD + N (%)
10
TA = 25°C
C2 = 0.1 mF
AVD = 2 (BTL)
RL = 8 W
STEADY STATE POWER (W)
100
VCC = 2.7 V
VCC = 5.0 V
VCC = 3.3 V
1
0.1
0.0001 0.001
0.01
0.1
1
8 Lead DFN −
150 mm2
1.00
SOIC−8 −
650 mm2
0.75
0.50
8 Lead
DFN − 50 mm2
0.25 SOIC−8 − 150 mm2
25
10
75
100
125
150
Figure 14. THD + N vs. POUTPUT
(Frequency = 20 Hz)
Figure 15. SOA Curve with PCB Copper
Thickness 2 oz and Various Areas
2.0
TA = 25°C
C2 = 0.1 mF
AVD = 2 (BTL)
RL = 8 W
1.8
VCC = 2.7 V
1.6
VCC = 5.0 V
1.4
Pout (W)
VCC = 5.0 V
VCC = 3.3 V
1.2
1.0
0.8
0.6
0.1
0.4
VCC = 3.3 V
0.2
0.01
VCC = 2.7 V
0
0.0001 0.001
0.01
0.1
1
10
4
8
12
16
20
24
28
32
36
40
POUTPUT (W)
LOAD RESISTANCE (W)
Figure 16. THD + N vs. POUTPUT
(Frequency = 1 kHz)
Figure 17. Pout vs. Load Resistance
TA = 25°C
C2 = 0.1 mF
AVD = 2 (BTL)
RL = 8 W
INTERNAL POWER DISSIPATION (W)
100
THD + N (%)
50
T−AMBIENT (°C)
1
10
SOIC−8 −
50 mm2
POUTPUT (W)
100
THD + N (%)
1.25
0
0.01
10
8 Lead DFN − 650 mm2
VCC = 2.7 V
VCC = 5.0 V
VCC = 3.3 V
1
0.1
0.01
0.0001 0.001
0.01
0.1
1
VCC = 5 V
1.2
RL = 4 W
1.0
0.8
0.6
RL = 8 W
0.4
0.2
0
0.5
1.0
1.5
POUTPUT (W)
OUTPUT POWER (W)
Figure 18. THD + N vs. POUTPUT
(Frequency = 20 kHz)
Figure 19. Power Dissipation vs. Output
Power
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6
48
1.4
0
10
44
2.0
NCS2211, NCV2211
TYPICAL PERFORMANCE CHARACTERISTICS
Channel 1: Enable Logic
and OUT+ and OUT−
Channel 2: Differential
Output
Time Base: 1 mSec per
Division
Figure 20. Turn−on Time
Channel 1: SHUTDOWN
Logic and OUT+ and OUT−
Channel 2: Differential
Output
Time Base: 5 mSec per
Division
Figure 21. Turn−off Time
80
135
60
90
40
45
20
0
GAIN (dB)
180
−45
0
−20
10
100
1k
10 k
100 k
1M
10 M
−90
100 M
FREQUENCY (Hz)
Figure 22. Gain and Phase Shift vs. Frequency
http://onsemi.com
7
PHASE SHIFT (degrees)
100
NCS2211, NCV2211
TYPICAL PERFORMANCE CHARACTERISTICS
+0
VCC = 5 V
RL = 8 W
Rf = Rg = 20 kW
Avd = 1
Cbypass = 10 mF ⎢⎢ 0.1 mF
C2 = 0.1 mF
Ripple = 200 mVp−p
−10
−20
−30
−40
(dB)
−50
−60
−70
−80
−90
−100
−110
−120
10
100
1k
FREQUENCY OF POWER−SUPPLY RIPPLE (Hz)
Figure 23. Power−Supply Rejection
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8
10 k
NCS2211, NCV2211
APPLICATIONS INFORMATION
The NCS2211 is unity gain stable and therefore does not
require any compensation, but a proper power−supply
bypass is required as shown in Figure 24. Performance will
be enhanced by adding a filter capacitor (C2) to the
mid−supply node (pin 2). See Typical Performance
Characteristics for details.
It is preferable to AC couple the input to avoid a large
DC output offset.
Both outputs can be driven to within 400 mV of either
supply rail with an 8 W load.
Typical Application of the Device:
+5 V
VCC
R1
C1 20k
(−) Input
0.1 mF
6
C3
10 mF⎟⎟ 0.1 mF
R2
20k
4
−
+
5
Output (+)
3
2 VPP
RL
(+) Input
Bias
Filtering
−
+
8
Output (−)
2
C2
0.1 mF
7
1
Enable
VEE
Figure 24.
THERMAL CONSIDERATIONS
GAIN
Care must be taken to not exceed the maximum junction
temperature of the device (150°C). Figure 15 shows the
tradeoff between output power and junction temperature for
different areas of exposed PCB copper (2 oz). If the
maximum power is exceeded momentarily, normal circuit
operation will be restored as soon as the die temperature is
reduced. Leaving the device in an “overheated” condition
for an extended period can result in device burnout. To
ensure proper operation, it is important to observe the SOA
curves.
Since the output is differential, the gain from input to the
speaker is: AVD = 2 x R2/R1. For low level input signals,
THD will be optimized by pre−amplifying the signal and
running the NCS2211 at gain AVD = 2 and C2=1 mF.
BIAS FILTERING
Even though the NCS2211 will operate nominally with no
filter capacitor on pin 2, THD performance will be improved
dramatically with a filter capacitor installed (see Typical
Performance Characteristics). In addition a C2 filter
capacitor at pin 2 will suppress start−up popping noise. To
insure optimal suppression the time constant of the bias
filtering needs to be greater than the time constant of the
input capacitive coupling circuit, that is C2 x 25 k > C1 x R1.
ORDERING INFORMATION
Device
NCS2211DR2G
NCV2211DR2G*
NCS2211MNTXG
Package
Shipping†
SOIC−8
(Pb−Free)
2500 / Tape & Reel
DFN−8
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 3x3, 0.5P
CASE 506BJ−01
ISSUE O
1
SCALE 2:1
PIN 1
REFERENCE
2X
0.10 C
2X
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
0.10 C
EDGE OF PACKAGE
A
B
D
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30
MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L1
DETAIL A
E
OPTIONAL
CONSTRUCTION
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
L
TOP VIEW
DETAIL A
OPTIONAL
CONSTRUCTION
DETAIL B
0.05 C
DATE 08 NOV 2007
A
8X
0.05 C
NOTE 4
8X
8X
(A3)
SIDE VIEW
A1
D2
L
1
C
DETAIL A
4
8
5
e
8X
ÉÉ
ÉÉ
1
MOLD CMPD
DETAIL B
E2
K
GENERIC
MARKING DIAGRAM*
SEATING
PLANE
EXPOSED Cu
OPTIONAL
CONSTRUCTION
b
0.10 C A B
BOTTOM VIEW
0.05 C
NOTE 3
SOLDERMASK DEFINED
MOUNTING FOOTPRINT
1.85
8X
0.35
8X
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.64
1.84
3.00 BSC
1.35
1.55
0.50 BSC
0.20
−−−
0.30
0.50
0.00
0.03
XXXXX
XXXXX
ALYWG
G
8
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
3.30
1.55
0.63
0.50
PITCH
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON25786D
DFN8 3X3, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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