NCS6416
Low-V oltage,
Bus-Contr olled Video
Matrix Switch
Description
The main function of the NCS6416 is to switch 8 video input
sources to the 6 outputs. The NCS6416 operates with a low 5 V power
supply.
Each output can be switched to only one of the inputs, whereas any
single input may be connected to several outputs.
All switching possibilities are controlled through the I2C bus inputs.
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MARKING DIAGRAMS*
20
20
NCS6416
AWLYYWWG
1
Features
•20 MHz Bandwidth
•5 V Operating Voltage
•Cascadable with another NCS6416 (Internal Address can be changed
by Pin 7 Voltage)
•8 Inputs (CVBS, RGB, Chroma, ...)
•6 Outputs with 150 Output Driving Capability
•Possibility of Chroma Signal for each Input by Switching off the
Clamp with an External Resistor Bridge
•Bus Controlled
•6 dB Gain between any Input and Output
•-65 dB Crosstalk at 5 MHz
•Full ESD Protection
•These are Pb-Free Devices
SO-20 WB
DW SUFFIX
CASE 751D
A
WL
YY
WW
G
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
INPUT1 1
20 INPUT8
DATA1 2
19 VCCO
INPUT2 3
18 OUTPUT6
CLOCK 4
17 OUTPUT5
INPUT3 5
16 OUTPUT4
INPUT4 6
15 OUTPUT3
PROG 7
14 OUTPUT2
INPUT5 8
13 OUTPUT1
12 GND
VCC 9
INPUT6 10
11 INPUT7
ORDERING INFORMATION
Package
Shipping†
NCS6416DWG
SO-20
(Pb-Free)
38 Units / Rail
NCS6416DWR2G
SO-20
(Pb-Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2007
June, 2007 - Rev. 1
1
Publication Order Number:
NCS6416/D
NCS6416
OUTPUT6
OUTPUT4
OUTPUT2
OUTPUT5
OUTPUT3
OUTPUT1
GND
18
INPUT1
1
INPUT2
3
INPUT3
5
INPUT4
6
INPUT5
8
INPUT6
10
INPUT7
11
INPUT8
20
17
16
15
14
13
12
NCS6416
Bus Decoder
2
7
4
9
19
DATA
PROG
CLOCK
VCC
VCCO
Figure 1. Block Diagram
The main function of the NCS6416 is to switch 8 video
input sources to the 6 outputs.
Each output can be switched to only one of the inputs,
whereas any single input may be connected to several
outputs. The lowest level of each signal is aligned on each
input (bottom of sync pulse for CVBS or Black Level for
RGB signals). Each output is able to drive a 150 load.
The nominal gain between any input and output is 6 dB.
For Chroma signals, the clamp is switched off by forcing an
external 2.5 V DC resistor bridge on the input. Each input
can be used as a normal input or as a Chroma input (with
external resistor bridge). All the switching possibilities are
changed through the I2C bus.
The switches configuration is defined by words of 16 bits:
one word of 16 bits for each output channel.
So, 6 words of 16 bits are necessary to determine the
starting configuration upon power-on (power supply: 0 to
5 V). But a new configuration needs only the words of the
changed output channels.
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2
NCS6416
Table 1. ATTRIBUTES
Characteristics
ESD
Value
Human Body Model
Machine Model
2 kV
200 V
Moisture Sensitivity (Note 1)
Flammability Rating
Level 3
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in.
1. For additional information, see Application Note AND8003/D
Table 2. MAXIMUM RATINGS
Parameter
Power Supply Voltage
Output Driver Power Supply
Symbol
Rating
Unit
VCC
6
V
VCCO
6
V
Operating Temperature Range
TA
0 to +70
°C
Storage Temperature Range
Tstg
-60 to +150
°C
Thermal Resistance, Junction-to-Air
SO-20
°C/W
JA
30 to 35
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. DC & AC Characteristics (TA = 25°C, VCC = 5 V, RL = 150 , CL = 3 pF)
Symbol
Parameter
Min
Typ
Max
Unit
V
VCC
Supply Voltage
4.75
5.0
5.25
VCCO
Output Driver Power Supply
4.75
5.0
5.25
V
ICC
Power Supply Current (No Load)
20
30
40
mA
INPUTS
Signal Amplitude (CVBS signal) (Note 2)
1.0
Input Current (Per Output Connected)
DC Level (Bottom of Sync Pulse)
1.25
VPP
1
3
A
1.35
1.45
V
100
DC Level Shift (0°C to 70°C) (Note 2)
5
RIN
Input Resistance (Note 2)
1
M
mV
CIN
Input Capacitance (Note 2)
2
pF
OUTPUTS
Dynamic Range (VIN = 1 VPP) (Note 2)
1.9
Output Impedance (Note 2)
AV
Gain (Note 2)
BW
Bandwidth (Note 2)
-1 dB Attenuation
-3 dB Attenuation
2.0
2.1
1
5.5
6.0
VPP
6.5
dB
MHz
7
15
20
DG
Differential Gain Error (Note 2)
DP
Differential Phase Error (Note 2)
1.5
Crosstalk (f = 5 MHz) (Note 2)
-65
-60
dB
0.3
0.4
V
I2C
0.5
DC Level (Bottom of Sync Pulse)
0.2
Continuous Output Current (Note 2)
20
%
°
mA
BUS INPUT: DATA, CLOCK AND PROG
Threshold Voltage (Note 2)
1.5
2. Guaranteed by design and/or characterization.
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3
2
3
V
NCS6416
Table 4. I2C BUS CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Max
Unit
SCL
VIL
Low Level Input Voltage
-0.3
+1.5
V
VIH
High Level Input Voltage
3.0
VCC +0.5
V
ILI
Input Leakage Current
-10
+10
A
fSCL
Clock Frequency (Note 3)
0
100
kHz
tR
Input Risetime (Note 3)
1.5 V to 3 V
1000
ns
tF
Input Falltime (Note 3)
3 V to 1.5 V
300
ns
CI
Input Capacitance (Note 3)
10
pF
VI = 0 to VCC
SDA
VIL
Low Level Input Voltage
-0.3
+1.5
V
VIH
High Level Input Voltage
3.0
VCC +0.5
V
ILI
Input Leakage Current
-10
+10
A
CI
Input Capacitance (Note 3)
10
pF
tR
Input Risetime (Note 3)
1.5 V to 3 V
1000
ns
tF
Input Falltime (Note 3)
3 V to 1.5 V
300
ns
VOL
Low Level Output Voltage
IOL = 3 mA
0.4
V
tF
Output Falltime (Note 3)
3V to 1.5 V
250
ns
CL
Load Capacitance (Note 3)
400
pF
VI = 0 to VCC
TIMING
tLOW
Clock Low Period (Note 4)
4.7
s
tHIGH
Clock High Period (Note 4)
4.0
s
tSU,DAT
Data Setup Time (Note 4)
250
ns
tHD,DAT
Data Hold Time (Note 4)
0
tSU,STO
Setup Time from Clock High to Stop (Note 4)
4.0
s
tBUF
Start Setup Time following a Stop (Note 4)
4.7
s
tHD,STA
Start Hold Time (Note 4)
4.0
s
tSU,STA
Start Setup Time following Clock Low to High Transition
(Note 4)
4.7
s
3. Guaranteed by design and/or characterization.
4. Functionality guaranteed by design and/or characterization.
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4
340
ns
NCS6416
Bus Selections
The I2C chip address is defined by the first byte. The second byte defines the input/output configuration.
Table 5. CHIP ADDRESS BYTE (1ST BYTE OF TRANSMISSION)
NOTE:
HEX
BINARY
Comment
86
1000 0110
When PROG pin is connected to Ground
06
0000 0110
When PROG pin is connected to VCC
Input/Output Selection Byte (2nd byte of transmission)
Table 6. I2C BUS OUTPUT SELECTIONS
Output Address (MSB)
Input Address (LSB)
Selected Output
00000
XXX
Pin 18
00100
XXX
Pin 14
00010
XXX
Pin 16
00110
-
Not Used
00001
XXX
Pin 17
00101
XXX
Pin 13
00011
XXX
Pin 15
00111
-
Not Used
Output is selected by the 5 MSBs
Table 7. I2C BUS INPUT SELECTIONS
Output Address (MSB)
Input Address (LSB)
Selected Input
00XXX
000
Pin 5
00XXX
100
Pin 8
00XXX
010
Pin 3
00XXX
110
Pin 20
00XXX
001
Pin 6
00XXX
101
Pin 10
00XXX
011
Pin 1
00XXX
111
Pin 11
Input is selected by the 3 LSBs
Example: 0010 0101 (Binary) or 25 (Hex) connects Pin 10 (input) to Pin 14 (output)
SDA
tBUF
tSU.DAT
tLOW
SCL
tR
tHD.STA
tHD.DAT tHIGH
SDA
tSU.STA
Figure 2.
I2C
Bus Timing Diagram
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5
tF
tSU.STO
NCS6416
Pins 1, 3,
5, 6, 8, 10,
11 and 20
VCCO
Video
Inputs
Input Clamp
+
75 Z = 75
75
Video Inputs
+DC
To Switch
Matrix
ESD Protection
Input Buffer
Video
Output
75
NCS6416
Figure 3. Input Configuration
Figure 4. Output Configuration
Pins 2, 4, 7
I2C Bus Inputs
I2C Decode Logic
Input Buffer
ESD Protection
ACK
*For Pin 2
(SDA)
Figure 5. Bus I/O Configuration
USING A SECOND NCS6416
The programming input pin (PROG) allows two NCS6416 circuits to operate in parallel and to select them independently
through the I2C bus by modifying the address byte. Consequently, the switching capabilities are doubled, or can be cascaded
as shown in Figure 6.
NCS6416
SDA/SCL
Logical “0”
MCU
PROG
Video Inputs
Video Outputs
NCS6416
SDA/SCL
Logical “1”
Video Inputs
Figure 6. Cascaded NCS6416
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6
PROG
Video Outputs
NCS6416
TYPICAL APPLICATION DIAGRAM
NCS6416 is suited for single supply system, running on
a single +5 V supply. It can drive a 150 video output due
to the built-in low impedance and high current video output
stage. The high quality of the output stage and excellent
linearity provides video signal comparable to broadcast
studio quality signals. The layout is not as critical to the
design and it can be easily realized on a single sided board.
Additional Video Inputs
Satellite TV
receiver
circuit
Outpu 1
1 Input 1
3
5
6
8
10
11
20 Input 8
Additional Video Outputs
SCL
Prog
SDA
Bus
Decoder
HDTV
Receiver
circuit
Screen
VCR
NCS6416
Security
Video
Interface
Output 6
18 17 16 15 14 13
VCCO
Microcontroller
Figure 7. Typical Application Diagram
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7
NCS6416
VCCO = +5V
100F
10F
C10
Input 1
SDA
C1
100
75
C2
Input 2
100nF 1
R1
R4
R2
100
4
Input 3
R5
75
Input 4
100nF 5
C4
100nF 6
R6
75
7
INPUT2
CLOCK
INPUT3
INPUT4
PROG
VCC = +5V
C6
Input 5
100nF 8
R7
Input 6
OUTPUT5
OUTPUT4
R8
R10
75
18
H
C9
F
75
R11
75
Z = 75
16
R12
75
Z = 75
15
R13
75
Z = 75
14
R14
75
Z = 75
17
R15
75
75
75
75
75
GND
11
C13
Input 7
100nF
INPUT7
R11
75
C8
100nF
Figure 8. Typical Application Circuit
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8
Output 5
Output 4
Output 3
Output 2
Output 1
75
12
INPUT6
Output 6
Z = 75
OUTPUT1
75
VCC = +5V
75
Z = 75
OUTPUT2
10
100nF
Input 8
R9
13
INPUT5
100nF
OUTPUT3
VCC
C7
C12
VCCO
OUTPUT6
9
75
20
19
DATA
100nF 3
SCL
C3
INPUT8
2
R3
75
INPUT1
C11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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