NCV51511PDR2G

High-Frequency, High Side and Low Side Gate Driver NCV51511 The NCV51511 is high side and low side gate−drive IC designed for high−voltage, high−speed, driving MOSFETs operating up to 80 V. The NCV51511 integrates a driver IC and a bootstrap diode. The driver IC features low delay time and matched PWM input propagation delays, which further enhance the performance of the part. The high speed dual gate drivers are designed to drive both the high−side and low−side of N−Channel MOSFETs in a half bridge or synchronous buck configuration. The floating high−side driver is capable of operating with supply voltages of up to 80 V. In the dual gate driver, the high side and low side each have independent inputs to allow maximum flexibility of input control signals in the application. The PWM input signal (high level) can be 3.3 V, 5 V or up to VDD logic input to cover all possible applications. The bootstrap diode for the high−side driver bias supply is integrated in the chip. The high−side driver is referenced to the switch node (HS) which is typically the source pin of the high−side MOSFET and drain pin of the low−side MOSFET. The low−side driver is referenced to VSS which is typically ground. The functions contained are the input stages, UVLO protection, level shift, bootstrap diode, and output driver stages. Features • • • • • • • • • • • • • Drives two N−Channel MOSFETs in High & Low Side Integrated Bootstrap Diode for High Side Gate Drive Bootstrap Supply Voltage Range up to 100 V 3 A Source, 6 A Sink Output Current Capability Drives 1nF Load with Typical Rise/Fall Times of 6 ns/4 ns TTL Compatible Input Thresholds Wide Supply Voltage Range 8 V to 16 V (Absolute Maximum 18 V) Fast Propagation Delay Times (Typ. 30 ns) 2 ns Delay Matching (Typical) Under−Voltage Lockout (UVLO) Protection for Drive Voltage Industry−Standard Pinouts, SOIC 8 with Exposed PAD Automotive Qualified to AEC−Q100: ♦ Operating temperature range from −40°C to 150°C ♦ Reliability at 150°C for 2,016 hrs These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com 8 1 SOIC8−EP CASE 751AC MARKING DIAGRAM 8 V51511 ALYWG G 1 V51511 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Device (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. Typical Applications • 48 V Converters for HEV/EV • Half−Bridge and Full−Bridge Converters • Synchronous−Buck Converters © Semiconductor Components Industries, LLC, 2018 July, 2021 − Rev. 1 1 Publication Order Number: NCV51511/D NCV51511 TYPICAL APPLICATIONS L VDC Supply Voltage VDD 2 HB 3 HO 4 HS CHB NCV51511 RHGATE 1 CIN L LO 8 VSS 7 LI 6 HI 5 COUT RLGATE O A D PWM Controller FEEDBACK Figure 1. Application Schematic − Synchronous Buck Converter VDC SECONDARY SIDE CIRCUIT RHGATE 6 LI 7 VSS 8 LO HS 4 HO 3 HB 2 VDD 1 CHB CIN Supply Voltage HI NCV51511 PWM Controller 5 RLGATE ISOLATION AND FEEDBACK Figure 2. Application Schematic − Half Bridge Converter www.onsemi.com 2 NCV51511 BLOCK DIAGRAM V DD 1 2 HB UVLO HI LI V SS 5 3 HO 4 HS 8 LO LEVEL SHIFT 6 UVLO 7 Figure 3. Simplified Block Diagram PIN CONNECTIONS NCV51511 V DD 1 HB 2 8 LO 7 V SS Thermal Pad HO 3 6 LI HS 4 5 HI Figure 4. Pin Assignments − SOIC8−EP (Top View) Table 1. PIN DESCRIPTION Pin No. Pin Name Description 1 VDD Logic and low−side gate driver power supply voltage 2 HB High−side floating supply 3 HO High−side driver output 4 HS High−voltage floating supply return 5 HI Logic input for High−side gate driver output 6 LI Logic input for Low−side gate driver output 7 VSS Logic Ground 8 LO Low−side driver output − Exposed PAD Can either be left open or connected to VSS. We recommend EPAD to be connected to VSS plane for improved thermal performance. www.onsemi.com 3 NCV51511 Table 2. MAXIMUM RATINGS All voltage parameters are referenced to VSS, unless otherwise noted. Symbol Parameter Min. Max. Units −0.3 18 V −1 100 V −(24 – VDD) 100 V −0.3 VDD + 0.3 V −2 VDD + 0.3 V VHS – 0.3 VHB + 0.3 V VHS – 2 VHB + 0.3 V Logic Input Voltage −0.3 VDD + 0.3 V High−Side Floating Supply Voltage −0.3 100 V VHB – VHS VHS to VHB Supply Voltage −0.3 18 V PD Power Dissipation (Note 3) 2.5 W TJ, Operating Junction Temperature 150 °C VDD Low−Side and Logic Fixed Supply Voltage VHS High−Side Floating Supply Offset Voltage(Note 1) Repetitive Pulse (< 100 ns)(Note 2) VLO Low−Side Output Voltage, LO Pin Repetitive Pulse (< 100 ns)(Note 2) VHO High−Side Floating Output Voltage, HO Pin Repetitive Pulse (< 100 ns)(Note 2) VLI, VHI VHB −55 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The VHS negative voltage capability can be calculated using (VHB –VHS)−18 V base on VHB, due to its dependence on VDD voltage level. 2. Verified at bench characterization. 3. JEDEC standard: JESD51−2, JESD51−3. Mounted on 76.2 x 114.3 x1.6 mm PCB (FR−4 glass epoxy material). Table 3. ESD AND MSL Symbol ESDHBM Parameters Electrostatic Discharge Capability ESDCDM MSL Value Unit.s Human Body Model,per AEC Q100−002 2000 V Charged Device Model, AEC Q100−011 1000 Moisture Sensitivity Level 2 Level Value Units Table 4. THERMAL INFORMATION (Note 4) Symbol Parameter qJA Thermal Resistance Junction−Air (Note 4) 39 °C/W yJL Thermal characterization parameter Junction−Lead 15 °C/W yJT Thermal characterization parameter Junction−Case (TOP) 6 °C/W 4. As mounted on a 76.2 x 114.3 x 1.6 mm FR4 substrate with a Multi−layer of 1 oz copper traces and heat spreading area. As specified for a JEDEC 51−7 conductivity test PCB. Test conditions were under natural convection or zero air flow Table 5. RECOMMENDED OPERATING RANGES All voltage parameters are referenced to VSS Symbol Parameters VDD Supply Voltage VHS High Side Floating Return VHB dVSW/dt TJ Test Condition Min. Max. Units DC 8 16 V DC −1 80 V Repetitive Pulse (< 100 ns) −(24 – VDD) 100 V DC VHS + 8 VHS + 16 V 50 V/ns −40 150 °C Voltage on HB Voltage Slew Rate on SW Operating Temperature Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 4 NCV51511 Table 6. ELECTRICAL CHARACTERISTICS VDD = VHB = 12 V, VHS = VSS = 0 V, TA = TJ = −40°C to 150°C, no load on HO or LO, unless otherwise noted. Symbol Parameters Test Condition Min. Typ. Max. Units Power Supply Section IDD VDD Quiescent Current VHI = 0 V; VLI = 0 V 0.17 0.3 mA IDDO VDD Operating Current fSW = 500 kHz 1.5 3.0 mA IHB HB Quiescent Current VHI = 0 V; VLI = 0 V 0.1 0.2 mA IHBO HB Operating Current fSW = 500 kHz 1.9 3.0 mA IHBS HB to VSS Quiescent Current VHS = VHB = 80 V IHBSO HB to VSS Operating Current fSW = 500 kHz VDDR VDD UVLO Threshold VDD Rising 6.2 VDDH VDD UVLO Hysteresis VHBR HB UVLO Threshold HB Rising 5.5 VHBH HB UVLO Hysteresis 0 10 mA 0.3 1.0 mA 6.8 7.4 V 0.6 6.3 V 7.2 0.4 V V Input Logic Section VIH High Level Input Voltage Threshold 1.80 2.2 2.50 V VIL Low Level Input Voltage Threshold 1.3 1.7 2.0 V VIHYS RIN Input Logic Voltage Hysteresis 0.5 V Input Pull−down Resistance 100 kW Bootstrap Diode VFL Forward Voltage @ Low Current IVDD−HB = 100 mA 0.55 0.8 V VFH Forward Voltage @ High Current IVDD−HB = 100 mA 0.8 1.0 V RD Dynamic Resistance IVDD−HB = 100 mA 0.7 1.5 W tBS (Note 5) Diode Turn−off Time IF = 20 mA, IREV = 0.5 A 20 VOLL Low Level Output Voltage ILO = 100 mA 0.06 0.15 V VOHL High Level Output Voltage ILO = −100 mA, VOHL = VDD − VLO 0.16 0.28 V IOHL (Note 5) Peak Pull−up Current VLO = 0 V 3 IOLL (Note 5) ns Low Side Driver A Peak Pull−down Current VLO = 12 V 6 A tR_LO LO Rise Time 10% to 90%, CLOAD = 1 nF 6 ns tF_LO LO Fall Time 90% to 10%, CLOAD = 1 nF 4 tR_LO1 LO Rise Time 3 V to 9 V, CLOAD = 100 nF 300 500 ns ns tF_LO1 LO Fall Time 9 V to 3 V, CLOAD = 100 nF 140 300 ns tLPHL LI = Low Propagation Delay VLI Falling to VLO Falling, CLOAD = 0 28 45 ns tLPLH LI = High Propagation Delay VLI Rising to VLO Rising, CLOAD = 0 30 47 ns VOLH Low Level Output Voltage IHO = 100 mA 0.06 0.15 V VOHH High Level Output Voltage IHO = −100 mA, VOHH = VHB − VHO 0.16 0.28 V IOHH (Note 5) Peak Pull−up Current VHO = 0 V 3 A IOLH (Note 5) Peak Pull−down Current VHO = 12 V 6 A tR_HO HO Rise Time 10% to 90%, CLOAD = 1 nF 6 ns tF_HO HO Fall Time 90% to 10%, CLOAD = 1 nF 4 ns tR_HO1 HO Rise Time 3 V to 9 V, CLOAD = 100 nF 300 500 ns tF_HO1 HO Fall Time 9 V to 3 V, CLOAD = 100 nF 140 300 ns tHPHL HI = Low Propagation Delay VHI Falling to VHO Falling, CLOAD = 0 28 45 ns tHPLH HI = High Propagation Delay VHI Rising to VHO Rising, CLOAD = 0 30 47 ns High Side Driver www.onsemi.com 5 NCV51511 Table 6. ELECTRICAL CHARACTERISTICS VDD = VHB = 12 V, VHS = VSS = 0 V, TA = TJ = −40°C to 150°C, no load on HO or LO, unless otherwise noted. Symbol Parameters Test Condition Min. Typ. Max. Units Delay Matching tMON HI Turn−OFF to LI Turn−ON 2 10 ns tMOFF LI Turn−OFF to HI Turn−ON 2 10 ns 50 ns Minimum Pulse Width tPW Minimum Pulse Width for HI and LI (Note 5) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. These parameters are guaranteed by design. TYPICAL CHARACTERISTICS Typical characteristics are provided at 25°C and VDD, VHB = 12 V unless otherwise noted. Figure 5. Quiescent Current vs. Temperature Figure 6. Quiescent Current vs. VDD (VHB) Figure 7. Operating Current vs. Temperature Figure 8. IDD Operating Current vs. Frequency www.onsemi.com 6 NCV51511 TYPICAL CHARACTERISTICS Figure 9. IHB Operating Current vs. Frequency Figure 10. Input Threshold vs. Temperature Figure 11. Input Threshold vs. VDD Figure 12. VDD UVLO Threshold vs. Temperature Figure 13. VHB UVLO Threshold vs. Temperature Figure 14. Bootstrap Diode VF vs. Temperature www.onsemi.com 7 NCV51511 TYPICAL CHARACTERISTICS Figure 16. VOH, VOL Voltage vs. VDD (VHB) Figure 15. VOH, VOL Voltage vs. Temperature Figure 17. Low Side Propagation Delay vs. Temperature Figure 18. High Side Propagation Delay vs. Temperature Figure 19. Low Side Propagation Delay vs. VDD Figure 20. High Side Propagation Delay vs. VHB www.onsemi.com 8 NCV51511 TYPICAL CHARACTERISTICS Figure 21. HO, LO Peak Source Current vs. Supply Voltage Figure 22. HO, LO Peak Sink Current vs. Supply Voltage Figure 23. Bootstrap Diode Forward Voltage vs. Temperature www.onsemi.com 9 NCV51511 Switching Time Definitions Figure 23 shows the switching time waveforms definitions of the turn on and off propagation delay times. HIN (LIN) 50% 50% tHPLH tLPLH tHPHL tLPHL 90% LIN HIN 90% LO 50% HO (LO) 50% 10% 10% HO tF tR tMON tMOFF Figure 24. Timing Diagrams Input to Output Definitions Figure 24 shows an input to output timing diagram for overall operation. VDD UVLO period VDD VDD UVLO threshold voltage : Typ. 6.8 V VDD UVLO Hysteresis HB UVLO period HB HI HB UVLO threshold voltage : Typ. 6.3 V VDD UVLO Hysteresis PWM Input Threshold PWM Input Threshold LI HO LO Figure 25. Overall Operation Timing Diagram www.onsemi.com 10 NCV51511 APPLICATIONS INFORMATION differential voltage is below the specified threshold. The HB UVLO rise threshold is 6.3 V with 0.4 V hysteresis. The NCV51511 is designed to drive high side and the low side N−channel power MOSFETs in a half bridge or synchronous buck. The driver IC integrates a bootstrap diode for high side driver bias supply. High side and Low side outputs are independently controlled by each of input control signals with TTL or logic compatibility. The floating high side driver can operate with supply voltage up to 80 V. The NCV51511 functions consist of the input stage, level shift, bootstrap diode, Under−Voltage Lockout (UVLO) protection and output stage. The UVLO function is included in both the high−and low side. Output Stage The NCV51511 output stage is able to Sink/Source 3.0 A /6.0 A typical which can effectively charge and discharge a 1 nF load in few ns. High−speed switching, low resistance and high current capability of both high side and low side drivers allow for efficient switching operation. The low side driver is referenced from VDD to VSS and the high side is referenced from HB to HS. The device logic status shows as below. Input Stage Table 7. DEVICE LOGIC STATUS The input pins (HI,LI) of gate driver devices are based on a TTL compatible input threshold logic that is independent of the VDD supply voltage. The PWM input signal (high level) can be 3.3 V, 5 V or up to VDD logic input to accommodate all possible applications. The input impedance of the NCV51511 is 100 kW nominal. The 100 kW is a pull−down resistance to ground (GND). The logic level compatible input provides a 2.2 V rising threshold and a 1.7 V falling threshold. Status Level Shift HI LI HO LO L L L L L H L H H L H L H H H H X X L L Select Bootstrap Capacitor The level shift circuit is the interface from the high side input to the high side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides excellent delay matching with the low side driver. To control the high side output drive utilizes a widely used technique for high side level shifter circuit so called pulsed latch level translators. The maximum allowable voltage drop across the bootstrap capacitor to ensure enough gate−source voltage is highly dependent to the internal under−voltage Lockout level of the gate drive IC, and the voltage level at the source connection of switching node HS. The maximum allowable drop voltage can be obtained by (eq.1) DV HB + V DD * V f * V HB,UVLO (eq. 1) Where: Bootstrap Diode • VDD: Gate drive IC supply voltage • Vf : Static forward voltage drop of bootstrap diode • VHB,UVLO: HB Under−Voltage Lockout level The NCV51511 integrates a high voltage bootstrap diode to generate the high side bias. It is provided to charge high side gate drive bootstrap capacitor. The diode anode is connected to VDD and cathode connected to HB. The boot capacitor should be connected externally to HB and the HS pins, the HB capacitor charge is refreshed every switching cycle when HS transitions to ground. The bootstrap diode provides fast recovery times, and a low resistance value of 0.7 W typ. The total charge (QBS) required by the bootstrap capacitor can be calculated by summing the Qg of the MOSFET and the charge required for the level shifter in the gate drive IC which is negligible quantity to compared Qg of the MOSFET. Q BS + Q g ) (I HBS Under−Voltage Lockout (UVLO) Both high side and low side drivers have independent UVLO protections which monitor the VDD supply voltage and HB bootstrap voltage. The function of the UVLO circuits is to ensure that there are enough supply voltages (VDD and HB) to correctly bias high side and low side circuits. This also ensures that the gate of external MOSFETs are driven at an optimum voltage. The VDD UVLO disables both high side and low side drivers when VDD is below the specified threshold. The rise VDD threshold is 6.8 V with 0.6 V hysteresis. The HB UVLO disables only the high side driver when the HB to HS • • • • T ON) (eq. 2) Where: QBS: Total gate charge of bootstrap capacitor Qg: Gate charge of the MOSFET IHBS: Quiescent current in High side gate drive IC. TON: Turning−on time of high−side MOSFET The guiding criteria for calculating the minimum required bootstrap capacitance can be obtained through (eq.3). C BOOT.MIN w www.onsemi.com 11 Q BS DV HB (eq. 3) NCV51511 Select External Bootstrap Series Resistor The NCV51511 utilizes high−speed gate driving for synchronous buck and half bridge applications. In these applications, voltage ringing can be generated by parasitic inductance of the primary power path, consisting of the input capacitor and switching MOSFETs (Coss). To reduce this ringing phenomenon, the first step is to optimize the PCB layout to reduce parasitic components of the power path. The second step is to add a series resistor with the bootstrap capacitor to slow down the turn−on transition of the high side MOSFET. Bias Supply Input Supply HB RB Bootstrap Diode HS Driver • • • • • • • • • LHS− D CIN HO LHS− S HS L LCIN LHS− D LS Driver LS COSS GND VOUT L O A D I OLH + V DD * V f * V OLH R gate I OHL + V DD * V OHL R gate I OLL + V DD * V OLL R gate (eq. 5) Where: IOHH: High side peak source current IOLH: High side peak sink current IOHL: Low side peak source current IOLL: Low side peak sink current Vf : Bootstrap diode forward voltage drop VOHH: High level output voltage drop (high side) VOLH: Low level output voltage drop (high side) VOHL: High level output voltage drop (low side) VOLL: Low level output voltage drop (low side) The total power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver losses are: • The static and dynamic losses related to the switching frequency • Output load capacitance losses on high and low side drivers • Internal consumption supply voltage, VDD The static losses are due to the quiescent current from the voltage supplies VDD and ground in low side driver and the leakage current in the level shifting stage in high side driver, which are dependent on the voltage supplied on the HS pin and proportional to the duty cycle when only the high side power device is turned on. The quiescent current is consumed by the device through all internal circuits such as input stage, reference voltage, logic circuits, protections, and also any current associated with switching of internal devices when the driver output changes state. The effect of the static losses within the gate driver can be safely assumed to be negligible thanks to the NCV51511 low 0.17 mA quiescent current. The dynamic losses are defined as follows: In the low side driver, the dynamic losses are due to two different sources. One is due to whenever a load capacitor is charged or discharged through a gate resistor, half of the energy that Figure 26 shows the synchronous buck with the parasitic component at the power path. Each of parasitic inductance and low side COSS of MOSFET made up the ringing phenomenon at the HS node, when the high side turns on. When the bootstrap series resistor RB installed with bootstrap capacitor, the bootstrap resistor limits the current available to charge the gate of the high side MOSFET, increasing the time needed to turn the high side MOSFET on. The increased switching time slows the HS node rate of rising and can have a significant impact on the peak voltage on the HS node. We recommend selecting less than 10 W for RB. V DD * V f RB V DD * V f * V OHH R gate Gate Driver Power Dissipation LHS− S Figure 26. Application Circuit with Parasitic Components I BOOT(PEAK) + I OHH + (eq. 4) Select Gate Resistor The gate resistor is also sized to reduce a ringing voltage of the HS node by parasitic inductances and capacitances. But, it limits the current capability of the gate driver output by the resistance value. The limited current capability value by the gate resistor can be obtained (eq.5). www.onsemi.com 12 NCV51511 • The gate driver should be located as close as possible of goes into the capacitance is dissipated in the resistor. The losses in the gate driver resistance, internal and external to the gate driver, and the switching losses of the internal CMOS circuitry. The dynamic losses of the high side driver also have two different sources. One is due to the level shifting circuit and the other is to the charging and discharging of the capacitance of the high side. The static losses are neglected here because the total IC power dissipation is mainly dynamic losses of gate drive IC and can be estimated as: P DGATE + 2 CL fS • • • 2 V DD [W] • (eq. 6) The bootstrap circuit power dissipation is the sum of the bootstrap diode losses and the bootstrap resistor losses if any exist. The bootstrap diode loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these events happens once per cycle, the diode power loss is proportional to switching frequency. Larger capacitive loads require more current to recharge the bootstrap capacitor, resulting in more losses. switching MOSFET. The VDD capacitor and bootstrap capacitor should be located as near as possible to the device. In order to reduce a ringing voltage of the HS node, the space between high side source and low side drain of the MOSFET should be small as possible. The exposed pad should be connected to GND plane and use at least four or more vias for improved thermal performance. Avoid driver input pulse signal close to the HS node. One of recommendation layout pattern for the driver is shown in Figure 27. VDD 2 HB 3 HO 4 HS NCV51511 1 LO 8 VSS 7 LI 6 HI 5 PCB Layout Guideline NCV51511 is a high speed and high current high side and low side driver. To avoid any device malfunction during device operation, it is very important that there is very low parasitic inductance in the current switching path. It is very important that the best layout practices are followed for the PCB layout of the NCV51511. The following should be considered before beginning a PCB layout using the NCV51511. Figure 27. Layout Recommendation ORDERING INFORMATION Device NCV51511PDR2G Output Configuration Temperature Range (5C) Package Shipping† High Side and Low Side −40 to 150 SOIC8−EP (Pb−Free) Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D www.onsemi.com 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 EP CASE 751AC ISSUE D 8 1 SCALE 1:1 DATE 02 APR 2019 GENERIC MARKING DIAGRAM* 8 XXXXX AYWWG G 1 DOCUMENT NUMBER: DESCRIPTION: XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package 98AON14029D SOIC−8 EP *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present and may be in either location. Some products may not follow the Generic Marking. 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