NCV8184
Tracking Regulator/Line
Driver - Micropower,
Low Dropout
70 mA
http://onsemi.com
The NCV8184 is a monolithic integrated low dropout tracking
voltage regulator designed to provide an adjustable buffered output
voltage that closely tracks (±3.0 mV) the reference input.
The part can be used in automotive applications with remote
sensors, or any situation where it is necessary to isolate the output of
your regulator.
The NCV8184 also enables the user to bestow a quick upgrade to
their module when added current is needed, and the existing regulator
cannot provide.
The versatility of this part also enables it to be used as a high−side
driver.
1
SOIC−8 EP
PD SUFFIX 8
CASE 751AC
• 70 mA Source Capability
• Output Tracks within ±3.0 mV
• Low Input Voltage Tracking Performance
PIN CONNECTIONS AND
MARKING DIAGRAMS
(Works Down to VREF = 2.1 V)
Low Dropout (0.35 V Typ. @ 50 mA)
Low Quiescent Current
Thermal Shutdown
Wide Operating Range
Internally Fused Leads in SOIC−8 Package
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
VOUT
Current Limit &
Saturation Sense
Adj
−
VREF/ENABLE
+
1
VIN
GND
GND
GND
GND
VREF/ENABLE
Adj
VOUT
NC
GND
Adj
1
8
8184
AYWWG
G
VIN
VOUT
8184
ALYW
G
•
1
DPAK 5−LEAD
DT SUFFIX
CASE 175AA
1
Features
•
•
•
•
•
•
SOIC−8
D SUFFIX
CASE 751
8184G
ALYWW
Pin
Tab,
VIN
NC
NC
VREF/ENABLE
1. VIN
2. VOUT
3. GND
4. Adj
5. VREF/ENABLE
1
GND
BIAS
Thermal
Shutdown
8184
A
L
Y
W, WW
G or G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2012
October, 2019 − Rev. 27
1
Publication Order Number:
NCV8184/D
NCV8184
MAXIMUM RATINGS
Rating
Value
Unit
Storage Temperature
−65 to 150
°C
Supply Voltage Range (Continuous)
−15 to 45
V
Supply Voltage Operating Range
4.0 to 42
V
Peak Transient Voltage (VIN = 14 V, Load Dump Transient = 31 V)
45
V
Voltage Range (VOUT, Adj)
−3.0 to 45
V
Voltage Range (VREF/ENABLE)
−0.3 to 45
V
Maximum Junction Temperature
ESD Capability
150
°C
2.5
200
1000
kV
V
V
240 peak
260 peak (Pb−Free) (Note 2)
°C
Human Body Model
Machine Model
Charge Device Model
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 60 second maximum above 183°C.
2. −5°C / +0°C Allowable Conditions, applies to both Pb and Pb−Free devices.
THERMAL CHARACTERISTICS See Package Thermal Data Section (Page 8)
ELECTRICAL CHARACTERISTICS (VIN = 14 V; VREF/ENABLE > 2.1 V; −40°C < TJ < +150°C; COUT = 1.0 mF;
IOUT = 1.0 mA; Adj = VOUT; COUT−ESR = 1.0 W, unless otherwise specified.)
Parameter
Test Conditions
Min
Typ
Max
Unit
−3.0
−
3.0
mV
REGULATOR OUTPUT
VREF/ENABLE − VOUT
VOUT Tracking Error
5.7 V ≤ VIN ≤ 26 V, 100 mA ≤ IOUT ≤ 60 mA
2.1 V ≤ VREF/ENABLE ≤ (VIN − 600 mV)
Dropout Voltage (VIN − VOUT)
IOUT = 100 mA
IOUT = 5.0 mA
IOUT = 60 mA
−
−
−
100
250
350
150
500
600
mV
mV
mV
Line Regulation
5.7 V ≤ VIN ≤ 26 V, VREF/ENABLE = 5.0 V
−
−
3.0
mV
Load Regulation
100 mA ≤ IOUT ≤ 60 mA, VREF/ENABLE = 5.0 V
−
−
3.0
mV
Adj Input Bias Current
VREF/ENABLE = 5.0 V
−
0.2
6.0
mA
Current Limit
VIN = 14 V, VREF = 5.0 V, VOUT = 90% of VREF (Note 3)
70
−
225
mA
Quiescent Current (IIN − IOUT)
VIN = 12 V, IOUT = 60 mA
VIN = 12 V, IOUT = 100 mA
VIN = 12 V, VREF/ENABLE = 0 V
−
−
−
5.0
50
−
7.0
70
20
mA
mA
mA
Ripple Rejection
f = 120 Hz, IOUT = 60 mA, 6.0 V ≤ VIN ≤ 26 V
60
−
−
dB
Thermal Shutdown
Guaranteed by Design
150
180
210
°C
0.8
−
2.1
V
−
0.2
3.0
mA
VREF/ENABLE
Enable Voltage
−
Input Bias Current
VREF/ENABLE = 5.0 V
3. VOUT connected to Adj lead.
PACKAGE PIN DESCRIPTION
Package Lead Number
SOIC−8 EPAD
SOIC−8
DPAK, 5−LEAD
Lead Symbol
8
8
1
VIN
1
1
2
VOUT
Regulated output.
3, EPAD
2, 3, 6, 7
Tab, 3
GND
Ground.
4
4
4
Adj
5
5
5
VREF/ENABLE
2, 6, 7
−
−
NC
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2
Function
Battery supply input voltage.
Adjust lead, noninverting input.
Reference voltage and ENABLE input.
No Connection. PCB traces allowed.
NCV8184
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
IOUT = 50 mA
0.3
0.8
TRACKING ERROR (mV)
TRACKING ERROR (mV)
0.4
0.2
0.1
0.0
−0.1
−0.2
0.6
+125°C
0.4
0.2
+25°C
0.0
−0.2
−40°C
−0.4
−0.3
−40
−20
0
20
40
60
80
TEMPERATURE (°C)
100
−0.6
120
0
Figure 2. Tracking Error vs. Temperature
50
3.5
Unstable Region
ESR (W)
ESR (W)
35
25
20
15
2.0
1.5
C2 = 0.1 mF
0
10
Stable Region
50
20
30
40
OUTPUT CURRENT (mA)
60
0.0
70
0
10
C2 = 0.1 mF
VOUT = 5.0 V
20
30
40
50
OUTPUT CURRENT (mA)
60
70
Figure 5. Output Stability with 0.1 mF at Low ESR
2.5
12
VREF / ENABLE = 5.0 V
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
Data is for 0.1 mF only. Capacitor
values 0.5 mF and above do not
exhibit instability with low ESR.
0.5
Figure 4. Output Stability with Capacitor Change
10
+125°C
8
+25°C
6
−40°C
4
2
0
Unstable Region
2.5
1.0
C2 = 10 mF
5
0
Stable Region
3.0
10
70
4.0
40
30
60
Figure 3. Tracking Error vs. Output Current
VOUT = 5.0 V
45
20
30
40
50
OUTPUT CURRENT (mA)
10
0
10
20
30
40
50
OUTPUT CURRENT (mA)
60
2
1
0.5
IOUT = 1 mA
0
70
IOUT = 20 mA
1.5
0
Figure 6. Quiescent Current vs. Output Current
5
10
15
INPUT VOLTAGE (V)
20
Figure 7. Quiescent Current vs. Input Voltage
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3
25
NCV8184
TYPICAL PERFORMANCE CHARACTERISTICS
6
OUTPUT VOLTAGE VOUT (V)
DROPOUT VOLTAGE (V)
0.5
+125°C
0.4
+25°C
0.3
0.2
−40°C
0.1
5
4
+25°C
3
+125°C
2
1
−40°C
0.0
0
10
20
30
40
50
OUTPUT CURRENT (mA)
60
0
70
0
6
0.6
REFERENCE CURRENT (mA)
0.7
5
4
3
2
1
0
0
1
2
3
4
5
REFERENCE VOLTAGE (V)
6
5
10
15
20
INPUT VOLTAGE VIN (V)
0.4
0.3
0.2
0.1
0.0
7
0
1
2
3
4
5
REFERENCE VOLTAGE (V)
115
110
105
100
95
90
85
1
6
Figure 11. Reference Current vs. Reference
Voltage
120
0
30
0.5
Figure 10. Output Voltage vs. Reference Voltage
80
25
Figure 9. Output Voltage vs. Input Voltage
7
THERMAL RESISTANCE, JUNCTION
TO AMBIENT, RqJA, (°C/W)
OUTPUT VOLTAGE (V)
Figure 8. Dropout Voltage vs. Output Current
VREF/ENABLE = 5.0 V
2
3
4
COPPER AREA (in2)
5
Figure 12. SOIC−8, qJA as a Function of the
Pad Copper Area (2.0 oz. Cu Thickness),
Board Material = 0.0625 G−10/R−4
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4
6
7
NCV8184
CIRCUIT DESCRIPTION
By pulling the VREF/ENABLE lead below 0.8 V, (see
Figure 16 or Figure 17), the IC is disabled and enters a sleep
state where the device draws less than 20 mA from supply.
When the VREF/ENABLE lead is greater than 2.1 V, VOUT
tracks the VREF/ENABLE lead normally.
The output is capable of supplying 70 mA to the load
while configured as a similar (Figure 13), lower (Figure 15),
or higher (Figure 14) voltage as the reference lead. The Adj
lead acts as the inverting terminal of the op amp and the
VREF lead as the non−inverting.
The device can also be configured as a high−side driver as
displayed in Figure 18.
GND
C1*
1.0 mF
GND
GND
VREF/
ENABLE
Adj
VOUT, 70 mA
Loads
VOUT
C2**
GND
10 mF
RF
GND
B+
VIN
RA
Figure 13. Tracking Regulator at the Same Voltage
GND
GND
Adj
NCV8184
GND
GND
GND
VREF
C3***
10 nF
Figure 14. Tracking Regulator at Higher Voltages
VOUT, 70 mA
B+
VIN
C2**
10 mF
C1*
1.0 mF
VOUT
GND
GND
R1
VREF/
ENABLE
C1*
1.0 mF
R
VOUT + VREF(1 ) E)
RA
VOUT + VREF
VOUT, 70 mA
Loads
VOUT
C2**
GND
10 mF
B+
VIN
VREF/
ENABLE
Adj
5.0 V
C3***
10 nF
C3***
10 nF
Adj
VREF
R2
NCV8184
VOUT, 70 mA
Loads
VOUT
C2**
GND
10 mF
NCV8184
Output Voltage
NCV8184
ENABLE Function
B+
VIN
C1*
1.0 mF
GND
GND
VREF/
ENABLE
from MCU
R
C3***
10 nF
VREF
VOUT + VREF( R2 )
R1 ) R2
Figure 15. Tracking Regulator at Lower Voltages
NCV8501
VREF (5.0 V)
70 mA
70 mA
VOUT
To Load 10 mF
(e.g. sensor)
GND
GND
Adj
NCV8184
100 nF
VIN
GND
GND
C1*
1.0 mF
mC
GND
Adj
GND
VREF/
ENABLE
VOUT
I/O
C3***
10 nF
NCV8184
VIN
6.0 V−40 V
Figure 16. Tracking Regulator with ENABLE Circuit
B+
VIN
GND
GND
VREF/
ENABLE
C3***
10 nF
MCU
VOUT + B ) * VSAT
Figure 17. Alternative ENABLE Circuit
Figure 18. High−Side Driver
* C1 is required if the regulator is far from the power source filter. In case of power supply generates voltage ripple (e.g. DC-DC converter) a passive low pass filter with C1 value at least 1 mF is required to suppress the ripple. The filter should be designed according
to particular operating conditions and verified in the application.
** C2 is required for stability.
*** C3 is recommended for EMC susceptibility
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5
NCV8184
APPLICATION NOTES
VOUT Short to Battery
Figure 20. In this case the NCV8184 supply input voltage is
set at 7.0 V when a short to battery (14 V typical) occurs on
VOUT which normally runs at 5.0 V. The current into the
device (ammeter in Figure 20) will draw additional current
as displayed in Figure 21.
The NCV8184 will survive a short to battery when hooked
up the conventional way as shown in Figure 19. No damage
to the part will occur. The part also endures a short to battery
when powered by an isolated supply at a lower voltage as in
Short to battery
C2**
10 mF
B+
VIN
VOUT
NCV8184
VOUT 70 mA
Loads
GND
GND
C1*
1.0 mF
GND
GND
VREF/
ENABLE
Adj
+ Automotive Battery
− typically 14 V
5.0 V
+
5.0 V
−
C3***
10 nF
VOUT = VREF
Figure 19.
Short to battery
A
Loads
VOUT
B+
70 mA
VIN
VOUT
C2**
10 mF
GND
GND
NCV8184
Automotive Battery
typically 14 V
Adj
* C1 is required if the regulator is far from the power source filter.
** C2 is required for stability.
*** C3 is recommended for EMC susceptibility.
C1*
7V
1.0 mF
GND
+
−
GND
VREF/
ENABLE
VOUT = VREF
C3***
10 nF
5.0 V
+
5.0 V
−
Figure 20.
18
Switched Application
16
The NCV8184 has been designed for use in systems where
the reference voltage on the VREF/ENABLE pin is
continuously on. Typically, the current into the
VREF/ENABLE pin will be less than 1.0 mA when the
voltage on the VIN pin (usually the ignition line) has been
switched out (VIN can be at high impedance or at ground.)
Reference Figure 22.
12
10
8
6
Ignition
Switch
VOUT
4
2
C2
10 mF
0
5 6 7 8 9 10 1112 1314 15 1617 1819 20 2122 2324 25 26
VOUT VOLTAGE (V)
GND
GND
Figure 21. VOUT Short to Battery
VIN
VOUT
Adj
NCV8184
CURRENT (mA)
14
GND
6
VBAT
GND
VREF/
ENABLE
Figure 22.
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C1
1.0 mF
< 1.0 mA
VREF
5.0 V
NCV8184
External Capacitors
The value of RqJA can then be compared with those in the
Package Thermal Data Section of the data sheet. Those
packages with RqJA’s less than the calculated value in
equation 2 will keep the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external heat
sink will be required.
The output capacitor for the NCV8184 is required for
stability. Without it, the regulator output will oscillate.
Actual size and type may vary depending upon the
application load and temperature range. Capacitor effective
series resistance (ESR) is also a factor in the IC stability.
Worst−case is determined at the minimum ambient
temperature and maximum load expected.
The output capacitor can be increased in size to any
desired value above the minimum. One possible purpose of
this would be to maintain the output voltage during brief
conditions of negative input transients that might be
characteristic of a particular system.
The capacitor must also be rated at all ambient
temperatures expected in the system. To maintain regulator
stability down to −40°C, a capacitor rated at that temperature
must be used.
More information on capacitor selection for SMART
REGULATOR®s is available in the SMART REGULATOR
application note, “Compensation for Linear Regulators,”
document number SR003AN/D, available through our
website at http://www.onsemi.com.
VIN
IOUT
VOUT
IQ
Figure 23. Single Output Regulator with Key
Performance Parameters Labeled
Heatsinks
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RqJA:
The maximum power dissipation for a single output
regulator (Figure 23) is:
PD(max) + {VIN(max) * VOUT(min)} IOUT(max)
(eq. 1)
where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IOUT(max) is the maximum output current, for the
application,and
IQ is the quiescent current the regulator consumes at
IOUT(max).
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
RqJA + 150° C * TA
PD
SMART
REGULATOR®
Control
Features
Calculating Power Dissipation in a Single Output
Linear Regulator
) VIN(max)IQ
IIN
RqJA + RqJC ) RqCS ) RqSA
(eq. 3)
where:
RqJC = the junction−to−case thermal resistance,
RqCS = the case−to−heatsink thermal resistance, and
RqSA = the heatsink−to−ambient thermal resistance.
RqJC appears in the package section of the data sheet. Like
RqJA, it is a function of package type. RqCS and RqSA are
functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heatsink manufacturers.
(eq. 2)
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7
NCV8184
PACKAGE THERMAL DATA
Conditions
Typical Value
Parameter
100
mm2
Spreader Board
Units
645
mm2
Spreader Board
1 oz
2 oz
1 oz
2 oz
Junction−to−Pin 6 (Y−JL6, YJL6)
53
51
50
47
°C/W
Junction−to−Ambient (RqJA, qJA)
151
135
111
100
°C/W
SOIC−8 Package
Package construction
Without mold compound
Figure 24. PCB Layout and Package Construction for Simulation
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8
NCV8184
Table 1. SOIC−8 THERMAL RC NETWORK MODELS*
100 mm2
Copper Area (1 oz thick)
645 mm2
100 mm2
Cauer Network
C_C1
C_C2
C_C3
C_C4
C_C5
C_C6
C_C7
C_C8
C_C9
C_C10
Junction
node1
node2
node3
node4
node5
node6
node7
node8
node9
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
R_R1
R_R2
R_R3
R_R4
R_R5
R_R6
R_R7
R_R8
R_R9
R_R10
Junction
node1
node2
node3
node4
node5
node6
node7
node8
node9
node1
node2
node3
node4
node5
node6
node7
node8
node9
gnd
100 mm2
0.0000015
0.0000059
0.0000171
0.0001340
0.0001322
0.0010797
0.0087127
0.0863882
0.3109255
0.8359004
100 mm2
0.8380955
1.9719907
5.0213740
3.1295806
3.2483544
6.5922506
16.5499898
45.3838437
32.8928798
37.5059686
645 mm2
Foster Network
645 mm2
0.0000015
0.0000059
0.0000171
0.0001340
0.0001323
0.0010811
0.0087918
0.0950421
1.0127094
1.5167041
645 mm2
0.8380935
1.9719679
5.0211819
3.1288061
3.2468794
6.5781209
16.2818051
34.7292748
7.6862725
24.4060143
Units
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Tau
1.00E-06
1.00E-05
1.00E-04
1.76E-04
0.0010
0.008
0.150
3.00
8.96
52.5
R’s
0.49519
1.070738
3.385971
1.617537
5.10
7.00
15.00
20.00
28.19863
71.26626
Tau
1.00E-06
1.00E-05
1.00E-04
1.76E-04
0.0010
0.008
0.150
3.00
5.15
68.4
R’s
0.49519
1.070738
3.385971
1.617537
5.10
7.00
15.00
20.00
16.67727
33.54171
Units
sec
sec
sec
sec
sec
sec
sec
sec
sec
sec
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
*Bold face items in the tables above represent the package without the external thermal system.
tools, whereas Foster networks may be more easily
implemented using mathematical tools (for instance, in a
spreadsheet program), according to the following formula:
The Cauer networks generally have physical significance
and may be divided between nodes to separate thermal
behavior due to one portion of the network from another.
The Foster networks, though when sorted by time constant
(as above) bear a rough correlation with the Cauer networks,
are really only convenient mathematical models. Cauer
networks can be easily implemented using circuit simulating
R(t) +
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9
n
Ri ǒ1−e−tńtaui Ǔ
S
i+1
NCV8184
160
150
qJA (°C/W)
140
130
1.0 oz Cu
120
110
2.0 oz Cu
100
90
80
0
100
200
300
400
COPPER HEAT SPREADER AREA
500
600
700
(mm2)
Figure 25. SOIC−8, qJA as a Function of the Pad Copper Area, Board Material FR4
1000
R(t) (°C/W)
100
50% Duty Cycle
20%
10
10%
5%
Notes:
2%
1
0.1
PDM
t1
1%
Single Pulse
t1
Duty Cycle, D = t
2
(1.0 in pad PCB) Die Size = 2.08 x 1.55 x 0.40 5.0% Active Area
0.000001
0.00001
0.0001
0.001
0.01
0.1
t2
1
10
100
1000
PULSE TIME (sec)
Figure 26. SOIC−8 Thermal Duty Cycle Curves on 1.0 in Spreader Test Board, 1.0 oz Cu
1000
Cu Area 100 mm2
R(t) (°C/W)
100
Cu Area 645 mm2
10
1
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
PULSE TIME (sec)
Figure 27. SOIC−8 Single Pulse Heating Curve
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10
10
100
1000
NCV8184
PACKAGE THERMAL DATA
Conditions
Typical Value
Parameter
100
mm2
Spreader Board
Units
645
mm2
Spreader Board
1 oz
2 oz
1 oz
2 oz
Junction−to−Board (Y−JB, YJB)
26
26
26
25
°C/W
Junction−to−Pin 6 (tab) (Y−JL6, YJL6)
48
45
37
34
°C/W
Junction−to−Ambient (RqJA, qJA)
140
123
88
78
°C/W
SOIC−8 EP Package
Package construction
Without mold compound
Figure 28. PCB Layout and Package Construction for Simulation
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11
NCV8184
Table 2. SOIC−8 EP THERMAL RC NETWORK MODELS*
Drain Copper Area (1 oz thick)
(SPICE Deck Format)
100 mm2
645 mm2
100 mm2
Cauer Network
C_C1
C_C2
C_C3
C_C4
C_C5
C_C6
C_C7
C_C8
C_C9
C_C10
Junction
node1
node2
node3
node4
node5
node6
node7
node8
node9
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
R_R1
R_R2
R_R3
R_R4
R_R5
R_R6
R_R7
R_R8
R_R9
R_R10
Junction
node1
node2
node3
node4
node5
node6
node7
node8
node9
node1
node2
node3
node4
node5
node6
node7
node8
node9
gnd
100 mm2
0.0000015
0.0000059
0.0000171
0.0001359
0.0001349
0.0011157
0.0110409
0.0963225
0.3406538
0.9202956
100 mm2
0.8378620
1.9693564
5.0005397
3.0695514
3.1989711
6.2274239
13.5796441
40.4842477
30.5112160
33.6034987
645 mm2
Foster Network
645 mm2
0.0000015
0.0000059
0.0000172
0.0001360
0.0001352
0.0011253
0.0118562
0.2080891
1.1005982
0.8512155
645 mm2
0.8378491
1.9692100
4.9993083
3.0646169
3.1895109
6.1397875
11.9712961
18.5111622
10.0330297
27.3017101
Units
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Tau
1.00E-06
1.00E-05
1.00E-04
1.76E-04
0.0010
0.008
0.150
3.00
9.11
52.1
R’s
0.49519
1.070738
3.385971
1.617537
5.030483
7.00
12.00
17.676107
25.169021
65.037264
Tau
1.00E-06
1.00E-05
1.00E-04
1.76E-04
0.0010
0.008
0.150
3.00
5.12
68.6
R’s
0.49519
1.070738
3.385971
1.617537
5.030483
7.00
12.00
7.880592
8.550583
40.98639
Units
sec
sec
sec
sec
sec
sec
sec
sec
sec
sec
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
*Bold face items in the tables above represent the package without the external thermal system.
The Cauer networks generally have physical significance
and may be divided between nodes to separate thermal
behavior due to one portion of the network from another.
The Foster networks, though when sorted by time constant
(as above) bear a rough correlation with the Cauer networks,
are really only convenient mathematical models. Cauer
networks can be easily implemented using circuit simulating
tools, whereas Foster networks may be more easily
implemented using mathematical tools (for instance, in a
spreadsheet program), according to the following formula:
R(t) +
http://onsemi.com
12
n
Ri ǒ1−e−tńtaui Ǔ
S
i+1
NCV8184
150
140
qJA (°C/W)
130
TJ = 25°C
120
110
1.0 oz Cu
100
90
2.0 oz Cu
80
70
60
0
100
200
300
400
500
600
700
COPPER HEAT SPREADER AREA (mm2)
Figure 29. SOIC–8 Exposed Pad, θJA as a Function of
the Pad Copper Area, Board Material FR4
R(t) (°C/W)
100
50% Duty Cycle
20%
10 10%
5%
2%
1
Notes:
PDM
t1
1%
t1
Duty Cycle, D = t
2
Single Pulse
(1.0 in pad PCB) Die Size = 2.08 x 1.55 x 0.40 5.0% Active Area
0.1
0.000001 0.00001
0.0001
0.001
0.01
0.1
t2
1
10
100
1000
PULSE TIME (sec)
Figure 30. SOIC–8 Exposed Pad Thermal Duty Cycle
Curves on 1.0 in Spreader Test Board, 1.0 oz Cu
1000
Cu Area 100 mm2
R(t) (°C/W)
100
Cu Area 645 mm2
10
1
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
PULSE TIME (sec)
1
10
Figure 31. SOIC–8 Exposed Pad Single Pulse Heating Curve
http://onsemi.com
13
100
1000
NCV8184
PACKAGE THERMAL DATA
Conditions
Typical Value
Parameter
100
mm2
Spreader Board
Units
645
mm2
Spreader Board
1 oz
2 oz
1 oz
2 oz
Junction−to−Board-top (Y−JB, YJB)
18
18
17
16
°C/W
Junction−to−Pin 3 (tab) (Y−JL3, YJL3)
16
16
16
16
°C/W
Junction−to−Ambient (RqJA, qJA)
87
77
62
55
°C/W
DPAK 5−LEAD Package
Package construction
Without mold compound
Figure 32. PCB Layout and Package Construction for Simulation
http://onsemi.com
14
NCV8184
Table 3. DPAK 5−LEAD THERMAL RC NETWORK MODELS*
Drain Copper Area (1 oz thick)
(SPICE Deck Format)
100 mm2
645 mm2
100 mm2
Cauer Network
C_C1
C_C2
C_C3
C_C4
C_C5
C_C6
C_C7
C_C8
C_C9
C_C10
Junction
node1
node2
node3
node4
node5
node6
node7
node8
node9
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
R_R1
R_R2
R_R3
R_R4
R_R5
R_R6
R_R7
R_R8
R_R9
R_R10
Junction
node1
node2
node3
node4
node5
node6
node7
node8
node9
node1
node2
node3
node4
node5
node6
node7
node8
node9
gnd
100 mm2
0.0000016
0.0000060
0.0000177
0.0001586
0.0001927
0.0056684
0.0832719
0.1125429
0.5161495
1.4600223
100 mm2
0.8287213
1.9304163
4.7751915
2.3736457
2.0679537
5.3364094
6.0331860
22.7616126
17.9894079
22.7199543
645 mm2
Foster Network
645 mm2
0.0000016
0.0000060
0.0000177
0.0001587
0.0001931
0.0058019
0.1225791
0.3555671
1.2959188
1.8396650
645 mm2
0.8287120
1.9303119
4.7743247
2.3705112
2.0623650
5.1102633
3.2428679
8.6995800
16.1165074
16.7871407
Units
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Tau
1.00E-06
1.00E-05
1.00E-04
1.76E-04
0.0010
0.030
0.285
3.00
9.03
55.2
R’s
0.490938
1.061544
3.356895
1.606314
5.00
5.00
2.00
9.147005
17.23178
41.92202
Tau
1.00E-06
1.00E-05
1.00E-04
1.76E-04
0.0010
0.030
0.299
3.00
11.80
79.0
R’s
0.490938
1.061544
3.356895
1.606314
5.00
5.00
2.00
5.071663
3.646957
34.68827
Units
sec
sec
sec
sec
sec
sec
sec
sec
sec
sec
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
*Bold face items in the tables above represent the package without the external thermal system.
tools, whereas Foster networks may be more easily
implemented using mathematical tools (for instance, in a
spreadsheet program), according to the following formula:
The Cauer networks generally have physical significance
and may be divided between nodes to separate thermal
behavior due to one portion of the network from another.
The Foster networks, though when sorted by time constant
(as above) bear a rough correlation with the Cauer networks,
are really only convenient mathematical models. Cauer
networks can be easily implemented using circuit simulating
R(t) +
http://onsemi.com
15
n
Ri ǒ1−e−tńtaui Ǔ
S
i+1
NCV8184
90
85
80
TJ = 25°C
75
1.0 oz Cu
qJA (°C/W)
70
65
2.0 oz Cu
60
55
50
45
40
0
100
200
300
400
500
600
700
COPPER HEAT SPREADER AREA (mm2)
Figure 33. DPAK 5−Lead, θJA as a Function of the
Pad Copper Area, Board Material FR4
100
50% Duty Cycle
R(t) (°C/W)
20%
10
10%
5%
2%
Notes:
t1
1 1%
Single Pulse
0.1
0.00001
0.0001
0.001
0.01
0.1
t2
t1
Duty Cycle, D = t
2
(1.0 in pad PCB) Die Size = 2.08 x 1.55 x 0.40 5.0% Active Area
0.000001
PDM
1
10
100
1000
PULSE TIME (sec)
Figure 34. DPAK 5−Lead Thermal Duty Cycle Curves
on 1.0 in Spreader Test Board, 1.0 oz Cu
100
Cu Area 100 mm2
R(t) (°C/W)
Cu Area 645 mm2
10
1
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
PULSE TIME (sec)
Figure 35. DPAK 5−Lead Single Pulse Heating Curve
http://onsemi.com
16
10
100
1000
NCV8184
R1
Junction
R2
C1
C2
R3
Rn
Cn
C3
Ambient
(thermal ground)
Time constants are not simple RC products.
Amplitudes of mathematical solution are not the resistance values.
Figure 36. Grounded Capacitor Thermal Network (“Cauer” Ladder)
Junction
R1
R2
R3
Rn
C1
C2
C3
Cn
Each rung is exactly characterized by its RC−product time constant;
Amplitudes are the resistances
Ambient
(thermal ground)
Figure 37. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder)
ORDERING INFORMATION
Package Type
Shipping†
NCV8184DG
SOIC−8
(Pb−Free)
98 Units / Tube
NCV8184DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCV8184DTRKG
DPAK
(Pb−Free)
2500 / Tape & Reel
NCV8184PDG
SOIC−8 epad
(Pb−Free)
98 Units / Tube
NCV8184PDR2G
SOIC−8 epad
(Pb−Free)
2500 / Tape & Reel
Device Order Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK−5, CENTER LEAD CROP
CASE 175AA
ISSUE B
DATE 15 MAY 2014
SCALE 1:1
−T−
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
R1
Z
A
S
12 3 4 5
U
K
F
J
L
H
D
G
5 PL
0.13 (0.005)
M
T
2.2
0.086
0.34 5.36
0.013 0.217
5.8
0.228
10.6
0.417
0.8
0.031
SCALE 4:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON12855D
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.020 0.028
0.018 0.023
0.024 0.032
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.045 BSC
0.170 0.190
0.185 0.210
0.025 0.040
0.020
−−−
0.035 0.050
0.155 0.170
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.51
0.71
0.46
0.58
0.61
0.81
4.56 BSC
0.87
1.01
0.46
0.58
2.60
2.89
1.14 BSC
4.32
4.83
4.70
5.33
0.63
1.01
0.51
−−−
0.89
1.27
3.93
4.32
GENERIC
MARKING DIAGRAMS*
RECOMMENDED
SOLDERING FOOTPRINT*
6.4
0.252
DIM
A
B
C
D
E
F
G
H
J
K
L
R
R1
S
U
V
Z
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DPAK−5 CENTER LEAD CROP
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 EP
CASE 751AC
ISSUE E
8
1
SCALE 1:1
DATE 05 OCT 2022
GENERIC
MARKING DIAGRAM*
8
XXXXX
AYWWG
G
1
DOCUMENT NUMBER:
DESCRIPTION:
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
98AON14029D
SOIC−8 EP
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”, may
or may not be present and may be in either
location. Some products may not follow the
Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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