NCV8415DTRKG

Self-Protected Low Side Driver with In-Rush Current Management NCV8415 The NCV8415 is a three terminal protected Low−Side Smart Discrete FET. The protection features include Delta Thermal Shutdown, overcurrent, overtemperature, ESD and integrated Drain−to−Gate clamping for overvoltage protection. The device also offers fault indication via the gate pin. This device is suitable for harsh automotive environments. www.onsemi.com VDSS (Clamped) RDS(ON) TYP ID MAX (Limited) 42 V 80 mW @ 10 V 11 A Features • • • • • • • • • • Short−Circuit Protection with In−Rush Current Management Delta Thermal Shutdown Thermal Shutdown with Automatic Restart Overvoltage Protection Integrated Clamp for Overvoltage Protection and Inductive Switching ESD Protection dV/dt Robustness Analog Drive Capability (Logic Level Input) NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Grade 1 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant SOT−223 CASE 318E STYLE 3 MARKING DIAGRAMS 4 AYW 8415G G 1 Typical Applications • Switch a Variety of Resistive, Inductive and Capacitive Loads • Can Replace Electromechanical Relays and Discrete Circuits • Automotive / Industrial 1 2 3 Drain AYWW NCV 8415G 1 = Gate 2 = Drain 3 = Source 4 = Drain 4 = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ESD Protection Temperature Limit Pin Marking Information 2 3 SOT−223 DPAK A Y W, WW G or G Overvoltage Protection Gate Input DPAK CASE 369C STYLE 2 Current Limit ORDERING INFORMATION Current Sense Device Package Shipping† NCV8415DTRKG DPAK (Pb−Free) 2500 / Tape & Reel NCV8415STT1G SOT−223 (Pb−Free) 1000 / Tape & Reel NCV8415STT3G SOT−223 (Pb−Free) 4000 / Tape & Reel Source Figure 1. Block Diagram †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2018 January, 2021 − Rev. 0 1 Publication Order Number: NCV8415/D NCV8415 MAXIMUM RATINGS Rating Symbol Value Unit Drain−to−Source Voltage Internally Clamped VDSS 42 V Drain−to−Gate Voltage Internally Clamped VDG 42 V Gate−to−Source Voltage VGS ±14 V Drain Current − Continuous ID Total Power Dissipation (SOT−223) @ TA = 25°C (Note 1) @ TA = 25°C (Note 2) PD Internally Limited 1.29 2.20 Total Power Dissipation (DPAK) @ TA = 25°C (Note 1) @ TA = 25°C (Note 2) W 1.54 2.99 °C/W Thermal Resistance (SOT−223) Junction−to−Ambient (Note 1) Junction−to−Ambient (Note 2) Junction−to−Case (Soldering Point) RqJA RqJA RqJS 96.4 56.8 10.6 Thermal Resistance (DPAK) Junction−to−Ambient (Note 1) Junction−to−Ambient (Note 2) Junction−to−Case (Soldering Point) RqJA RqJA RqJS 80.8 41.8 3.2 Single Pulse Inductive Load Switching Energy (L = 10 mH, ILpeak = 4.2 A, VGS = 5 V, RG = 25 W, TJstart = 25°C) EAS 88 Load Dump Voltage (VGS = 0 and 10 V, RL = 10 W) (Note 3) US * 52 V TJ −40 to 150 °C Tstorage −55 to 150 °C Operating Junction Temperature Storage Temperature mJ Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Mounted onto a 80 × 80 × 1.6 mm single layer FR4 board (100 sq mm, 1 oz. Cu, steady state). 2. Mounted onto a 80 × 80 × 1.6 mm single layer FR4 board (645 sq mm, 1 oz. Cu, steady state). 3. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in production. Passed Class C according to ISO16750−1. ESD ELECTRICAL CHARACTERISTICS (Note 4, 5) Test Condition Parameter Electro−Static Discharge Capability Human Body Model (HBM) Symbol Min Typ Max Unit ESD 4000 − − V 1000 − − Charged Device Model (CDM) 4. Not tested in production. 5. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (JS−001−2017). Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes smaller than 2 × 2 mm due to the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current waveform characteristic defined in JEDEC JS−002−2018. + ID DRAIN IG + VDS GATE SOURCE VGS − − Figure 2. Voltage and Current Convention www.onsemi.com 2 NCV8415 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Test Condition Symbol Min Typ Max Unit VGS = 0 V, ID = 10 mA V(BR)DSS 42 46 51 V 42 44 51 − 0.6 2.0 − 2.4 10 IGSS − 50 70 OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage VGS = 0 V, ID = 10 mA, TJ = 150°C (Note 6) Zero Gate Voltage Drain Current VGS = 0 V, VDS = 32 V IDSS VGS = 0 V, VDS = 32 V, TJ = 150°C (Note 6) Gate Input Current VGS = 5 V, VDS = 0 V mA ON CHARACTERISTICS Gate Threshold Voltage VGS = VDS, ID = 150 mA VGS(th) 1.0 1.6 2.0 V VGS = VDS, ID = 150 mA (Note 6) VGS(th)/TJ − −4.0 − mV/°C VGS = 10 V, ID = 1.4 A RDS(ON) − 80 100 mW VGS = 10 V, ID = 1.4 A, TJ = 150°C (Note 6) − 150 190 VGS = 5.0 V, ID = 1.4 A − 105 120 VGS = 5.0 V, ID = 1.4 A, TJ = 150°C (Note 6) − 185 210 VGS = 5.0 V, ID = 0.5 A − 105 120 VGS = 5.0 V, ID = 0.5 A, TJ = 150°C (Note 6) − 185 210 VSD − 0.88 1.10 V ms Gate Threshold Temperature Coefficient Static Drain−to−Source On Resistance Source−Drain Forward On Voltage IS = 7 A, VGS = 0 V SWITCHING CHARACTERISTICS (Note 6) VGS = 0 V to 5 V, VDD = 12 V, ID = 1 A Turn−On Time (10% VGS to 90% ID) Turn−Off Time (90% VGS to 10% ID) VGS = 0 V to 10 V, VDD = 12 V, ID = 1 A Turn−On Time (10% VGS to 90% ID) tON − 30 35 tOFF − 44 55 tON − 13 20 tOFF − 70 90 Turn−On Rise Time (10% ID to 90% ID) trise − 9 15 Turn−Off Fall Time (90% ID to 10% ID) tfall − 29 40 Slew Rate On (80% VDS to 50% VDS) −dVDS/dtON 0.5 1.63 − Slew Rate Off (50% VDS to 80% VDS) dVDS/dtOFF 0.4 0.55 − ILIM 7.0 8.8 11 VGS = 5 V, VDS = 10 V, TJ = 150°C (Note 6) 6.4 7.9 9.1 VGS = 10 V, VDS = 10 V (Note 6) 5.2 8.2 11 VGS = 10 V, VDS = 10 V, TJ = 150°C (Note 6) 5.0 7.4 10 150 175 185 Turn−Off Time (90% VGS to 10% ID) V/ms SELF PROTECTION CHARACTERISTICS Current Limit VGS = 5 V, VDS = 10 V Temperature Limit (Turn−Off) VGS = 5.0 V (Note 6) Thermal Hysteresis Temperature Limit (Turn−Off) VGS = 10 V (Note 6) Thermal Hysteresis TLIM(OFF) DTLIM(ON) − 15 − TLIM(OFF) 150 185 200 DTLIM(ON) − 15 − IGON 35 50 70 250 310 450 45 76 95 320 450 550 210 240 260 620 700 830 A °C GATE INPUT CHARACTERISTICS (Note 6) Device ON Gate Input Current VGS = 5 V, VDS = 10 V, ID = 1 A VGS = 10 V, VDS = 10 V, ID = 1 A Current Limit Gate Input Current VGS = 5 V, VDS = 10 V IGCL VGS = 10 V, VDS = 10 V Thermal Limit Gate Input Current VGS = 5 V, VDS = 10 V, ID = 0 A VGS = 10 V, VDS = 10 V, ID = 0 A IGTL mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Not subject to production testing. www.onsemi.com 3 NCV8415 TYPICAL PERFORMANCE CURVES 10 TJ(start) = 25°C Emax (mJ) ILmax (A) 1000 TJ(start) = 25°C 100 TJ(start) = 150°C TJ(start) = 150°C 1 10 10 10 100 L (mH) Figure 3. Single Pulse Maximum Switch−Off Current vs. Load Inductance 100 L (mH) Figure 4. Single Pulse Maximum Switching Energy vs. Load Inductance 1000 Emax (mJ) ILmax (A) 10 TJ(start) = 25°C TJ(start) = 25°C 100 TJ(start) = 150°C TJ(start) = 150°C 1 1 10 10 tav (ms) 1 Figure 5. Single Pulse Maximum Inductive Switch−Off Current vs. Time in Avalanche 12 7V 6V TA = 25°C 10 tav (ms) Figure 6. Single Pulse Maximum Inductive Switching Energy vs. Time in Avalanche 10 9V VDS = 10 V 10 8 6 8V 10 V 5V 4 4V 6 4 −40°C 3V 25°C 105°C 2 2 0 ID (A) ID (A) 8 VGS = 2.5 V 0 1 2 3 4 150°C 0 5 1 VDS (V) Figure 7. On−State Output Characteristics 1.5 2 2.5 3.5 3 VGS (V) 4 4.5 Figure 8. Transfer Characteristics www.onsemi.com 4 5 NCV8415 TYPICAL PERFORMANCE CURVES 300 210 190 250 RDS(ON) (mW) RDS(ON) (mW) 200 150°C, ID = 1.4 A 150 150°C, ID = 0.5 A 105°C, ID = 1.4 A 105°C, ID = 0.5 A −40°C, ID = 1.4 A 100 50 150°C, VGS = 5 V 170 3 4 6 7 VGS (V) 8 9 150°C, VGS = 10 V 130 105°C, VGS = 10 V 110 25°C, VGS = 5 V 25°C, VGS = 10 V 70 25°C, ID = 0.5 A 5 150 90 25°C, ID = 1.4 A −40°C, ID = 0.5 A 105°C, VGS = 5 V 50 0.2 10 0.4 Figure 9. RDS(ON) vs. Gate−Source Voltage 0.6 0.8 1 1.2 ID (A) 1.4 1.6 1.8 2 Figure 10. RDS(ON) vs. Drain Current 2.0 12 ID = 1.4 A 1.75 VDS = 10 V 11.5 −40°C 11 10.5 1.5 VGS = 5 V ILIM (A) Normalized RDS(ON) −40°C, VGS = 5 V −40°C, VGS = 10 V 1.25 1.0 VGS = 10 V 25°C 10 9.5 105°C 9 150°C 8.5 8 0.75 7.5 0.5 −40 −20 0 20 40 60 TJ (5C) 80 100 120 7 140 5 Figure 11. Normalized RDS(ON) vs. Temperature 5.5 6 6.5 7 7.5 8 VGS (V) 8.5 9.5 9 10 Figure 12. Current Limit vs. Gate−Source Voltage 10 100 VDS = 10 V VGS = 0 V 9.5 10 IDSS (mA) ILIM (A) 9 VGS = 10 V 8.5 8 VGS = 5 V −20 0 20 40 60 80 100 120 0.001 10 140 150°C 105°C 0.1 0.01 7.5 7 −40 1 25°C −40°C 15 20 25 30 35 TJ (5C) VDS (V) Figure 13. Current Limit vs. Junction Temperature Figure 14. Drain−to−Source Leakage Current www.onsemi.com 5 40 NCV8415 TYPICAL PERFORMANCE CURVES 1.2 1.1 1.1 1 1 0.9 0.7 0.7 0.6 0.6 −40 0.5 −20 0 20 40 60 80 100 120 140 1 Drain−Source Voltage Slope (V/ms) 60 tr tOFF 20 tf 4 5 6 7 VGS (V) 8 9 10 tOFF, VGS = 10 V 60 Time (ms) 6 7 8 9 50 tOFF, VGS = 5 V 40 tON, VGS = 5 V 30 tr, VGS = 5 V 20 10 tf, VGS = 5 V tf, VGS = 10 V 500 tON, VGS = 10 V 1000 RG (W) tr, VGS = 10 V 1500 10 1.5 −dVDS/dtON 1.0 dVDS/dtOFF 0.5 0 3 4 5 6 7 VGS (V) 8 9 10 Figure 18. Resistive Load Switching Drain−Source Voltage Slope vs. Gate−Source Voltage Drain−Source Voltage Slope (V/ms) VDD = 12 V ID = 1 A 0 5 VDD = 12 V ID = 1 A RG = 0 W Figure 17. Resistive Load Switching Time vs. Gate−Source Voltage 0 4 2 tON 80 70 3 Figure 16. Source−Drain Diode Forward Characteristics 100 80 2 Figure 15. Normalized Threshold Voltage vs. Temperature 120 Time (ms) 150°C IS (A) VDD = 12 V ID = 1 A RG = 0 W 3 105°C TJ (5C) 140 40 25°C 0.8 0.8 0 −40°C 0.9 VSD (V) Normalized VGS(th) (V) VGS = 0 V ID = 150 mA VDS = VGS 2 1.8 1.4 1.2 Figure 19. Resistive Load Switching Time vs. Gate Resistance dVDS/dtOFF, VGS = 5 V 1 dVDS/dtOFF, VGS = 10 V 0.8 0.6 −dVDS/dtON, VGS = 5 V 0.4 VDD = 12 V ID = 1 A 0.2 0 2000 −dVDS/dtON, VGS = 10 V 1.6 0 500 1000 RG (W) 1500 2000 Figure 20. Resistive Load Switching Drain−Source Voltage Slope vs. Gate Resistance www.onsemi.com 6 NCV8415 100 90 90 80 80 70 RqJA (5C/W) RqJA (5C/W) TYPICAL PERFORMANCE CURVES PCB Cu thickness, 1.0 oz 70 60 50 40 100 200 300 50 40 PCB Cu thickness, 2.0 oz 0 PCB Cu thickness, 1.0 oz 60 400 500 600 30 800 700 PCB Cu thickness, 2.0 oz 0 100 200 300 400 500 600 700 Copper Heat Spreader Area (mm2) Copper Heat Spreader Area (mm2) Figure 21. RqJA vs. Copper Area (SOT−223) Figure 22. RqJA vs. Copper Area (DPAK) 800 100 50% Duty Cycle 20% Duty Cycle RqJA(t) (5C/W) 10 10% Duty Cycle 5% Duty Cycle 2% Duty Cycle 1 1% Duty Cycle 0.1 Single Pulse 0.01 0.000001 80 × 80 × 1.6 mm Single−Layer PCB, 645 mm2 1 oz. Copper 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 Pulse Width (s) Figure 23. Transient Thermal Resistance (SOT−223) 100 50% Duty Cycle RqJA(t) (5C/W) 10 20% Duty Cycle 10% Duty Cycle 5% Duty Cycle 1 2% Duty Cycle 1% Duty Cycle 0.1 Single Pulse 0.01 0.000001 80 × 80 × 1.6 mm Single−Layer PCB, 645 mm2 1 oz. Copper 0.00001 0.0001 0.001 0.01 0.1 1 Pulse Width (s) Figure 24. Transient Thermal Resistance (DPAK) www.onsemi.com 7 10 100 1000 NCV8415 APPLICATION INFORMATION Circuit Protection Features junction temperature is exceeded. When activated at typically 175°C, the NCV8415 turns off. This feature is provided to prevent failures from accidental overheating. The NCV8415 has three main protections. Current Limit, Thermal Shutdown and Delta Thermal Shutdown. These protections establish robustness of the NCV8415. EMC Performance Current Limit and Short Circuit Protection To improve the EMC performance/robustness, connect a small ceramic capacitor to the drain pin as close to the device as possible according to Figure 25. The NCV8415 has current sense element. In the event that the drain current reaches designed current limit level, integrated Current Limit protection establishes its constant level. RL Delta Thermal Shutdown Delta Thermal Shutdown (DTSD) Protection increases higher reliability of the NCV8415. DTSD consist of two independent temperature sensors – cold and hot sensors. The NCV8415 establishes a slow junction temperature rise by sensing the difference between the hot and cold sensors. ON/OFF output cycling is designed with hysteresis that results in a controlled saw tooth temperature profile (Figure 26). The die temperature slowly rises (DTSD) until the absolute temperature shutdown (TSD) is reached around 175°C. Gate D VDD G DUT S C Thermal Shutdown with Automatic Restart Internal Thermal Shutdown (TSD) circuitry is provided to protect the NCV8415 in the event that the maximum Figure 25. EMC Capacitor Placement TEST CIRCUITS AND WAVEFORMS Thermal Transient Limitation Phase Overtemperature Cycling VG ILIM ID INOM TSD Delta TSD activation TJ Time Figure 26. Overload Protection Behavior www.onsemi.com 8 Nominal Load + − NCV8415 TEST CIRCUITS AND WAVEFORMS RL VIN D RG VDD G DUT + − S IDS Figure 27. Resistive Load Switching Test Circuit 90% VIN 10% tON tOFF tr tf 90% IDS 10% Time Figure 28. Resistive Load Switching Waveforms www.onsemi.com 9 NCV8415 TEST CIRCUITS AND WAVEFORMS L VDS VIN D RG + VDD G DUT − S tp IDS Figure 29. Inductive Load Switching Test Circuit 5V VIN 0V tav tp V(BR)DSS Ipk VDD VDS IDS VDS(on) Time Figure 30. Inductive Load Switching Waveforms www.onsemi.com 10 0 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−223 (TO−261) CASE 318E−04 ISSUE R DATE 02 OCT 2018 SCALE 1:1 q q DOCUMENT NUMBER: DESCRIPTION: 98ASB42680B SOT−223 (TO−261) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com SOT−223 (TO−261) CASE 318E−04 ISSUE R STYLE 1: PIN 1. 2. 3. 4. BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. ANODE CATHODE NC CATHODE STYLE 6: PIN 1. 2. 3. 4. RETURN INPUT OUTPUT INPUT STYLE 7: PIN 1. 2. 3. 4. ANODE 1 CATHODE ANODE 2 CATHODE STYLE 11: PIN 1. MT 1 2. MT 2 3. GATE 4. MT 2 STYLE 3: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN STYLE 8: STYLE 12: PIN 1. INPUT 2. OUTPUT 3. NC 4. OUTPUT CANCELLED DATE 02 OCT 2018 STYLE 4: PIN 1. 2. 3. 4. SOURCE DRAIN GATE DRAIN STYLE 5: PIN 1. 2. 3. 4. STYLE 9: PIN 1. 2. 3. 4. INPUT GROUND LOGIC GROUND STYLE 10: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE DRAIN GATE SOURCE GATE STYLE 13: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR GENERIC MARKING DIAGRAM* AYW XXXXXG G 1 A = Assembly Location Y = Year W = Work Week XXXXX = Specific Device Code G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASB42680B SOT−223 (TO−261) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE G 4 1 2 DATE 31 MAY 2023 3 SCALE 1:1 GENERIC MARKING DIAGRAM* STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR DOCUMENT NUMBER: DESCRIPTION: STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE 98AON10527D DPAK (SINGLE GAUGE) XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete XXXXXX A L Y WW G = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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