NCV8411DTRKG

ON Semiconductor Is Now To learn more about onsemi™, please visit our website at www.onsemi.com onsemi and       and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others. NCV8411 Self-Protected Low Side Driver with In-Rush Current Management The NCV8411 is a three terminal protected Low−Side Smart Discrete FET. The protection features include Delta Thermal Shutdown, overcurrent, overtemperature, ESD and integrated Drain to Gate clamping for over voltage protection. The device also offers fault indication via the gate pin. This device is suitable for harsh automotive environments. Features • • • • • • • • • • Short Circuit Protection with In−Rush Current Management Delta Thermal Shutdown Thermal Shutdown with Automatic Restart Over Voltage Protection Integrated Clamp for Over Voltage Protection and Inductive Switching ESD Protection dV/dt Robustness Analog Drive Capability (Logic Level Input) NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant Typical Applications • Switch a Variety of Resistive, Inductive and Capacitive Loads • Can Replace Electromechanical Relays and Discrete Circuits • Automotive / Industrial Overvoltage Protection Current Limit ID MAX (Limited) 42 V 23 mW @ 10 V 45 A DPAK CASE 369C STYLE 2 MARKING DIAGRAM 1 = Gate 2 = Drain 3 = Source A Y WW G 1 2 3 AYWW NCV 8411G = Assembly Location = Year = Work Week = Pb−Free Package Device Package Shipping† NCV8411DTRKG DPAK (Pb−Free) 2500/Tape & Reel Current Sense Figure 1. Block Diagram © Semiconductor Components Industries, LLC, 2017 January, 2019 − Rev. 0 RDS(ON) TYP †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. ESD Protection Temperature Limit VDSS (Clamped) ORDERING INFORMATION Drain Gate Input www.onsemi.com Source 1 Publication Order Number: NCV8411/D NCV8411 Table 1. MAXIMUM RATINGS Rating Symbol Value (min) Unit Drain−to−Source Voltage Internally Clamped VDSS 42 V Drain−to−Gate Voltage Internally Clamped VDG 42 V Gate−to−Source Voltage VGS ±14 V Drain Current − Continuous ID Total Power Dissipation @ TA = 25°C (Note 1) @ TA = 25°C (Note 2) PD Thermal Resistance Junction−to−Case Junction−to−Ambient (Note 1) Junction−to−Ambient (Note 2) Internally Limited 1.3 2.7 W °C/W RthJC RthJA RthJA 0.65 95 45 Single Pulse Inductive Load Switching Energy (Note 3) (L = 120 mH, TJ(start) = 150°C) EAS 600 Load Dump Voltage (VGS = 0 and 10 V, RG = 2 W, RL = 3 W) (Note 4) US * 55 V TJ −40 to 150 °C Tstorage −55 to 150 °C ESD 4 kV Operating Junction Temperature Storage Temperature mJ ESD CHARACTERISTICS (Note 3) Electro−Static Discharge Capability Human Body Model (HBM) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Mounted onto a 2″ square FR4 board (100 sq mm, 1 oz. Cu, steady state) 2. Mounted onto a 2″ square FR4 board (645 sq mm, 1 oz. Cu, steady state) 3. Not tested in production. 4. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in production. Passed Class C according to ISO16750−1. + ID DRAIN IG + VDS GATE SOURCE VGS − − Figure 2. Voltage and Current Convention www.onsemi.com 2 NCV8411 Table 2. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Test Conditions Symbol Min Typ Max Unit VGS = 0 V, ID = 250 mA V(BR)DSS 42 42 46 50 V 44 50 − 1.5 5 − 5.5 − OFF CHARACTERISTICS Drain−to−Source Clamped Breakdown Voltage VGS = 0 V, ID = 250 mA, TJ = 150°C (Note 5) Zero Gate Voltage Drain Current IDSS VDS = 32 V, VGS = 0 V VDS = 32 V, VGS = 0 V, TJ = 150°C (Note 5) Gate Input Current mA VGS = 5 V, VDS = 0 V IGSS − 50 100 VGS = VDS, ID = 1.2 mA VGS(th) 1.0 1.8 2.5 V − 5 − mV/°C mW mA ON CHARACTERISTICS Gate Threshold Voltage Threshold Temperature Coefficient VGS = VDS, ID = 1.2 mA (Note 5) Static Drain−to−Source On Resistance VGS = 10 V, ID = 5 A, TJ = 25°C RDS(ON) − 23 29 VGS = 10 V, ID = 5 A, TJ = 150°C (Note 5) − 43 55 VGS = 5 V, ID = 5 A, TJ = 25°C − 28 34 VGS = 5 V, ID = 5 A, TJ = 150°C (Note 5) − 50 60 VSD − 0.8 1.1 V ms Source Drain Forward On Voltage IS = 5 A, VGS = 0 V SWITCHING CHARACTERISTICS (Note 5) VGS = 0 V to 5 V, VDS = 12 V, ID = 1 A Turn−On Time (10% VGS to 90% ID) Turn−Off Time (90% VGS to 10% ID) VGS = 0 V to 10 V, VDS = 12 V, ID = 1 A Turn−On Time (10% VGS to 90% ID) tON − 29 50 tOFF − 53 150 tON − 14 25 tOFF − 80 180 VGS = 0 V to 10 V, VDD = 12 V, RL = 4.7 W −dVDS/dtON − 1.52 2.5 dVDS/dtOFF − 0.71 0.85 VGS = 5 V, VDS = 10 V ILIM 29 33 40 VGS = 5 V, VDS = 10 V, TJ = 150°C (Note 5) 27 31 37 VGS = 10 V, VDS = 10 V (Note 5) 23 34 46 VGS = 10 V, VDS = 10 V, TJ = 150°C (Note 5) 23 33 46 150 170 185 Turn−Off Time (90% VGS to 10% ID) Slew Rate On (80% VDS to 50% VDS) Slew Rate Off (50% VDS to 80% VDS) V/ms SELF PROTECTION CHARACTERISTICS Current Limit VGS = 5 V (Note 5) Temperature Limit (Turn−Off) TLIM(OFF) Thermal Hysteresis DTLIM(ON) − 10 − TLIM(OFF) 150 180 200 DTLIM(ON) − 10 − IGON − 50 100 200 318 500 VGS = 10 V (Note 5) Temperature Limit (Turn−Off) Thermal Hysteresis A °C GATE INPUT CHARACTERISTICS (Note 5) Device ON Gate Input Current − Normal Operation Device ON Gate Input Current − Thermal Limit Device ON Gate Input Current − Current Limit VGS = 5 V, VDS = 10 V, ID = 1 A VGS = 10 V, VDS = 10 V, ID = 1 A VGS = 5 V, VDS = 10 V, ID = 0 A IGTL VGS = 10 V, VDS = 10 V, ID = 0 A VGS = 5 V, VDS = 10 V VGS = 10 V, VDS = 10 V IGCL − 633 900 − 1470 2000 − 245 600 − 1121 1500 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Not tested in production. www.onsemi.com 3 NCV8411 TYPICAL PERFORMANCE CURVES 10000 100 1000 Emax (mJ) ILmax (A) TJ(start) = 25°C 10 TJ(start) = 150°C 1 TJ(start) = 25°C TJ(start) = 150°C 100 10 1 10 1 100 10 Figure 3. Single Pulse Maximum Switch-off Current vs. Load Inductance Figure 4. Single Pulse Maximum Switching Energy vs. Load Inductance 10000 Emax (mJ) 100 ILmax (A) 100 L (mH) L (mH) TJ(start) = 25°C 10 TJ(start) = 25°C 1000 TJ(start) = 150°C TJ(start) = 150°C 1 1 10 100 100 1 10 Time in Avalanche (ms) Time in Avalanche (ms) Figure 5. Single Pulse Maximum Inductive Switch-off Current vs. Time in Avalanche 45 35 10 V 30 25 4V 20 ID (A) 25 3V 15 20 15 10 10 VGS = 2.5 V 5 0 −40°C 25°C 100°C 150°C 30 8V 35 ID (A) Figure 6. Single Pulse Maximum Inductive Switching Energy vs. Time in Avalanche 7V 40 100 0 1 2 3 4 5 0 5 VDS = 10 V 1 VDS (V) 1.5 2 2.5 3 3.5 4 VGS (V) Figure 7. On-state Output Characteristics at 255C Figure 8. Transfer Characteristics www.onsemi.com 4 4.5 5 NCV8411 TYPICAL PERFORMANCE CURVES 70 45 ID = 3 A 60 150°C, VGS = 10 V 35 RDS(on) (mW) 50 RDS(on) (mW) 150°C, VGS = 5 V 40 150°C 40 105°C 30 105°C, VGS = 5 V 105°C, VGS = 10 V 30 25 25°C, VGS = 5 V 20 25°C, VGS = 10 V 15 −40°C, VGS = 5 V 25°C 20 −40°C 10 10 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 −40°C, VGS = 10 V 1 2 3 4 5 VGS (V) 10 VDS = 10 V −40°C 40 25°C 100°C 38 VGS = 5 V 1.25 1 ILIM (A) Normalized RDS(on) 9 42 ID = 5 A 1.5 150°C 36 34 VGS = 10 V 0.75 32 0,5 −40 −20 0 20 40 60 80 30 100 120 140 5 5.5 6 6.5 7 TJ (5C) 7.5 8 8.5 9 9.5 10 VGS (V) Figure 11. Normalized RDS(on) vs. Temperature Figure 12. Current Limit vs. Gate-Source Voltage 50 100 VGS = 0 V VDS = 10 V 10 VGS = 10 V IDSS (mA) 40 ILIM (A) 8 Figure 10. RDS(on) vs. Drain Current 2 45 7 ID (A) Figure 9. RDS(on) vs. Gate-Source Voltage 1.75 6 35 VGS = 5 V 30 150°C 25°C 1 105°C −40°C 0.1 25 20 −40 −20 0 20 40 60 80 0.01 100 120 140 10 15 20 25 30 35 VDS (V) TJ (5C) Figure 13. Current Limit vs. Junction Temperature Figure 14. Drain-to-Source Leakage Current www.onsemi.com 5 40 NCV8411 1.2 1 1.1 0.9 −40°C 1 0.8 25°C VSD (V) Normalized VGS(th) TYPICAL PERFORMANCE CURVES 0.9 0.8 0.7 105°C 0.6 ID = 1.2 mA VDS = VGS 0.7 0.6 −40 −20 150°C 0.5 0 20 40 60 80 0.4 100 120 140 VGS = 0 V 1 2 3 4 5 TJ (5C) Drain-Source Voltage Slope (V/ms) VDD = 25 V, ID = 5 A, RG = 0 W tr 160 140 Time (ms) 9 10 2.5 180 120 100 td(off) 80 td(on) 60 40 tf 20 3 4 5 6 7 8 9 10 VDD = 25 V, ID = 5 A, RG = 0 W 1.5 dVDS/dt(off) 1 0.5 0 3 4 5 td(off), VGS = 10 V 80 td(off), VGS = 5 V 70 60 50 tf, VGS = 10 V 40 tr, VGS = 5 V td(on), VGS = 5 V 30 20 10 tf, VGS = 5 V 0 td(on), VGS = 10 V 7 8 9 10 Figure 18. Resistive Load Switching Drain-Source Voltage Slope vs. Gate-Source Voltage Drain-Source Voltage Slope (V/ms) VDD = 25 V, ID = 5 A 90 6 VGS (V) Figure 17. Resistive Load Switching Time vs. Gate-Source Voltage 100 −dVDS/dt(on) 2 VGS (V) Time (ms) 8 Figure 16. Source-Drain Diode Forward Characteristics 200 0 7 IS (A) Figure 15. Normalized Threshold Voltage vs. Temperature 0 6 tr, VGS = 10 V 2 1.8 −dVDS/dt(on), VGS = 5 V 1.4 1.2 1 dVDS/dt(on), VGS = 5 V 0.8 dVDS/dt(on), VGS = 10 V 0.6 0.4 VDD = 25 V, ID = 5 A 0.2 0 200 400 600 800 1000 1200 1400 1600 1800 2000 −dVDS/dt(on), VGS = 10 V 1.6 0 RG (W) 200 400 600 800 1000 1200 1400 1600 1800 2000 RG (W) Figure 19. Resistive Load Switching Time vs. Gate Resistance Figure 20. Drain-Source Voltage Slope during Turn On and Turn Off vs. Gate Resistance www.onsemi.com 6 NCV8411 TYPICAL PERFORMANCE CURVES 90 80 RqJA (5C/W) 70 60 PCB Cu thickness, 1.0 oz 50 40 PCB Cu thickness, 2.0 oz 30 20 0 200 400 600 800 1000 1200 1400 Copper Heat Spread Area (mm2) RqJA 645 mm2 5C/W, 2 oz. Copper Figure 21. RqJA vs. Copper Area 100 50% Duty Cycle 10 20% 10% 5% 1 2% 1% 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 Pulse Width (s) Figure 22. Transient Thermal Resistance www.onsemi.com 7 1 10 100 1000 NCV8411 APPLICATION INFORMATION Circuit Protection Features NCV8411 establishes a slow junction temperature rise by sensing the difference between the hot and cold sensors. ON/OFF output cycling is designed with hysteresis that results in a controlled saw tooth temperature profile (Figure 23). The die temperature slowly rises (DTSD) until the absolute temperature shutdown (TSD) is reached around 175°C. The NCV8411 has three main protections. Current Limit, Thermal Shutdown and Delta Thermal Shutdown. These protections establish robustness of the NCV8411. Current Limit and Short Circuit Protection The NCV8411 has current sense element. In the event that the drain current reaches designed current limit level, integrated Current Limit protection establishes its constant level. Thermal Shutdown with Automatic Restart Internal Thermal Shutdown (TSD) circuitry is provided to protect the NCV8411 in the event that the maximum junction temperature is exceeded. When activated at typically 175°C, the NCV8411 turns off. This feature is provided to prevent failures from accidental overheating. Delta Thermal Shutdown Delta Thermal Shutdown (DTSD) Protection increases higher reliability of the NCV8411. DTSD consist of two independent temperature sensors – cold and hot sensors. The TEST CIRCUITS AND WAVEFORMS Overtemperature Cycling Thermal Transient Limitation Phase VG ILIM ID INOM TSD Delta TSD Activation TJ Time Figure 23. Overload Protection Behavior www.onsemi.com 8 Nominal Load NCV8411 TEST CIRCUITS AND WAVEFORMS RL VIN D RG G VDD DUT + − S IDS Figure 24. Resistive Load Switching Test Circuit 90% VIN 10% tON tOFF 90% 10% IDS Time Figure 25. Resistive Load Switching Waveforms www.onsemi.com 9 NCV8411 TEST CIRCUITS AND WAVEFORMS L VDS VIN D RG G VDD DUT + − S tp IDS Figure 26. Inductive Load Switching Test Circuit 5V VIN 0V tav tp V(BR)DSS Ipk VDD VDS VDS(on) IDS 0 Time Figure 27. Inductive Load Switching Waveform www.onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E C A b3 B c2 4 L3 Z D 1 2 H DETAIL A 3 L4 NOTE 7 c SIDE VIEW b2 e b 0.005 (0.13) TOP VIEW BOTTOM VIEW C M Z H L2 GAUGE PLANE C L SEATING PLANE BOTTOM VIEW A1 L1 DETAIL A Z ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. 2.58 0.102 1.60 0.063 IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. 6.17 0.243 SCALE 3:1 AYWW XXX XXXXXG XXXXXX A L Y WW G 3.00 0.118 5.80 0.228 XXXXXXG ALYWW mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: STATUS: NEW STANDARD: 98AON10527D ON SEMICONDUCTOR STANDARD REF TO JEDEC TO−252 http://onsemi.com DPAK SINGLE GAUGE SURFACE 1 MOUNT © Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 − Rev. 0 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. Case Outline Number: PAGE 1 OFXXX 2 DOCUMENT NUMBER: 98AON10527D PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION. REQ. BY L. GAN 24 SEP 2001 A ADDED STYLE 8. REQ. BY S. ALLEN. 06 AUG 2008 B ADDED STYLE 9. REQ. BY D. WARNER. 16 JAN 2009 C ADDED STYLE 10. REQ. BY S. ALLEN. 09 JUN 2009 D RELABELED DRAWING TO JEDEC STANDARDS. ADDED SIDE VIEW DETAIL A. CORRECTED MARKING INFORMATION. REQ. BY D. TRUHITTE. 29 JUN 2010 E ADDED ALTERNATE CONSTRUCTION BOTTOM VIEW. MODIFIED DIMENSIONS b2 AND L1. CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY I. CAMBALIZA. 06 FEB 2014 F ADDED SECOND ALTERNATE CONSTRUCTION BOTTOM VIEW. REQ. BY K. MUSTAFA. 21 JUL 2015 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. © Semiconductor Components Industries, LLC, 2015 July, 2015 − Rev. F Case Outline Number: 369C ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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