DATA SHEET
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Voltage Regulator - Low Iq,
Low Dropout, Power Good
Output
GENERIC MARKING
DIAGRAMS
1
NCV8187
The NCV8187 is 1.2 A LDO Linear Voltage Regulator. It is a very
stable and accurate device with low quiescent current consumption
(typ. 30 mA over the full temperature range), low dropout, low output
noise and very good PSRR. The regulator incorporates several
protection features such as Thermal Shutdown, Soft Start, Current
Limiting and also Power Good Output signal for easy MCU
interfacing.
•
•
Operating Input Voltage Range: 1.5 V to 5.5 V
Adjustable and Fixed Voltage Options Available: 0.8 V to 5.2 V
Low Quiescent Current: typ. 30 mA over Temperature
±2% Accuracy Over Full Load, Line and Temperature variations
PSRR: 75 dB at 1 kHz
Low Noise: typ. 15 mVRMS from 10 Hz to 100 kHz
Stable With Small 10 mF Ceramic Capacitor
Soft−start to Reduce Inrush Current and Overshoots
Thermal Shutdown and Current Limit Protection
Power Good Signal Extends Application Range
Available in WDFN6 and WDFNW6 2x2, DFN6 3x3, DFNW6 3x3,
DFNW8 3x3 and DPAK−5 with Wettable Flank (pin edge plating)
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
•
•
•
•
•
•
•
1
1
DFN6/DFNW6 3x3
CASE 506DK & 507AW
1
1
Features
•
•
•
•
•
•
•
•
•
•
•
XX M
WDFN6/WDFNW6 2x2
CASE 511BR & 511DW
1.2 A
DFNW8 3x3
CASE 507AD
XXXXX
XXXXX
ALYWG
G
XXXXXX
XXXXXX
ALYWG
G
XXXXXXG
ALYWW
DPAK−5
CASE 175AA
XXXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W/WW = Work Week
D
= Date Code
G/G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
Wireless Chargers and Portable Equipment
Smart Camera and Robotic Vision Systems
Telecommunication and Networking Systems
Infotainment and Cluster
Modular Platforms for Dashboard Display
Internet Connection Sharing (ICS) Gateway Server Applications
General Purpose Automotive
VIN
CIN
IN
1 mF
Ceramic
EN
OUT
NCV8187
SNS
GND
PG
ON
VOUT
COUT
10 mF
Ceramic
OFF
Figure 1. Typical Application Schematic
© Semiconductor Components Industries, LLC, 2018
August, 2021 − Rev. 8
1
Publication Order Number:
NCV8187/D
NCV8187
PIN FUNCTION CONNECTION
DFN6 3x3 mm,
DFNW6 3x3 mm
(Top View)
WDFN6 2x2 mm
WDFNW6 2x2 mm
(Top View)
DFNW8 3x3 mm
(Top View)
DPAK−5
(Top View)
Figure 2. Pin Function Connection
PIN FUNCTION DESCRIPTION
Pin No.
WDFN6 &
WDFNW6
2x2
Pin No.
DFN6 &
DFNW6
3x3
Pin No.
DFNW8
3x3
Pin No.
DPAK−5
Pin
Name
1
6
8
2
IN
6
4
1
4
OUT
Regulated output voltage pin. A small 10 mF ceramic capacitor is needed
from this pin to ground to assure stability
3, EXP
2, EXP
5, EXP
TAB
GND
Power supply ground
2
1
7
1
EN
5
−
2/−
5/−
SNS
Sense pin. Connect this pin to regulated output voltage
−
−
−/2
−/5
ADJ
Adjustable feedback voltage input. Connect this pin to external resistor
divider for desired voltage output
4
3
3
−
PG
Power Good, open collector. Use 10 kW to 100 kW pull−up
resistor connected to output or input voltage
−
5
4, 6
−
NC
No connection. This pin can be tied to ground to improve
thermal dissipation or left disconnected
Description
Input pin. A small capacitor is needed from this pin to ground to assure
stability
Enable pin. Driving this pin high turns on the regulator. Driving EN pin low
puts the regulator into shutdown mode
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NCV8187
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Input Voltage (Note 1)
Ratings
VIN
−0.3 to 6
V
Enable Voltage
VEN
−0.3 to 6
V
Power Good Current
IPG
30
mA
Power Good Voltage
VPG
−0.3 to 6
V
Output Voltage
VOUT
−0.3 to VIN + 0.3 (max. 5.5)
V
Output Short Circuit Duration
tSC
Indefinite
s
TJ(MAX)
150
°C
TSTG
−55 to 150
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
2000
V
ESD Capability, Machine Model (Note 2)
ESDMM
200
V
Maximum Junction Temperature
Storage Temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
THERMAL CHARACTERISTICS, WDFN6, 2x2, 0.65 PITCH PACKAGE
RqJA
51
°C/W
Thermal Resistance, Junction−to−Case (top)
RqJC(top)
142
°C/W
Thermal Resistance, Junction−to−Case (bottom) (Note 4)
RqJC(bot)
7.8
°C/W
Thermal Resistance, Junction−to−Board
RqJB
125
°C/W
Characterization Parameter, Junction−to−Top
YJT
2.0
°C/W
Characterization Parameter, Junction−to−Board
YJB
7.7
°C/W
Thermal Resistance, Junction−to−Ambient (Note 3)
THERMAL CHARACTERISTICS, DFN6 / DFNW6, 3x3, 0.95 PITCH PACKAGES
RqJA
50
°C/W
Thermal Resistance, Junction−to−Case (top)
RqJC(top)
142
°C/W
Thermal Resistance, Junction−to−Case (bottom) (Note 4)
RqJC(bot)
7.9
°C/W
RqJB
125
°C/W
Characterization Parameter, Junction−to−Top
YJT
2.0
°C/W
Characterization Parameter, Junction−to−Board
YJB
7.5
°C/W
Thermal Resistance, Junction−to−Ambient (Note 3)
Thermal Resistance, Junction−to−Board
3. The junction−to−ambient thermal resistance under natural convection is obtained in a simulation on a high−K board, following the JEDEC51.7
guidelines with assumptions as above, in an environment described in JESD51−2a.
4. The junction−to−case (bottom) thermal resistance is obtained by simulating a cold plate test on the IC exposed pad. Test description can
be found in the ANSI SEMI standard G30−88.
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NCV8187
ELECTRICAL CHARACTERISTICS − WDFN6 2x2, WDFNW6 2x2, DFN6 3x3 AND DFNW6 3x3 (−40°C ≤ TJ ≤ 150°C;
VIN = VOUT + 1.0 V; IOUT = 10 mA, CIN = 1 mF, COUT = 10 mF, unless otherwise noted. Typical values are at TJ = +25°C. (Note 6))
Test Conditions
Parameter
Operating Input Voltage
Output Voltage Accuracy
−40°C ≤ TJ ≤ 150°C,
VOUT +1 V < VIN < 5.5 V,
0 mA < IOUT < 1.2 A
VOUT < 1.7 V
Symbol
Min
Typ
Max
Unit
VIN
1.5
−
5.5
V
VOUT
−35 mV
−
+35 mV
V
−2%
−
+2%
VREF
−
0.8
−
V
VOUT ≥ 1.7 V
Reference Voltage
Line Regulation
VOUT + 1 V ≤ VIN ≤ 5.5 V, IOUT = 1 mA
RegLINE
−
40
−
mV/V
Load Regulation
IOUT = 0 mA to 1.2 A
RegLOAD
−
2
−
mV/mA
Dropout Voltage
VDO = VIN – (VOUT(NOM) – 3%)
IOUT = 1.2 A
VDO
−
325
495
mV
1.5 V – 1.7 V
−
240
400
1.8 V – 2.7 V
−
200
335
2.8 V – 3.2 V
−
165
250
3.3 V – 4.9 V
−
150
220
5V
−
120
180
IOUT
1300
1750
−
mA
1.2 V – 1.4 V
Maximum Output Current
(Note 7)
Short Circuit Current
(Note 7)
ISC
−
1850
−
mA
Disable Current
VEN = 0 V
IDIS
−
0.1
5.0
mA
Quiescent Current
IOUT = 0 mA
IQ
−
30
45
mA
Ground Current
IOUT = 1.2 A
IGND
−
2
−
mA
Power Supply Rejection
Ratio
VIN = 3.5 V + 100 mVpp
VOUT = 2.5 V
IOUT = 10 mA, COUT = 1 mF
PSRR
−
75
−
dB
Output Noise Voltage
VOUT = 1.8 V, IOUT = 10 mA, f = 10 Hz to 100 kHz
VN
−
15
−
mVrms
Enable Input Threshold
Voltage
Voltage increasing
VEN_HI
0.9
−
−
V
Voltage decreasing
VEN_LO
−
−
0.3
EN Pin Current
VEN = 5.5 V
−
100
−
nA
Active Output Discharge
Resistance
VIN = 5.5 V, VEN = 0 V
RDIS
−
120
−
W
Power Good, Output
Voltage Raising
VPGup
−
92
−
%
Power Good, Output
Voltage Falling
VPGdw
−
80
−
%
VPGlo
−
0.14
0.4
V
f = 1 kHz
Power Good Output
Voltage Low
IPG = 6 mA, Open drain
Thermal Shutdown
Temperature (Note 5)
Temperature increasing from TJ = +25°C
TSD
−
170
−
°C
Thermal Shutdown
Hysteresis (Note 5)
Temperature falling from TSD
TSDH
−
15
−
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Guaranteed by design and characterization.
6. Performance guaranteed over the indicated operating temperature range by design and/or characterization production tested at TJ =
TA = 25_C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
7. Respect SOA.
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NCV8187
ELECTRICAL CHARACTERISTICS − DFNW8 3x3 AND DPAK−5 (−40°C ≤ TJ ≤ 150°C; VIN = VOUT + 1.0 V; IOUT = 10 mA,
CIN = 1 mF, COUT = 10 mF, unless otherwise noted. Typical values are at TJ = +25°C. (Note 9))
Test Conditions
Parameter
Operating Input Voltage
Output Voltage Accuracy
−40°C ≤ TJ ≤ 150°C,
VOUT + 1 V < VIN < 5.5 V,
0 mA < IOUT < 1 A
VOUT < 1.7 V
Symbol
Min
Typ
Max
Unit
VIN
1.5
−
5.5
V
VOUT
−35 mV
−
+35 mV
V
−2%
−
+2%
VREF
−
1.2
−
V
VOUT ≥ 1.7 V
Reference Voltage
Line Regulation
VOUT + 1 V ≤ VIN ≤ 5.5 V, IOUT = 1 mA
RegLINE
−
40
−
mV/V
Load Regulation
IOUT = 0 mA to 1 A
RegLOAD
−
2
−
mV/mA
Dropout Voltage
VDO = VIN – (VOUT(NOM) – 3%)
IOUT = 1 A
VDO
−
295
450
mV
1.5 V – 1.7 V
−
220
360
1.8 V – 2.7 V
−
180
305
2.8 V – 3.2 V
−
150
225
3.3 V – 4.9 V
−
135
200
5V
−
110
165
1.2 V – 1.4 V
Maximum Output Current
(Note 10), TJ = 25°C
IOUT
1025
1500
1750
mA
Maximum Output Current
(Note 10)
IOUT
1025
1500
1950
mA
Short Circuit Current
(Note 10)
ISC
−
1550
−
mA
Disable Current
VEN = 0 V
IDIS
−
0.1
5.0
mA
Quiescent Current
IOUT = 0 mA
IQ
−
30
45
mA
Ground Current
IOUT = 1 A
IGND
−
2
−
mA
Power Supply Rejection
Ratio
VIN = 3.5 V + 100 mVpp
VOUT = 2.5 V
IOUT = 10 mA, COUT = 1 mF
PSRR
−
75
−
dB
Output Noise Voltage
VOUT = 1.8 V, IOUT = 10 mA, f = 10 Hz to 100 kHz
VN
−
15
−
mVrms
Enable Input Threshold
Voltage
Voltage increasing
VEN_HI
0.9
−
−
V
Voltage decreasing
VEN_LO
−
−
0.3
EN Pin Current
VEN = 5.5 V
Active Output Discharge
Resistance
VIN = 5.5 V, VEN = 0 V
f = 1 kHz
−
100
−
nA
RDIS
−
120
−
W
Power Good, Output
Voltage Raising
VPGup
−
92
−
%
Power Good, Output
Voltage Falling
VPGdw
−
80
−
%
VPGlo
−
0.14
0.4
V
Power Good Output
Voltage Low
IPG = 6 mA, Open drain
Thermal Shutdown
Temperature (Note 8)
Temperature increasing from TJ = +25°C
TSD
−
170
−
°C
Thermal Shutdown
Hysteresis (Note 8)
Temperature falling from TSD
TSDH
−
15
−
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Guaranteed by design and characterization.
9. Performance guaranteed over the indicated operating temperature range by design and/or characterization production tested at TJ =
TA = 25_C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
10. Respect SOA.
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NCV8187
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE (V)
1.215
1.210
1.820
VIN = 2.2 V
IOUT = 1 mA
COUT = 10 mF
1.815
OUTPUT VOLTAGE (V)
1.220
1.205
1.200
1.195
1.190
1.180
−40 −20
3.310
1.800
1.795
1.790
0
20
40
60
80
100
120
1.780
−40 −20
140
60
80
100
120
140
Figure 4. Output Voltage vs. Temperature –
VOUT = 1.8 V
450
VIN = 4.3 V
IOUT = 1 mA
COUT = 10 mF
425
3.295
3.290
3.285
400
VOUT = 1.2 V
IOUT = 1.2 A
COUT = 10 mF
375
350
325
300
275
250
225
3.280
−40 −20
0
20
40
60
80
100
120
200
−40 −20
140
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. Output Voltage vs. Temperature –
VOUT = 3.3 V
Figure 6. Dropout Voltage vs. Temperature –
VOUT = 1.2 V
240
325
VOUT = 1.8 V
IOUT = 1.2 A
COUT = 10 mF
220
VOLTAGE DROPOUT (mV)
VOLTAGE DROPOUT (mV)
40
Figure 3. Output Voltage vs. Temperature –
VOUT = 1.2 V
3.300
275
20
TEMPERATURE (°C)
3.305
300
0
TEMPERATURE (°C)
VOLTAGE DROPOUT (mV)
OUTPUT VOLTAGE (V)
3.315
1.805
1.785
1.185
3.320
1.810
VIN = 2.8 V
IOUT = 1 mA
COUT = 10 mF
250
225
200
175
150
125
100
75
−40 −20
0
20
40
60
80
100
120
200
VOUT = 3.3 V
IOUT = 1.2 A
COUT = 10 mF
180
160
140
120
100
80
60
40
−40 −20
140
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Dropout Voltage vs. Temperature –
VOUT = 1.8 V
Figure 8. Dropout Voltage vs. Temperature –
VOUT = 3.3 V
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NCV8187
TYPICAL CHARACTERISTICS
3.0
36
VOUT = nom.
IOUT = 0 mA
COUT = 10 mF
34
32
30
28
26
24
22
20
−40 −20
CURRENT LIMIT (mA)
1950
1900
0
20
40
60
80
100
120
2.6
VOUT = nom.
IOUT = 1.2 A
COUT = 10 mF
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
−40 −20
140
0
20
40
60
80
100
120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Quiescent Current vs. Temperature
Figure 10. Ground Current vs. Temperature
0.80
VOUT = nom.
COUT = 10 mF
0.75
ENABLE THRESHOLD (V)
2000
1850
1800
1750
1700
1650
1600
1550
1500
−40 −20
POWER GOOD THRESHOLD (%)
2.8
GROUND CURRENT (mA)
38
0.70
Output ON
0.65
0.60
Output OFF
0.55
0.50
0.45
0
20
40
60
80
100
120
0.40
−40 −20
140
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Current Limit vs. Temperature
Figure 12. Enable Thresholds vs. Temperature
96
135
94
134
VOUT = rising
to nominal
92
ACTIVE DISCHARGE (W)
QUIESCENT CURRENT (mA)
40
90
88
86
VOUT = falling
from nominal
84
82
80
−40 −20
0
20
40
60
80
100
120
133
EN = low
COUT = 10 mF
132
131
130
129
128
127
126
125
−40 −20
140
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Power Good Thresholds vs.
Temperature
Figure 14. Active Discharge Resistance vs.
Temperature
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NCV8187
TYPICAL CHARACTERISTICS
NOISE SPECTRAL DENSITY (nV/√Hz)
100
90
80
PSRR (dB)
70
60
50
40
30
20
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.01
0.1
1
10
100
1k
10k
10
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 15. Power Supply Rejection Ratio
for VOUT = 1.8 V, IOUT = 10 mA, COUT = 10 mF
Figure 16. Output Voltage Noise Spectral Density
for VOUT = 1.8 V, IOUT = 10 mA, COUT = 10 mF
IOUT
10 mA
IOUT
500 mA
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
3.6
3.3
3.0
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6 IOUT
IOUT
10 mA
0.3
500 mA
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 17. Output Voltage vs. Input Voltage,
VOUT = 1.2 V
Figure 18. Output Voltage vs. Input Voltage,
VOUT = 3.3 V
10000
GROUND CURRENT (mA)
10000
GROUND CURRENT (mA)
100
FREQUENCY (kHz)
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
10
0
1k
1000
100
10
0.001
0.01
0.1
1
10
100
1000
1000
100
10
0.001
0.01
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Figure 19. Ground Current vs. Output Current,
VOUT = 1.2 V
Figure 20. Ground Current vs. Output Current,
VOUT = 3.3 V
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NCV8187
TYPICAL CHARACTERISTICS
1.2025
IOUT
50 mA
500
450
400
350
300
250
200
150
100
IOUT
0.5 mA
50
0
−40
−20
0
20
40
60
25°C
1.2020
OUTPUT VOLTAGE (V)
GROUND CURRENT (mA)
600
550
85°C
1.2015
1.2010
150°C
1.2005
1.2000
1.1995
1.1990
−40°C
1.1985
80
100
120
1.1980
1.5
140
2.0
TEMPERATURE (°C)
Figure 21. Ground Current vs. Temperature
VOLTAGE DROPOUT (mV)
OUTPUT VOLTAGE (V)
85°C
3.300
3.298
150°C
3.296
−40°C
3.7
3.9
4.1
4.3
4.5
4.7
4.0
4.5
5.0
5.5
200
25°C
3.302
3.294
3.5
3.5
Figure 22. Line Regulation, VOUT = 1.2 V
220
3.304
3.0
INPUT VOLTAGE (V)
3.308
3.306
2.5
4.9
180
150°C
160
140
85°C
25°C
120
−40°C
100
80
60
40
20
5.1
5.3
5.5
00
0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
INPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Figure 23. Line Regulation, VOUT = 3.3 V
Figure 24. Dropout Voltage vs. Output Current,
VOUT = 3.3 V
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NCV8187
APPLICATIONS INFORMATION
Recommended operating current is between 10 mA and
1 mA to obtain low saturation voltage. External pull−up
resistor can be connected to any voltage up to 5.5 V (please
see Absolute Maximum Ratings table above).
The NCV8187 is the member of new family of high output
current and low dropout regulators which delivers low
quiescent and ground current consumption, good noise and
power supply ripple rejection ratio performance. The
NCV8187 incorporates EN pin and power good output for
simple controlling by MCU or logic. Standard features
include current limiting, soft−start feature and thermal
protection.
Power Dissipation and Heat Sinking
The maximum power dissipation supported by the device
is dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material, and the
ambient temperature affect the rate of junction temperature
rise for the part. For reliable operation junction temperature
should be limited to +125_C. The maximum power
dissipation the NCV8187 can handle is given by:
Input Decoupling (CIN)
It is recommended to connect at least 1 mF ceramic X5R
or X7R capacitor between IN and GND pin of the device.
This capacitor will provide a low impedance path for any
unwanted AC signals or noise superimposed onto constant
input voltage. The good input capacitor will limit the
influence of input trace inductances and source resistance
during sudden load current changes. Higher capacitance and
lower ESR capacitors will improve the overall line transient
response.
P D(MAX) +
ƪTJ(MAX) * TAƫ
(eq. 1)
R qJA
The power dissipated by the NCV8187 for given
application conditions can be calculated from the following
equations:
P D [ V INǒI GND(I OUT)Ǔ ) I OUTǒV IN * V OUTǓ
Output Decoupling (COUT)
The NCV8187 does not require a minimum Equivalent
Series Resistance (ESR) for the output capacitor. The device
is designed to be stable with standard ceramics capacitors
with values of 4.7 mF or greater. Recommended capacitor for
the best performance is 10 mF. The X5R and X7R types have
the lowest capacitance variations over temperature thus they
are recommended.
(eq. 2)
or
V IN(MAX) [
P D(MAX) ) ǒV OUT
I OUT ) I GND
I OUTǓ
(eq. 3)
Hints
VIN and GND printed circuit board traces should be as
wide as possible. When the impedance of these traces is
high, there is a chance to pick up noise or cause the regulator
to malfunction. Place external components, especially the
output capacitor, as close as possible to the NCV8187, and
make traces as short as possible.
Power Good Output Connection
The NCV8187 include Power Good functionality for
better interfacing to MCU system. Power Good output is
open collector type, capable to sink up to 10 mA.
www.onsemi.com
10
NCV8187
ADJUSTABLE VERSION
where VFIX is voltage of original fixed version (from 0.8 V
up to 5.2 V). Do not operate the device at output voltage
about 5.2 V, as device can be damaged.
In order to avoid influence of current flowing into SNS pin
to output voltage accuracy (SNS current varies with voltage
option and temperature, typical value is 300 nA) it is
recommended to use values of R1 and R2 below 500 kW.
Not only adjustable version, but also any fixed version can
be used to create adjustable voltage, where original fixed
voltage becomes reference voltage for resistor divider and
feedback loop. Output voltage can be equal or higher than
original fixed option, while possible range is from 0.8 V up
to 5.2 V. Picture below shows how to add external resistors
to increase output voltage above fixed value.
Output voltage is then given by equation:
V OUT + V FIX
(1 ) R1ńR2)
VIN
VOUT
IN
CIN
NCV8187 OUT
ADJ or FIX version
1 mF
Ceramic
EN
GND
R1
SNS
ON
R2
OFF
COUT
10 mF
Ceramic
Figure 25.
recommended to use as high fixed variant as possible – for
example in case above it is better to use 3.3 V fixed variant
to create 3.6 V output voltage, as output noise will be
amplified only 3.6/3.3 = 1.09 × (16.4 mVrms).
Please note that output noise is amplified by VOUT / VFIX
ratio. For example, if original 0.8 V fixed variant is used to
create 3.6 V output voltage, output noise is increased 3.6/0.8
= 4.5 times and real value will be 4.5 × 15 mVrms =
67.5ĂmVrms . For noise sensitive applications it is
www.onsemi.com
11
NCV8187
ORDERING INFORMATION
Voltage
Option
Marking
Option
Package
Shipping†
NCV8187AMT110TAG
1.1 V
PM
NCV8187AMT120TAG
1.2 V
PJ
With Active Output
Discharge
WDFN6 2x2 non WF
(Pb−Free)
3,000 /
Tape & Reel
NCV8187AMT180TAG
1.8 V
PK
NCV8187AMT330TAG
3.3 V
PL
NCV8187AMN120TAG
1.2 V
NA
NCV8187AMN180TAG
1.8 V
NH
With Active Output
Discharge
DFN6 3x3 non WF
(Pb−Free)
3,000 /
Tape & Reel
NCV8187AMTWADJTAG
ADJ
K2
NCV8187AMTW080TAG
0.8 V
KG
With Active Output
Discharge
WDFNW6 2x2 WF SLP
(Pb−Free)
3,000 /
Tape & Reel
NCV8187AMTW090TAG
0.9 V
KH
NCV8187AMTW110TAG
1.1 V
KM
NCV8187AMTW180TAG
1.8 V
KJ
NCV8187AMTW330TAG
3.3 V
KK
NCV8187AML120TAG
1.2 V
WD
NCV8187AML180TAG
1.8 V
WE
With Active Output
Discharge
DFNW6 3x3 WF SLP
(Pb−Free)
3,000 /
Tape & Reel
NCV8187AMLE120TCG
1.2 V
CA
NCV8187AMLE180TCG
1.8 V
CC
With Active Output
Discharge
DFNW8 3x3 WF
(Pb−Free)
3,000 /
Tape & Reel
NCV8187AMLE280TCG
2.8 V
CE
NCV8187AMLE330TCG
3.3 V
CD
NCV8187AMLEADJTCG
ADJ
C2
NCV8187ADT180RKG*
1.8 V
V8187BG
NCV8187ADT330RKG*
3.3 V
V8187CG
With Active Output
Discharge
DPAK−5
(Pb−Free)
2,500 /
Tape & Reel
NCV8187ADTADJRKG*
ADJ
V8187AG
Device Part No.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*Package in development.
www.onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK−5, CENTER LEAD CROP
CASE 175AA
ISSUE B
DATE 15 MAY 2014
SCALE 1:1
−T−
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
R1
Z
A
S
12 3 4 5
U
K
F
J
L
H
D
G
5 PL
0.13 (0.005)
M
T
2.2
0.086
0.34 5.36
0.013 0.217
5.8
0.228
10.6
0.417
0.8
0.031
SCALE 4:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON12855D
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.020 0.028
0.018 0.023
0.024 0.032
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.045 BSC
0.170 0.190
0.185 0.210
0.025 0.040
0.020
−−−
0.035 0.050
0.155 0.170
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.51
0.71
0.46
0.58
0.61
0.81
4.56 BSC
0.87
1.01
0.46
0.58
2.60
2.89
1.14 BSC
4.32
4.83
4.70
5.33
0.63
1.01
0.51
−−−
0.89
1.27
3.93
4.32
GENERIC
MARKING DIAGRAMS*
RECOMMENDED
SOLDERING FOOTPRINT*
6.4
0.252
DIM
A
B
C
D
E
F
G
H
J
K
L
R
R1
S
U
V
Z
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DPAK−5 CENTER LEAD CROP
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFNW6 3x3, 0.95P
CASE 506DK
ISSUE A
1
SCALE 2:1
DATE 07 MAY 2021
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON12549G
DFNW6 3X3, 0.95P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFNW8 3x3, 0.65P
CASE 507AD
ISSUE A
1
SCALE 2:1
DATE 15 JUN 2018
A
B
D
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
L3
L
L
ALTERNATE
CONSTRUCTION
DETAIL A
E
PIN ONE
REFERENCE
EXPOSED
COPPER
DETAIL B
PLATING
A1
A4
A
ALTERNATE
CONSTRUCTION
DETAIL B
A3
C
C
0.05 C
NOTE 4
A4
C
SIDE VIEW
SEATING
PLANE
PLATED
SURFACES
D2
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. THIS DEVICE CONTAINS WETTABLE FLANK
DESIGN FEATURE TO AID IN FILLET FORMATION ON THE LEADS DURING MOUNTING.
A4
A1
TOP VIEW
0.05 C
L3
1
L3
SECTION C−C
4
DIM
A
A1
A3
A4
b
D
D2
E
E2
e
K
L
L3
GENERIC
MARKING DIAGRAM*
1
8X
L
E2
K
8
5
e/2
8X
0.05 C
NOTE 3
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
2.50
2.35
8X
0.58
8
5
1
4
XXXXXX
XXXXXX
ALYWG
G
XXXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
b
0.10 C A B
e
MILLIMETERS
MIN
NOM
MAX
1.00
0.80
0.90
−−−
−−−
0.05
0.20 REF
0.10
−−−
−−−
0.25
0.30
0.35
2.90
3.00
3.10
2.30
2.40
2.50
2.90
3.00
3.10
1.55
1.65
1.75
0.65 BSC
0.28 REF
0.30
0.40
0.50
0.05 REF
3.30 1.75
PACKAGE
OUTLINE
8X
0.65
PITCH
0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON17792G
DFNW8 3x3, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFNW6 3X3, 0.95P
CASE 507AW
ISSUE O
1
DATE 21 MAY 2019
EXPOSED
COPPER
GENERIC
MARKING DIAGRAM*
1
XXXXX
A
L
Y
W
G
XXXXX
XXXXX
ALYWG
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON07566H
DFNW6 3X3, 0.95P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN6 2x2, 0.65P
CASE 511BR
ISSUE B
ÉÉ
ÉÉ
ÇÇ
SCALE 4:1
D
A
B
A1
0.10 C
0.10 C
ALTERNATE B−1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND
IS MEASURED BETWEEN 0.15 AND 0.25 mm FROM
THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS
WELL AS THE TERMINALS.
5. FOR DEVICES CONTAINING WETTABLE FLANK
OPTION, DETAIL A ALTERNATE CONSTRUCTION
A-2 AND DETAIL B ALTERNATE CONSTRUCTION
B-2 ARE NOT APPLICABLE.
MOLD CMPD
ALTERNATE B−2
ALTERNATE
CONSTRUCTIONS
E
L
L
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
L1
TOP VIEW
ALTERNATE A−1
ALTERNATE A−2
DETAIL A
A3
DETAIL B
0.05 C
ÉÉ
ÉÉ
ÇÇ
EXPOSED Cu
DETAIL B
ÍÍÍ
ÍÍÍ
ÍÍÍ
PIN ONE
REFERENCE
A3
DATE 19 JAN 2016
ALTERNATE
CONSTRUCTIONS
A
6X
0.05 C
A1
NOTE 4
C
SIDE VIEW
D2
DETAIL A
1
3
SEATING
PLANE
GENERIC
MARKING DIAGRAM*
1
L
XX M
XX = Specific Device Code
M = Date Code
E2
6
4
6X
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
b
e
BOTTOM VIEW
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.25
0.35
2.00 BSC
1.50
1.70
2.00 BSC
0.90
1.10
0.65 BSC
0.20
0.40
--0.15
0.10
M
C A
0.05
M
C
B
RECOMMENDED
MOUNTING FOOTPRINT
NOTE 3
1.72
6X
0.45
1.12
PACKAGE
OUTLINE
6X
0.40
2.30
1
0.65
PITCH
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98AON55829E
WDFN6 2X2, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFNW6 2x2, 0.65P
CASE 511DW
ISSUE B
DATE 15 JUN 2018
SCALE 4:1
GENERIC
MARKING DIAGRAM*
XXMG
G
M
G
= Month Code
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON79327G
WDFNW6 2x2, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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